JPH03211654A - Data transfer control system - Google Patents

Abstract

PURPOSE:To increase a data transfer quantity per unit time to a prescribed rate compared to a conventional case by providing a system bus use request signal holding circuit for a master transferring data. CONSTITUTION:The system bus use request signal holding circuit 8 is provided for the master 2' which intends to increase the data transfer quantity per unit time to the prescribed rate. The circuit holds a system bus use request signal which a transfer control circuit 6' transmits at the prescribed timing of a data transfer cycle based on an output from the transfer control circuit 6' for a constant period. Thus, data is continuously transferred by using the constant period and the data transfer quantity per unit time is increased to the prescribed rate compared to the conventional case, whereby the occurrence of an overrun error is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transfer control system in electronic computers and the like.

(Prior Art) FIG. 2 is a block diagram showing an example of a conventional data transfer control system. In the figure, 1 is a system bus, and a master (A) 2 and a master (A) are connected to this system bus 1.
B) 3, memory 4, and system bus control circuit 5 are connected. Here, the master refers to a device that actively issues a bus request to an external bus arbitration circuit (for example, a DMA controller or a CPU).

Under such a configuration, conventionally, when both master (A) 2 and master (B) 3 always need to access memory by cycle steal transfer, first, master (A)
2. Each master (B) 3 requests permission to use the bus from the system bus control circuit 5. Next, the system bus control circuit 5
Either master that is permitted to use the system bus 1 can access the memory 4 once. When the memory access by one master is completed, the other master is controlled by the system bus control circuit 5 to
The use of the memory is permitted, and memory access can be performed at -degrees. In this way, accesses by master (A) 2 and master (B) 3 are alternately repeated once until the requested number of accesses is reached.

An example of conventional data transfer using such a method is shown in FIG.

In FIG. 3, when master (A) 2 is permitted to use system bus 1 by system bus control circuit 5 and performs data transfer (IA), master (B) 3 transfers data to system bus control circuit 5. The system bus 1 is permitted to be used and data transfer (IB) is performed. Similarly, the master (
After the data transfer (IB) of B) 3, the data transfer (2A) of master (A) 2 is performed, and so on.
2 and master (B) 3 are shown alternately transferring data.

(Problem to be Solved by the Invention) However, in the conventional data transfer control method described above, one master, for example, master (A) 2, performs a higher rate per unit time than the other master, for example, master (B) 3. ,
In the case of a system in which it is necessary to transfer more data, there is a drawback that the master (A) 2 cannot transfer the required amount of data, resulting in an overrun error.

SUMMARY OF THE INVENTION In view of these conventional drawbacks, an object of the present invention is to provide data transfer control that allows a master that transfers data to transfer the necessary amount of data and prevents overrun errors from occurring. The goal is to provide a method.

(Means for Solving the Problems) The present invention provides a system bus with a plurality of masters, a memory,
In a data transfer control method in which a system bus control circuit is connected and each master that transfers data obtains permission to use the system bus from the system bus control circuit and transfers data, the amount of data transferred per unit time is set at a predetermined rate. The master that wants to increase sends a system bus use request signal to the system bus control circuit, obtains permission to use the bus from the system bus control circuit, and transfers information from the transfer control circuit that controls data transfer and from this transfer control circuit. and a system bus use request signal holding circuit for holding the previous system path use request signal for a certain period of time at a predetermined timing based on the output of the system bus use request signal.

(Function) In the present invention, a master that wants to increase the amount of data transferred per unit time to a predetermined rate is provided with a system bus use request signal holding circuit. This system bus use request signal holding circuit can hold the system bus use request signal sent by the transfer control circuit for a certain period of time at a predetermined timing of the data transfer cycle based on the output from the transfer control circuit. Using this fixed period, a master who wants to increase the amount of data transferred per unit time by a predetermined percentage can transfer data continuously.

Therefore, a system bus use request signal holding circuit is installed in the master that transfers data! -J, it is possible to increase the rate of data transfer per unit time to a predetermined rate compared to the conventional method, and it is possible to prevent the occurrence of overrun errors.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data transfer control system according to the present invention. The numbers in the figure and t/'1 are the same or corresponding parts as in FIG. 2 (the same reference numerals are used here).

In FIG. 1, the master (B) 3 is composed of a transfer control circuit 6 and a bus interface 7, as in the prior art. In addition, the master (A) 2'& the bus interface 7' connected to the system bus 1, the transfer control circuit 6' connected to this bus interface 7', and the transfer control circuit 6' are reset. Signal -N (N is lycee
Indicates that the signal is active when the signal is negative. ),
Transfer permission signal ACK-P (P is transfer permission signal ACK
Indicates that it is active when is positive. The same applies to P below. ) and the bus request signal BR-P are supplied, and the system bus use request signal 5 is supplied to the bus interface 7.
It consists of a system bus use request signal holding circuit 8 that sends out a BUS BREQ signal. This system bus use request signal holding circuit 8 is a circuit for holding a system bus use request signal for a certain period of time at a predetermined timing of a data transfer cycle based on the output from the data transfer control circuit 6'. The bus use request signal holding circuit 8 is a circuit added in the present invention.

The system bus use request signal holding circuit 8 also includes an RS flip-flop 9, 10, an AND circuit 11, and a NOR circuit 1.
It is composed of 2. Here, the reset input terminal 100 of the RS flip-flop 9 is supplied with a reset signal -N from the transfer control circuit 6'. A clock input terminal C of the RS flip-flop 9 is supplied with a transfer permission signal ACK-P from the transfer control circuit 6'. The output terminal Q of the RS flip-flop 9 is connected to the clock input terminal C of the RS flip-flop 10 and one input terminal of the AND circuit 11. The output terminal of the RS flip-flop 9 is connected to the set input terminal S. A transfer control circuit 6 is connected to the reset input terminal R of the RS flip-flop 1o.
' is supplied with a reset signal -N. The output terminal of the RS flip-flop 1o is connected to the set input terminal S. The output terminal Q of the RS flip-flop 1o is connected to the other input terminal of the AND circuit 11. The output terminal of the AND circuit 11 is connected to one input terminal of the NOR circuit 12. The other input terminal of the NOR circuit 12 is supplied with a bus request signal BR-P from the transfer control circuit 6'. The output terminal of the NOR circuit 12 is the bus interface 7
'It is connected to the.

Next, the operation will be explained using FIG.

When the master (A) 2' transfers data, a bus request signal BR as shown in FIG. 4(a) is sent from the transfer control circuit 6'.
-P is supplied to the bus interface 7' via the NOR circuit 12 of the system bus use request signal holding circuit 8. The bus interface 7' is connected to the system bus 1 in FIG.
), the system bus request signal 5BUS BRE
Q Sends out an umbrella.

This system bus use request signal 5BUS BREIC is supplied to the system bus control circuit 5 via the system bus 1. In the system bus control circuit 5, the master (
When the system bus request by A) 2' is recognized, a transfer permission signal ACK-P is supplied from the system bus control circuit 5 to the transfer control circuit 6' via the system bus 1 and the bus interface 7'. As a result, master (A) 2'
This means that the use of system bus 1 is permitted. Then, the master (A) 2' performs data transfer (IA) based on permission to use the system bus 1, but the system bus use request signal holding circuit 8 retains the system bus use request signal 5BUS BREQ as shown in FIG. ) will remain retained as shown.

Here, based on the permission to use the system bus l, the system bus use request signal 5BUS BREQ*, which is the output of the system bus use request signal holding circuit 8, is held in a holding state as shown in FIG. 4(f). explain.

That is, the reset input terminal 100 of the RS flip-flop 9 is supplied with logic "1" (H level) as the reset signal -N, and the output of the output terminal q (input of the set input terminal S) is logic "1" ( H level), so the 4th
When the transfer permission signal ACK-P as shown in FIG. Logic “l” as shown in figure (C)
(H level) and is supplied to the clock input terminal C of the RS flip-flop IO and the AND circuit 11. Then, the output of the output terminal Q of the RS flip-flop 10 is as shown in FIG. 4(d) in the same manner as the RS flip-flop 9.
As shown in FIG. 2, the signal becomes logic "1" (H level) and is supplied to the AND circuit 11. Therefore, the output of the AND circuit 11 is logic "L" (H level) as shown in FIG. 4(e).
Therefore, the output of the NOR circuit 12 is logic “O” (L level)
Therefore, the bus request signal BR-P in FIG. 4(a)
Even if it turns off, the output of the NOR circuit 12 continues to be logic “O” (L level) based on the output of the AND circuit 11.
Therefore, the system bus use request signal 5BtlS 8
REQ* remains at the L level as shown in FIG. 4(f).

As can be seen from the above explanation, the system bus use request signal 5BUS BREQ* remains held even after the bus request signal BR-P turns off as shown in FIG. 4(f), so the master (A) 2 Master (A) 2' can use system bus 1, and after performing data transfer (IA), master (A) 2' can continuously perform the next data transfer (2A). As long as the system bus use request signal 5BUSBREQ (L level) is supplied to the system bus 1 from the master (A) 2', the master (B) 3 cannot use the system bus 1. After outputting the next bus request signal BR-P as shown in FIG. 4(a), the transfer control circuit 6' outputs the next transfer permission signal ACK-P as shown in FIG. 4(b).
).

Then, the output from the output terminal Q of the RS flip-flop 9 becomes logic "1" (H level) as shown in FIG. 4(C).
The logic becomes "0" (L level). Therefore, the output of the output terminal Q of the <RS flip-flop IO remains as it was, as shown in FIG. 4(d). However, AND circuit 1
The output of 1 is a logic “O” (L
level), so the output of the NOR circuit 12 is logic “1”
Therefore, the system bus use request signal 5BUS BREQ
The book is turned off (H level) as shown in FIG. 4(f).

Next, when the system bus use request signal 5BUS BREQ4 from the master (A) 2' turns off, the master (B)
A system bus use request signal based on the bus request signal BR-P from the system bus control circuit 5 is supplied to the system bus control circuit 5. Then, the system bus control circuit 5 issues a transfer permission signal ACK to permit the master (B) 3 to use the system bus l.
-P via the system bus 1. This results in
The master CB) 3 performs data transfer (IB) as before.

Thereafter, when the transfer control circuit 6' of the master (A) 2' outputs the bus request signal BR-P as shown in FIG. 4(a), the output of the NOR circuit 12 becomes logic "1" (H level)
becomes logic “0” (L level). That is, the system bus use request signal 5BuS BREQ* is as shown in FIG. 4(f).
G: Turns on as shown at 1m. When the system bus control circuit 5 grants the system bus use request from the master (A) 2', the transfer permission signal ACK-P is transmitted via the system bus 1 and the bus interface 7' of the master (A) 2'. The signal is supplied to the transfer control circuit 6'. Note that the transfer control circuit 6' receives the bus request signal BR as shown in FIG. 4(a).
-P, then sends a transfer permission signal ACK-P as shown in FIG. 4(b).

As a result, the output of the output terminal Q of the RS flip-flop 9 is inverted and becomes logic "1" as shown in FIG. 4(c), and therefore the output of the output terminal Q of the RS flip-flop 10 is As shown in (d), it is inverted and becomes logic "0". At this time, the output of the AND circuit 11 is logic “O” (
The output of the NOR circuit 12 remains at the logic “L level).
0" (L level). By the way, master (A) 2
When ' is permitted to use the system bus 1 by the system bus control circuit 5, the master (A) 2' performs data transfer (3A) while the system bus use request signal 5BIIS BREQ* is on.

Next, the system bus control circuit 5 grants permission to use the bus in response to the system bus use request signal 5susBREQ* from the master (B) 3. As a result, master (B) 3
performs data transfer (2B) in the same manner as described above.

Next, in the master (A) 2', the transfer control circuit 6'
sends the bus request signal BR-P to the NOR circuit 12 as shown in FIG. 4(a), and the output of the NOR circuit 12 is a logic "O".
(L level), and the system bus use request signal 5B
It is supplied to the system bus control circuit 5 via the bus interface 7' and the system bus 1 as US BREQ* (L level). Then, the system bus control circuit 5 grants permission to use the system bus 1 in response to the system bus use request from the master (A) 2'. The transfer control circuit 6' is
System bus control circuit 5 to system bus 1. It receives a transfer permission signal supplied via the bus 1 interface 7'. When master (A) 2' is permitted to use the system bar 21, master (A) 2' waits for data transfer (4A) as shown in Figure 4 (f). Note that the transfer control circuit 6
' is the transfer permission signal A after sending the bus request signal BR-P.
CK-P is sent as shown in FIG. 4(b). As a result, the output terminal from the output terminal Q of the RS flip-flop 9 is switched from logic "1" (H level) to "O" (L level) as shown in FIG. 4(C). The output from the output terminal Q of the RS flip-flop 10 and the output from the AND circuit 11 remain in the previous state as shown in FIGS. 4(d) and (e).

Next, the system bus control circuit 5 grants permission to use the bus in response to the system bus use request signal 5BUS 8REQs from the master (B) 3. As a result, master (B) 3 performs data transfer (3B) in the same manner as described above.

Thereafter, data transfer is repeated again from data transfer (IA) in the same manner as described above.

An example of data transfer by master (A) 2' and master (B) 3 explained above is shown in FIG. FIG. 2 is an explanatory diagram showing an example of data transfer.

FIG. 5 shows data transfer (I) when master (A) 2' first obtains permission to use system bus
A, 2A), then master (B) 3 data transfer (IB), then master (A) 2' data transfer (3)
A), master (B) 3 data transfer (2B), and so on until master (B) 3 data transfer (3B), and then again master (A) 2' data transfer (IA, 2A)
It shows how the cycle starts.

By doing the above, the transfer ratio of master (A) 2' and master (B) 3, which was previously 1:1, has been changed to 4=3
Therefore, the amount of data transferred by the master (A) per unit time can be increased compared to the conventional method. As a result, the master (A) (here, master (A) 2'), which previously could not transfer the required amount of data and caused an overrun error, now has an overrun error due to the increased amount of data transferred per unit time. can be prevented.

In this embodiment, when the master (A) 2' is allowed to use the system bus l at the beginning of a transfer cycle, the master (A) 2'
Although a method of forcibly performing two data transfers (continuous transfer) has been shown, the present invention is not limited to this, and the present invention is not limited to this, but can be applied to a system bus use request signal holding circuit according to the required performance of the master (A) 2'. By adding 8, the master (A)
By changing the transfer ratio between master (A) 2' and other master (B) 3, it is possible to increase the amount of data transferred per unit time of master (A) 2' to a predetermined rate.

Furthermore, in this embodiment, although the master (A) 2' is provided with the system bus use request signal holding circuit 8,
The present invention is not limited to this, but the master (B) 3 is similarly provided with a system bus use request signal holding circuit, and the transfer ratio between the master (B) 3 and other masters (A) is changed. B) The amount of data transferred per unit time of 3 can be increased to a predetermined rate.

In addition, in this embodiment, two masters (master (A
) 2' and master (B) 3), the present invention is not limited thereto, and can of course be similarly applied to data transfer between a plurality of masters.

(Effects of the Invention) As described above, by using the present invention, the master that transfers data can increase the amount of data transferred per unit time by a predetermined ratio compared to the conventional method by providing a system bus use request signal holding circuit. Therefore, it is possible to prevent overrun errors as in the conventional case.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer control method according to the present invention, FIG. 2 is a block diagram showing an example of a conventional data transfer control method, and FIG. 3 is a block diagram showing an example of a conventional data transfer method. The explanatory diagram, FIG. 4, is a master (A
) 2', and FIG. 5 is an explanatory diagram showing an example of data transfer according to the present invention. 1... System bus, 4... Memory, 5... System bus control circuit, 6.6'... Transfer control circuit, 7.7'... Bus interface, 8... System bus use Request signal holding circuit.

Claims (1)

[Claims] A plurality of masters, a memory, and a system bus control circuit are connected to a system bus, and each master that transfers data obtains permission to use the system bus from the system bus control circuit to transfer data. In the transfer control method, a master that wants to increase the amount of data transferred per unit time to a predetermined rate sends a system bus use request signal to the system bus control circuit and obtains bus use permission from the system bus control circuit. and a system bus use request signal holding circuit for holding the system bus use request signal for a certain period of time at a predetermined timing based on the output from the transfer control circuit. A data transfer control method characterized by: