JPH03211732A - Forming method for wiring - Google Patents

Abstract

PURPOSE:To increase the thickness of a wiring by selectively forming a resist layer and an insulating layer on a conductive layer on a semiconductor substrate, and forming a wiring on a part not formed with the resist layer and the insulating layer on the conductive layer by a plating method with the conductive layer as a cathode. CONSTITUTION:Metal layers 12 are sequentially formed of Ti, Pt, Au on an entire semiconductor substrate 10. The entire substrate 10 is coated several times with photoresist to form a thick resist film, an SiO2 insulating film 14 is formed on the resist film 13, a photoresist layer 15 is further formed thereon, and the layer 15 is so patterned as to etching the film 14 of the part corresponding to the window 11a of a protective resist film 11 formed previously. With the layer 15 as a mask the film 14 is etched, a window is opened, the film 13 of a lower layer is then etched to form a groove 16. The entire substrate is dipped in gold plating solution, a voltage is so applied that the film 12 becomes a cathode, and the Au is selectively grown on the exposed part of the cathode metal film.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming wiring, and more particularly to a method for forming wiring using a plating method.

[Conventional technology]

2. Description of the Related Art When forming a semiconductor device, especially an integrated circuit, a wiring process is performed to electrically connect each circuit element. Conventionally,
To form wiring, a resist layer with a desired pattern is deposited on a semiconductor substrate, and then a conductive layer for wiring is formed over the entire semiconductor substrate by vapor deposition, sputtering, etc., and the resist layer is removed. Therefore, a milling method is used, in which a conductive layer for wiring is first formed on the entire semiconductor substrate by evaporation or sputtering, and then a desired pattern is formed by ion milling. There is.

[Problem to be solved by the invention] In recent years, integrated circuits that process high-frequency signals have adopted low-resistance metals such as gold (Au) and platinum (PT) as wiring metals in order to reduce transmission loss. Furthermore, it has been found that it is preferable to increase the metal film thickness of the wiring metal. However, in the above lift-off method, the metal film thickness of the wiring layer is reduced to 1.5 μm.
In addition, with the milling method, increasing the thickness of the formed conductive layer increases the ion milling time and damages the resist used as a mask, so the thickness of the conductive layer that can be formed is only 2. The thickness was limited to about 2.5 μm.

On the other hand, as explained above, transmission loss of high frequency signals, particularly conductor loss, depends on the resistivity and thickness of the wiring. For example, if Au is used for wiring, the thickness should be 3 to 4 μm.
It is necessary to make it about m. In addition, in the lift-off method and milling method, a conductive layer is formed on the entire semiconductor substrate,
Since the wiring is formed by removing the unnecessary parts, the thicker the wiring, the more metal layers there are in the unnecessary parts, increasing the manufacturing cost.

Therefore, an object of the present invention is to provide a method for forming wiring that solves the above-mentioned problems.

[Means to solve the problem]

The wiring forming method of the present invention includes forming a conductive layer on a semiconductor substrate, selectively forming a resist layer and an insulating layer on the conductive layer, and using the conductive layer as a negative electrode, resist on the conductive layer. The method is characterized in that wiring is formed by a plating method on a portion where the layer and the insulating layer are not formed.

[Effect]

In the wiring forming method of the present invention, a thick resist film is selectively formed on a thinly formed conductive layer, and the wiring is formed by a plating method using the conductive layer as a negative electrode. Therefore, the thickness of the wiring can be increased by the thickness of the formed resist film, and a wiring layer with a desired thickness can be formed.

Additionally, since plating is used, there are no unnecessary parts to remove, and the amount of wiring material can be kept to a minimum.

〔Example〕

Embodiments according to the present invention will be described below with reference to the drawings.

Elements with the same reference numerals have the same functions, so duplicate explanations will be omitted.

FIG. 1 schematically shows the steps of an embodiment of the wiring forming method according to the present invention, and FIG. 2 shows the cross-sectional structure of the semiconductor device during each step shown in FIG.

As shown in FIG. 1, the wiring forming method of the embodiment includes a protective resist film forming step 1, a negative electrode metal film forming step 2,
The process includes a resist thick film forming step 3, a resist thick film buttering step 4, a resist thick film etching step 5, a plating step 6, and a metal film/protective resist removing step 7.

Each of the above steps will be explained below.

First, in the protective resist film forming step 1, wiring is selectively formed on a semiconductor substrate, for example, a semi-insulating GaAs substrate 10 (3,1-GaAs), as shown in FIG. 2(a). A window is opened in the portion 11a to be formed, and the photoresist 11 is patterned. This photoresist 11 later functions as a film that protects the semiconductor substrate when a metal layer formed thereon is removed by ion milling.

In the negative electrode metal film forming step 2, a metal layer 1 of Ti, Pt, and Au is formed over the entire semiconductor substrate 10 created in the previous step 1.
2 to 1000 to 2000 by vapor deposition method or sputtering method, etc.
It is formed to a thickness of about angstroms. This state is shown in FIG. 2(b).

As shown in FIG. 1(a), the metal layer 12 contacts the surface of the semiconductor substrate 10 at the window 11a of the resist film 11. As shown in FIG. Here, this metal layer 12 functions as a plating electrode during plating in plating step 6, which is a later step. Also,
Here, the thin film of Au is formed on the top layer of the metal layer 12 because Au is plated in the plating step 6.
This is to facilitate the growth of .

In the resist thick film forming step 3, a spinner is used to coat the entire semiconductor substrate with photoresist several times to form a resist thick film. The thickness of this resist thick film may be approximately 1 μm thicker than the thickness of the wiring to be formed. Then, on this resist thick film 13, an SiO3 insulating film 14 is formed by sputtering or the like, and a photoresist layer 15 is further formed on top of the insulating film 14 to form a window of the previously formed protective resist film 11. 11. The photoresist layer 15 is patterned so that the portion of the 5102 film 14 corresponding to a can be etched. Patterning of this photoresist layer 15 can be easily performed using conventional photolithography techniques.

Here, the material of the insulating film formed on the resist thick film 13 is not limited to SiO2, and various materials can be used, but reactive ion etching (hereinafter referred to as
It is preferable that the material has a high selectivity with respect to the photoresist layer 15 in RIE (referred to as RIE).

In the resist thick film etching step 5, first, using the photoresist layer 15 as a mask, CF4 is etched using an RIE device.
While flowing gas, the S102 film 14 is etched to open a window, and then, while flowing O2 gas, the underlying thick resist film 13 is etched to form grooves 16 as shown in FIG. 2(e). .

Next, in plating step 6, the entire semiconductor substrate created in the previous step is immersed in a gold layer plating solution, and a voltage is applied so that the negative electrode metal film 12 formed in the previous step 2 becomes a negative electrode.
is selectively grown on the exposed portion of the metal film for the negative electrode.

Here, as this month's plating solution, a plating solution conventionally used for plating gold can be used. After gold has grown to a desired thickness, plating is stopped and the thick resist film 13 is removed. During this removal, S i
The O2 film 14 is also removed at the same time by lift-off. Then, as shown in FIG. 2(f), a wiring layer 17 of Au is formed.

In the metal film/protective resist film removal step 7, first, unnecessary portions of the negative electrode metal film 12 formed in the previous step 2, that is, portions other than the lower part of the wiring layer 17, are removed by ion milling. During this removal, the wiring layer 17 is also etched, but the amount removed is only about 0.2 .mu.m compared to the wiring layer .mu.m.

Further, in this ion milling, since the surface of the semiconductor substrate 10 is covered with the protective resist film 11 and the wiring layer 17, damage to the semiconductor substrate due to ion milling can be prevented. Furthermore, after the negative electrode metal film 12 has been removed, the protective resist is removed in 02 Ashing! 111 is removed. This state is shown in FIG. 2(g).

The present invention is not limited to the above embodiments, and various modifications may be made.

Further, in the above embodiment, the wiring layer is formed of Au, but the wiring layer is not limited to this material, and may be formed of any material, such as Al1, as long as it can be plated with low resistance. .

Further, in the above embodiment, a protective resist film is formed to prevent damage to the semiconductor substrate due to ion milling during metal film removal, but even if such a protective resist film is not provided, the damage to the semiconductor substrate can be prevented. Any method may be used as long as damage can be prevented.

Furthermore, in the above embodiment, as the metal film for the negative electrode, Pt,
Although the material used is Ti, it is not limited to this, but any material can be used as long as it is a material with low resistance and is compatible with the characteristics of the semiconductor device to be manufactured. You can. In addition, A
Although a thin film of U is formed, this is to facilitate the growth of Au during gold plating to be performed later, and there is no need to provide such a thin film.

〔Effect of the invention〕

By using the wiring forming method of the present invention, thick wiring layers can be easily formed, as described above.
It becomes possible to form wiring with low resistance and excellent high frequency characteristics in a semiconductor device.

Furthermore, by using this wiring formation method, wiring material is not wasted, and the manufacturing cost of the semiconductor device can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing schematic steps of an embodiment of the wiring forming method according to the present invention, and FIG. 2 is a diagram showing a cross-sectional structure of a semiconductor device in each step shown in FIG. 1. 1 10... Semiconductor substrate, 11... Protective resist film, 2
...Metal film for cathode, 13...Resist thick film, 4.
... Insulating film, 15... Photoresist layer, 6... Groove, 17... Wiring layer.

Claims (1)

[Claims] 1. A step of forming a conductive layer on a semiconductor substrate, a step of forming a resist layer on the conductive layer, a step of forming an insulating film on the resist layer, and a step of forming the insulating layer on the conductive layer. selectively forming a resist layer on the film; selectively etching the insulating film and the resist using the resist layer as a mask; and forming the resist layer on the conductive layer using the conductive layer as a negative electrode. A method for forming wiring, which includes the step of growing metal by plating on the unused parts.