JPH03211766A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To micronize each element by forming the gate electrode layer and the contact layer of a MOS transistor and the emitter electrode layer and the base electrode layer of an NPN transistor at the same time in a self alignment manner. CONSTITUTION:The gate electrode of a MOS transistor and the emitter electrode of a bipolar transistor are formed. Phosphorus 109 is implanted, and an silicon oxide film is accumulated, and is etched, and the first silicon oxide layer 118 and, at the side of the first polysilicon layer, a wall body 110 are formed. Next, the second polycrystalline silicon 121 is stacked, and the source and the drain regions 113 of the MOS transistor are bored, and phosphorus is implanted, and a necessary area is bored, and B is implanted. The phosphorus is activated and also boron is diffused into the base of an NPN transistor, whereby the electrode lead-out diffusion layer 112 from the base layer of the NPN transistor and the source and the drain diffusion areas 111 of an N channel MOS transistor are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device in which an MO8 type semiconductor device and a bipolar type semiconductor device are mixed on the same substrate.

[Prior art] Vertical NPN bipolar transistor and N-channel M
FIG. 2 shows an example of a conventional method for manufacturing a semiconductor device in which an OSFET and an OSFET are formed on the same substrate.

On the main surface of the P-type semiconductor substrate 100, an N-type diffusion layer (N-well layer) 101. A P-type well layer 102 and a base diffusion layer 103 serving as a base region of an NPN transistor are formed, and 104 is a thick oxide film for element isolation. Thereafter, gate oxidation was performed to form a gate oxide film 105 with a thickness of about 10 nm to 200 nm. (FIG. 2(a)) After this, after removing the gate oxide film on the region that will become the emitter and collector of the N I-transistor, it is also used as the gate electrode layer 106 of the N-type MOS transistor. NPN) - A first polycrystalline silicon was deposited as the emitter electrode layer 107 and the collector electrode 1108 of the Lancistor, and then N was deposited in the first polycrystalline silicon.
A type impurity such as P (phosphorus) is ion-implanted, and the phosphorus is activated in a nitrogen gas atmosphere at 1000 degrees Celsius, and the NP
An NPN bipolar transistor structure was formed by diffusing phosphorus into the emitter open L1 portion of the N transistor and the opening region for leading out the collector electrode.

Thereafter, after photo-etching the first polycrystalline silicon to form a desired pattern, for example, an N-type MOS 1-
LDI Run Sister) (Lightly Dope)
d Drain) structure, phosphorus 109 is changed to 80
Kev acceleration energy is 2xlQI3 [pcs/cm”]
Injected. After this, a silicon oxide film is deposited to a thickness of 400 nm, and RIE (Reactive Ion Et.
The silicon oxide layer was etched using the etch method to form a wall body 110 made of a silicon oxide film on the side wall of the first polycrystalline silicon layer. (Fig. 2(b)) After this, phosphorus is applied to the source and drain regions 111 of the MOS transistor in an 8×10
” [pieces/cm2], 50 keys of boron is added to the region 112 that makes contact with the outside in the base region of the NPN transistor.
8xlOI5[/Cm21] were each injected with an acceleration energy of . Thereafter, wiring layers and the like were formed to complete the process. (Figure 2 (C)) [Problem to be solved by the invention] In the case of semiconductor devices configured by mixing bipolar elements and MO8 elements, it is important to increase the speed, and for this purpose, it is necessary to improve the speed of each semiconductor device. It is essential to miniaturize elements.

Furthermore, since bipolar elements and MO8 elements must be formed on the same substrate, the number of steps is inevitably increased compared to a process that only forms MOS transistors, which increases wafer costs and ultimately increases the cost of chips. Although the unit price will also increase, it is expected that the increase in chip cost can be kept to a minimum by advancing the miniaturization of elements. However, in a MOS transistor constructed using a conventional semiconductor device manufacturing method, the gate electrode layer 107 and the contact hole 1
16, depending on the accuracy limit of the aligner, at least 1
．． Similarly, NPN required an alignment margin of 3 μm.
) - An alignment margin of 1.3 μm was also required between the contact hole between the emitter electrode layer 107 of the Lancistor and the base. The alignment margins in both these MOS transistors and bipolar transistors have hindered miniaturization of elements.

Therefore, the present invention attempts to solve such problems, and its purpose is to simultaneously form the gate electrode layer and contact hole of a MOS transistor, and the emitter electrode layer and base electrode layer of an NPN transistor with a self-alignment line. By forming these elements, each element can be miniaturized.

[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes at least the following steps in a method for manufacturing a semiconductor device in which a MOS type semiconductor device and a bipolar type semiconductor device are mixed on the same semiconductor substrate. A step of forming a gate insulating film on a semiconductor substrate of a first conductivity type, a step of partially removing the gate insulating film, an impurity of the first conductivity type, an impurity of the second conductivity type, or an impurity of both conductivity types. a step of depositing a first electrode layer film containing impurities; a step of patterning the first electrode layer film; a step of oxidizing the semiconductor substrate to form a second insulating layer around the first electrode layer film; forming a wall made of an insulator on the sidewalls of the first gate electrode layer and the second insulating layer to partially expose the semiconductor substrate; a step of depositing a second electrode layer film containing impurities of a substance or both conductivity types; a step of extending and patterning the second electrode layer film on a second insulating film layer on the first electrode layer; [Example] The method for manufacturing a semiconductor device of the present invention will be described in detail below.

FIG. 1 shows an embodiment of a method for manufacturing a semiconductor device according to the present invention. Vertical NPN bipolar transistor and N
This is an example of a method for manufacturing a semiconductor device in which a channel MOSFET and a channel MOSFET are formed on the same substrate.

Of course, it is also possible to manufacture a PNPN bipolar transistor, a P-channel MOSFET, or a combination of these.

As a semiconductor substrate, for example, a P-type silicon substrate 100 has an N-type diffusion layer (N-well layer) 101, a P-type well layer 102, and a base diffusion layer 103, which becomes a base region of an NPN transistor, formed on the main surface of the semiconductor substrate 104. is a thick oxide film for element isolation.

Thereafter, gate oxidation was performed in a dry oxygen atmosphere at 1000 DEG C. to form a gate oxide film 104 with a thickness of about 5 nm to 1100 nm. (FIG. 1(a)) After this, after removing the gate oxide film on the region that will become the emitter and collector of the NPN I-transistor, Nf! :! MOS) The first polycrystalline silicon 105 is used as the gate electrode layer 106 of the transistor, and also as the emitter electrode layer 107 of the NPN transistor and, if necessary, the collector electrode layer 108.
CVD (Chemical VaporD)
Next, an N-type impurity such as P (phosphorus) was ion-implanted into the first polycrystalline silicon. Further, phosphorus in the first polycrystalline silicon is activated in an oxygen gas atmosphere at 1000°C, and phosphorus is diffused from the first polycrystalline silicon into the emitter region of the NPN transistor to form Nl)N.
An emitter diffusion layer 119 of a bipolar transistor was formed. At this time, a silicon oxide film is formed around the first polycrystalline silicon to a thickness of approximately 50 ohm to 500 nm. Thereafter, the silicon oxide film (118) and the first polycrystalline silicon were photo-etched to form a desired pattern. The etching conditions at this time were CF4 101005
The e-pressure was 0.2 Torr, and the RF power was 250 Ω. In this way, the gate electrode of the MOS transistor, the emitter electrode of the bipolar transistor, and the collector electrode of the bipolar transistor were formed as necessary. After this, for example, the N-type MOS transistor is
n) In order to obtain a structure, 2×1013 [pieces/cm2] of [109] were implanted at an acceleration energy of 80 keys. After this, a 400 nm silicon oxide film was deposited and RIE
The silicon oxide layer was etched by a (reactive ion etching) method to form walls (so-called sidewalls) 11o made of a silicon oxide film on the side walls of the first silicon oxide layer and the first polycrystalline silicon layer. This step also removes the gate oxide 1!104 under the first polycrystalline silicon layer and under the sidewalls. By this step, the first polycrystalline silicon is completely covered with the silicon oxide film layer. (FIG. 1(b)) Next, the second polycrystalline silicon 121 is
D (Chemical Vapor Depo
The second polycrystalline silicon is deposited to a thickness of about 400 nm using a photolithography method, and then holes are formed in necessary regions such as the source and drain regions 113 of the MOS transistor and wiring layers, and an N-type impurity such as P is deposited in this second polycrystalline silicon. (phosphorus) was ion-implanted at 8×1015 [1/cm21] with an acceleration energy of 80 keys. Further, by photolithography, holes are formed in necessary areas such as the electrode lead-out region 112 from the base region of the bipolar transistor, and furthermore, in the wiring layer, and a P-type impurity such as B (boron) is accelerated to 40 Ke in this second polycrystalline silicon. Ions were implanted at an energy of 8xlO'' [17cm2].

Further, phosphorus in the second polycrystalline silicon is activated in a nitrogen gas atmosphere at 1000°C, and boron is diffused from the second polycrystalline silicon into the base region of the NPN transistor to lead out the electrode from the base layer of the NPN bipolar transistor. A diffusion layer 112 and source and drain diffusion regions 111 of an N-channel MO8 transistor were formed.

Thereafter, the second polycrystalline silicon was photo-etched to form a desired pattern. Then, wiring layers and the like were formed to complete the process. (Fig. 1 (C)) Although this embodiment has been described with reference to the case where the bipolar transistor is a vertical 4NPN bipolar transistor, the present invention can also be applied to the case of a horizontal bipolar transistor, and furthermore, the present invention can be applied to the case of a horizontal bipolar transistor. It can also be applied when bipolar transistors are mixed on the same substrate, or when all of these are mixed, by replacing the impurity types.

Furthermore, although polycrystalline silicon was used as the electrode layer in this embodiment, polycide (MoSi2. Ti S j2.
WS i2s etc.) structure, salicide structure,
Alternatively, it may be only a metal layer.

Further, in this embodiment, an example is shown in which the first polycrystalline silicon layer is manufactured to serve as the gate electrode layer of the MOS transistor and the emitter electrode layer of the bipolar transistor, but as another example, the first polycrystalline silicon layer The layer is MOS
The second layer is formed to serve as the gate electrode layer of the transistor and the base electrode extraction layer of the bipolar transistor.
The polycrystalline silicon layer serves as the source of the MOS transistor,
A manufacturing method may also be used in which the drain region electrode extension layer is formed to serve as the emitter layer and emitter electrode extension layer of a bipolar transistor.

[Effects of the Invention] As described above, according to the present invention, the gate electrode, source and drain regions of a MOS transistor, and the emitter electrode and base electrode of a bipolar transistor can be formed as self-lined lines. - The device area of the transistor could be reduced by 20% compared to the device area by conventional manufacturing methods.

[Brief explanation of drawings]

FIGS. 1(a) to 1(c) are diagrams showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 2(a) to 2(C) are diagrams showing an example of a conventional method for manufacturing a semiconductor device. 101... P-type semiconductor substrate 102... P-type well layer 103... N-type well layer 104... Element isolation oxide film 105... Gate oxide film 106... Gate electrode layer 107... Emitter electrode layer 108...Collector electrode waste 109...Phosphorus ions 110...Side wall 111...Source and drain diffusion layer 112...Base electrode extraction region 113...Emitter electrode extraction diffusion layer region 114・・・
- Collector electrode extraction region 15 16 17 18 19 21 - Interlayer insulating film, contact hole, aluminum wiring layer, first silicon oxide layer, emitter diffusion layer, second polycrystalline silicon layer and above

Claims (1)

[Claims] In a method of manufacturing a semiconductor device in which a MOS type semiconductor device and a bipolar type semiconductor device are mixed on the same semiconductor substrate, at least a gate insulating film is formed on a first conductivity type semiconductor substrate. a step of partially removing the gate insulating film; a step of depositing a first electrode layer film containing impurities of the first conductivity type, impurities of the second conductivity type, or impurities of both conductivity types; a step of patterning the first electrode layer; a step of oxidizing the semiconductor substrate to form a second insulating layer around the first electrode layer; a step of forming a wall made of an insulator on the side wall and partially exposing the semiconductor substrate; a second electrode layer containing impurities of the first conductivity type, impurities of the second conductivity type, or impurities of both conductivity types; A method for manufacturing a semiconductor device, comprising the steps of: depositing a film; and patterning a second electrode layer by extending it over a second insulating film layer on the first electrode layer.