JPH03211775A - Manufacture of nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the density of memory cells by selectively remove the field oxide film around the portion to be designed as a source region of a memory transistor with a control gate used as a mask, and implanting impurity ions to form source and drain regions. CONSTITUTION:A field oxide film 2 around the portion for a source region 8 is masked by a control gate CG and selectively etched away. Accordingly, bird's beaks on the field oxide film 2 are removed, and in addition, the control gate CG and the field oxide film 2 are self-aligned. Masked by the control gate CG, the p-type silicon substrate 1 is heavily doped with an n-type impurity in the form of ions to form the source region 8 of the same width as the minimum rule on the source side. Therefore, the minimum rule on the source side can be reduced, and the area for memory cells is reduced accordingly. That is, the density of memory cell is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor nonvolatile memory having a memory transistor having a structure in which a control gate is stacked on a floating gate with an insulating film interposed therebetween.

[Summary of the invention]

The present invention has a memory transistor having a structure in which a control gate is stacked on a floating gate via an insulating film, and the floating gate and the control gate are formed in a self-aligned manner in the channel length direction of the memory transistor. In a method for manufacturing a memory, impurity ions are implanted to form a source region and a drain region after selectively removing a field oxide film around a portion that will become a source region of a memory transistor using a control gate as a mask. By doing so, it is possible to achieve a high integration density of memory cells.

Further, the present invention has a memory transistor having a structure in which a control gate is stacked on a floating gate with an insulating film interposed therebetween, and the floating gate and the control gate are formed in a self-aligned manner in the channel length direction of the memory transistor. A method for manufacturing a semiconductor nonvolatile memory includes a step of implanting ions of a first impurity at a low concentration into a semiconductor substrate in a portion that will become a source region and a drain region of a memory transistor using a control gate as a mask; A process of ion-implanting a second impurity at a high concentration into the semiconductor substrate, and forming sidewall spacers on the sides of the control gate and floating gate, and then using the sidewall spacers as a mask to form the parts that will become the source and drain regions. A process of implanting ions of a third impurity at a high concentration into the semiconductor substrate, thereby making it possible to prevent deterioration of the characteristics of the memory cell even when the memory transistor has an LDD structure. It is.

[Conventional technology]

Conventionally, as this type of semiconductor nonvolatile memory, E P
ROM (Erasable and Program
Mable Read Only Memory) is known. In recent years, in order to increase the integration density and improve the writing characteristics of EPROMs, the manufacturing method has been to use a double-self line (double cell line) in which the control gate and floating gate are formed in a self-aligned manner in the channel length direction of the memory transistor. Double 5el
A method called the f Align method is generally used.

FIG. 4 shows a plan view of a conventional EFROM manufactured using this double-self line method, and FIG.
It is an enlarged sectional view along the V line.

Referring to FIGS. 4 and 5, a method for manufacturing an EPROM using the double self-line method will be briefly explained as follows. That is, as shown in FIGS. 4 and 5,
First, a field oxide film 102 is selectively formed on the surface of a P-type silicon (Si) substrate 101 to isolate devices, and then a gate insulating film 103 is formed on the surface of the active region surrounded by this field oxide film 102. Form. Next, a -th layer polycrystalline Si film (not shown) is formed on the entire surface, and after doping the polycrystal 511g with an impurity such as phosphorus (P) to lower the resistance, the polycrystalline Si film 511g is A coupling insulating film 104 is formed on the film. Next, a resist pattern 105 having a shape as shown in FIG. 4 is formed on this coupling insulating film 104 by lithography. The width of this resist pattern 1050 is equal to the width of a floating gate FG', which will be described later, in the channel width direction of a memory (transistor).

Next, using this resist pattern 105 as a mask, the coupling insulating film 104 and the polycrystalline Si film of the negative layer are sequentially etched. Next, a second layer of polycrystalline Si film is formed on the entire surface, and this polycrystalline Si film is doped with an impurity such as P to lower the resistance. A resist pattern (not shown) having a shape corresponding to the shape of CG' is formed by lithography.

Next, using this resist pattern as a mask, the second layer polycrystalline Si film, the coupling insulating film 104, and the -th layer polycrystalline Si film are etched in a direction perpendicular to the substrate surface by, for example, reactive ion etching (RIE). Etch sequentially. As a result, the control gate CG' made of the second layer of polycrystalline Si film and the floating gate FC' made of the first layer of polycrystalline St film are formed in a self-aligned manner in the channel length direction of the memory transistor. Next, after removing the resist pattern, the control gate CG'
An insulating film 106 such as a SiO2 film is formed on the top and side surfaces of the floating gate FG' and the side surfaces of the floating gate FG'. Next, using this control gate CG' as a mask, p-type S
An n-type impurity such as arsenic (As) is ion-implanted into the t-substrate 101 at a high concentration.

As a result, for example, an n-type source region 107 and drain region 108 are formed in a self-aligned manner with respect to the control gate CG' and the floating gate FG'. Here, the source region 107 also serves as a source line.

C' indicates a contact hole for connecting a bit line (not shown) to the drain region 108.

Furthermore, Japanese Patent Application Laid-Open No. 163376/1983 discloses an EP which aims to increase the integration density of memory cells by forming floating gates and isolation regions in a self-aligned manner.
A method of manufacturing a ROM is disclosed.

[Problem to be solved by the invention]

In the conventional EFROM shown in FIGS. 4 and 5 described above, the minimum rule R on the source region 107 side is 2a+b. Here, a is the alignment margin (for example, 0.2 μm) with the field oxide film 102 in the lithography process for forming the control gate CG'.
This is the total dimension (for example, about 0.6 μm) of the length of the bird's beak at the end of the field oxide film 102 (for example, about 0.4 μm). Further, b is the width of the portion that actually becomes the source region 107. As EFROM becomes more highly integrated, b becomes smaller, for example, 1
1μ for megabit to 4 megabit EFROM
However, since a is determined by the alignment accuracy of the exposure apparatus and the bird's beak length of the field oxide film 102, it is approximately 0.
It is difficult to reduce the thickness to about 6 μm or less. Therefore, it has been difficult to further reduce the minimum rule on the source region 107 side, and therefore it has been difficult to achieve high integration density of memory cells.

On the other hand, the E
In the FROM manufacturing method, the first layer polycrystalline St film is etched using the resist pattern 105 shown in FIG. As described above, the width is predefined to be the same as that of the gate insulating film 103, and the thin gate insulating film 103 is exposed in the portion where the -th layer polycrystalline Si film is etched away. Since this exposed gate insulating film 103 is etched away at the same time as the coupling insulating film 104 formed on the -th layer polycrystalline Si film, the P-type Si substrate 101 is exposed at this portion. , during the next etching of the first polycrystalline St film, this part of the p-type St
The substrate 101 is etched and a step is formed (in FIG. 4, the etched region of the p-type Si substrate 101 is shaded).

For this reason, memory transistors are so-called LDD (L
In the case of an extremely doped drain structure, it becomes as shown in FIG. Here, Figure 6 is the fourth
This corresponds to an enlarged sectional view taken along line VI-VI in the figure. As shown in FIG. 6, in the memory transistor of this LDD structure, the lower side of the side wall spacer 109 formed on the side surface of the control gate CG' and the floating gate FG' among the source region 107 and the drain region 108 is An n-type low impurity concentration portion 107a is located in the portion.

108a is formed. In order to form a memory transistor with such an LDD structure, a control gate (CG) must be formed before forming the sidewall spacer 109.
' is used as a mask to ion-implant an n-type impurity such as P into the P-type Si substrate 101 at a low concentration, and then sidewall spacers 109 are formed. Using the sidewall spacers 109 as a mask, p-type Si substrate 101
For example, an n-type impurity such as As is ion-implanted into the substrate at a high concentration. In this case, sidewall spacers 1 are also provided on the side surfaces of the above-mentioned step portion felt on the surface of the P-type St substrate 101.
09 is formed, an n-1 low impurity concentration region 10 is formed under the sidewall spacer 109.
7aL will not be formed. However, the normal L
The sheet resistance of the n-type low impurity concentration region 107a in the DD structure memory transistor is about twice the sheet resistance of the n3-type source region 107. Therefore, the resistance of the source region 107 increases, and the drain current during reading increases. decrease in threshold voltage and shift amount Δ of threshold voltage during writing.
(2) There is a problem in that it leads to deterioration of the characteristics of the memory cell, such as a decrease in brightness.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor nonvolatile memory that can achieve high integration density of memory cells.

Another object of the present invention is to provide a method of manufacturing a semiconductor nonvolatile memory that can prevent deterioration of characteristics of memory cells.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a memory transistor having a structure in which a control gate (CG) is stacked on a floating gate (FG) via an insulating film (4). In a method for manufacturing a semiconductor nonvolatile memory in which a floating gate (FG) and a control gate (CG) are formed in a self-aligned manner in the channel length direction of a memory transistor, the control gate (CG) is used as a mask to form a memory transistor. After selectively removing the field oxide film (2) around the portion that will become the source region (8), impurity ions are implanted to form the source region (8) and drain region (9). ing.

Further, the present invention has a memory transistor having a structure in which a control gate (CG) is stacked on a floating gate (FC) via an insulating film (4), and the floating gate (FC) and the control gate (CC) are stacked. In a method of manufacturing a semiconductor non-volatile memory in which CG is formed in a self-aligned manner in the channel length direction of a memory transistor, a control gate (CG) is used as a mask to form a source region (8) and a drain region (9) of a memory transistor. a step of ion-implanting a first impurity at a low concentration into the semiconductor substrate (1); a step of ion-implanting a second impurity at a high concentration into a portion of the semiconductor substrate (1) that will become a source region; Sidewall spacers (
After forming the side wall spacer (12)
The source region (8) and drain region (9) are masked.
) of the semiconductor substrate (1) at a high concentration.

[Effect]

According to the method for manufacturing a semiconductor nonvolatile memory of the first invention configured as described above, the control game (CG)
) as a mask, the source region of the memory transistor (8
) Field oxidation II around the area where it becomes! (2)
This source region (8) by selectively removing
It is possible to remove the bird's beak part of the field oxide film (2) around the part that will become the control gate (CG) and the field oxide M (2) around the part that will become the source region (8). can be formed in a self-consistent manner. Therefore, by the subsequent ion implantation of impurities to form the source region (8) and drain region (9), the source region (8) can be formed to have the same width as the minimum rule on the source region side. . This makes it possible to further reduce the minimum rule on the source region side, so the memory cell
The area per memory cell can be reduced, and therefore the integration density of memory cells can be increased.

Further, according to the method for manufacturing a semiconductor nonvolatile memory of the second invention configured as described above, the control game) (
Forming a memory transistor with an LDD structure by ion implantation of a first impurity at a low concentration using the sidewall spacer (14) as a mask and ion implantation of a third impurity at a high concentration using the sidewall spacer (14) as a mask. I can do it.

In this case, sidewall spacers (
14), a floating gate (FC
A sidewall spacer (14) is also formed on the side surface of the step portion formed on the surface of the semiconductor substrate (1) during etching to form the step portion. 14), impurities are ion-implanted in advance at a high concentration into the semiconductor substrate (1) in the lower portion by a second impurity ion implantation performed at a high concentration. Therefore, the portion of the semiconductor substrate (1) below the sidewall spacer (14) formed on the side surface of this stepped portion also has a high impurity concentration, and therefore the source region (8) has a high impurity concentration everywhere. This makes it possible to prevent an increase in the sheet resistance of the source region (8), thereby preventing deterioration of the characteristics of the memory cell.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. The following examples are all examples in which the present invention is applied to manufacturing an EPROM using a double-self line method.

1A to 1C are EPROs according to an embodiment of the present invention.
Fig. 2 shows the manufacturing method of EPR according to this embodiment.
FIG. 2 is a plan view of an EPROM manufactured by the OM manufacturing method. Note that the cross sections shown in FIGS. 1A to 1C correspond to enlarged cross sections taken along line I-1 in FIG. 2.

In this embodiment, as shown in FIGS. 1A and 2, first, for example, the surface of a p-type Si substrate 1 is selectively thermally oxidized to form a field oxide film 2 to provide isolation between elements. After that, a gate insulating film 3 such as a SiO□ film is formed on the surface of the active region surrounded by the field oxide film 2 by, for example, thermal oxidation. Next, a first layer of polycrystalline St film is formed on the entire surface by CVD method, and this polycrystalline St film is doped with an impurity such as P to lower the resistance.
For example, by thermally oxidizing this polycrystalline Sf film, a coupling insulating film 4 such as a SiO□ film is formed on this polycrystalline Si film. Next, a resist pattern 5 having a shape as shown in FIG. 2 is formed on this coupling insulating film 4 by lithography. The width of this resist pattern 5 is equal to the width of a floating gate FG, which will be described later, in the channel width direction of a memory transistor. Next, by sequentially etching the coupling insulating film 4 and the -th layer polycrystalline St film using this resist pattern 5 as a mask, the width of the polycrystalline St film in the channel width direction is made the same as that of the floating gate FG. Specify the width in advance. Next, a second layer of polycrystalline Si is applied to the entire surface using the CVD method.
After forming the film, the polycrystalline Si film is doped with an impurity such as P to lower its resistance. Thereafter, a resist pattern (not shown) having a shape corresponding to the shape of a control gate CG to be described later is formed on this second layer polycrystalline Si film by lithography. Next, using this resist pattern as a mask, the second layer polycrystalline Si film, the coupling insulating film 4, and the -th layer polycrystalline Si film are sequentially etched in a direction perpendicular to the substrate surface by, for example, RIE.

As a result, the control gate CG made of the second layer of polycrystalline Si film and the floating gate FG made of the first layer of polycrystalline Si film are formed in a self-aligned manner in the channel length direction of the memory transistor. Note that as a material for the control gate CG, a polycide film in which a high melting point metal silicide film such as a tungsten silicide (WSiz) film is layered on a polycrystalline Si film doped with an impurity such as P may also be used. In this case, patterning is performed after forming a second layer of high melting point metal silicide film on the polycrystalline St peritoneum.

Next, after removing the resist pattern, a resist pattern 6 is formed by lithography in which a portion corresponding to the source region of the memory transistor is open.

In this case, both ends of this resist pattern 6 are located on the control gate CG.

Next, as shown in FIG. 1B and FIG. 2, for example, RIE
By performing etching using a method, field oxide film 2 is selectively removed using control gate CG as a mask. As a result, the bird's beak portion of the field oxide film 2 is removed, and the control gate CG
This portion of the field oxide film 2 is formed in a self-aligned manner.

In this case, the end surfaces of the control gate CG and the field oxide film 2 that are parallel to the longitudinal direction of the control gate CG coincide with each other. Note that it is preferable to minimize overetching during this etching. This is due to the fact that the selectivity of 5i02 to Si during this etching is not necessarily large enough, and the control gate CC made of polycrystalline Si film;
This is because the type Si substrate 1 may be etched.

Next, after removing the resist pattern 6, as shown in FIG. Form. Thereafter, by ion-implanting an n-type impurity such as As into the P-type Si substrate 1 at a high concentration using the control gate CG as a mask, for example n° The source region 8 and drain region 9 of the mold are connected to a control gate CG and a floating gate FG.
Formed in a self-consistent manner.

Thereafter, an interlayer insulating film, aluminum wiring (not shown), etc. are formed to complete the intended EPROM. Note that in FIG. 2, C indicates a contact hole for bringing a bit line (not shown) into contact with the drain region 9.

As described above, according to this embodiment, the field oxide film 2 in the periphery of the portion that will become the source region 8 is selectively etched and removed using the control gate CG as a mask, so that the bird's beak of the field oxide film 2 is removed. The control gate CG can be removed.
This field oxide film 2 can be formed in a self-aligned manner. And then the control gate CG
By ion-implanting n-type impurities at a high concentration into the p-type Si substrate l using as a mask, the source region 8 can be formed to have the same width as the minimum rule R on the source region side.

As a result, the minimum rule R on the source region side is reduced by 2a (see Fig. 4) compared to the conventional method, specifically, for example, 2X0.
．． It is possible to reduce the size by about 6 μm=1.2 μm.

As a result, for example, an EFR of 1 Mbit to 4 Mbit
In OM, the minimum rule R on the source region side, which was conventionally limited to about 2.2 μm, can be reduced to about 1 μm. Therefore, the area of the memory cell can be reduced by that amount, and therefore, the integration density of the memory cells can be increased.

Next, other embodiments of the present invention will be described.

This embodiment concerns the case where the memory transistor has an LDD structure.

FIGS. 3A to 3D illustrate a method of manufacturing an EPROM according to this embodiment. A plan view of EFROM0 manufactured by the EPROM manufacturing method according to this embodiment is the same as that shown in FIG. Note that the cross sections shown in FIGS. 3A to 3 correspond to the second enlarged cross section taken along the line ■-■.

In this example, the process is carried out in the same manner as in the above-mentioned example, and as shown in FIG. 3A and FIG. 2, the control gate CG and floating gate FC are formed in a self-aligned manner in the channel length direction. .

In this case, when etching the first polycrystalline Si film for forming the floating gate FG, the portion of the P-type Si substrate 1 that is not covered by the first polycrystalline Si film is etched, creating a step in this portion. It is formed. Next, 5 iOz is applied to the top and side surfaces of the control gate CG and the side surfaces of the floating gate (FC) by, for example, thermal oxidation.
An insulating film 7 like a film is formed. Thereafter, using the control gate CG as a mask, for example, P is placed in the p-type Si substrate 1.
A low concentration of n-type impurities such as ions are implanted. As a result, n-type semiconductor regions 10.11, for example, are formed in a self-aligned manner with respect to the control gate CG and floating gate FC.

Next, as shown in FIG. 3B and FIG. 2, a resist pattern 6 is opened in a portion corresponding to the source region.
is formed by lithography.

After that, using this resist pattern 6 as a mask, P type S
An n-type impurity such as As is ion-implanted into the i-substrate 1 at a high concentration. As a result, an n-type semiconductor region 13, for example, is formed in a portion that will become a source region. Specifically, the dose of this high concentration ion implantation is, for example, ~1
0"/ciil. Although the n-type semiconductor region 10 is almost completely eliminated by this high-concentration n-type impurity ion implantation, even when the memory transistor has an LDD structure, the source region is doped with low impurity. Since there is no need to form a doped region, this is not a problem at all; rather, it is preferable not to have a low impurity doped region on the source region 8 side because the resistance becomes smaller.

Next, after removing the resist pattern 6, for example, by CVD
After forming a film of, for example, Sin on the entire surface by the method, this S
In, the film is etched in a direction perpendicular to the substrate surface by RIE. As a result, sidewall spacers 14 are formed on the side surfaces of the control gate CG and floating gate FC, as shown in FIG. 3C. In this case, sidewall spacers 14 are also formed on the side surfaces of the above-mentioned step portion formed on the surface of the p-type 5ili plate 1.

Next, using the sidewall spacer 14 as a mask, an n-type impurity such as As is ion-implanted into the p-type Si substrate 1 at a high concentration. As a result, as shown in the third diagram, an n'-type source region 8 and drain region 9 are formed in a self-aligned manner with respect to the control gate CG and floating gate FC. Here, a portion of the drain region 7 below the sidewall spacer 14 formed on the side surfaces of the control gate CG and the floating gate FC is doped with a low impurity layer consisting of the previously formed n-type semiconductor region 11. A concentrated portion 9a is formed. The control gate, floating gate FC, source region 8, and drain region 9 form an LDD structure memory transistor.

As described above, according to this embodiment, before forming the sidewall spacers 14 on the side surfaces of the control gate CG and floating gate FG, n-type impurities are doped into the p-type St substrate 1 in the portion that will become the source region 8. Since ions are implanted at a high concentration, the P of the lower part of the sidewall spacer 14 formed on the side surface of the stepped portion formed on the surface of the p-type Si substrate 1 during etching to form the floating gate FC is An n-type semiconductor region 13 can be formed in advance in the St-type substrate 1. Therefore, the impurity concentration is high everywhere in the source region 8, including the above-mentioned step portion, so that the sheet resistance of the source region 8 can be prevented from increasing. Thereby, even when the memory transistor has an LDD structure, deterioration of the characteristics of the memory cell can be prevented.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the second embodiment described above, high concentration n-type impurity ions are implanted into the entire portion that will become the source region 8 using the resist pattern 6. Ion implantation may be performed, for example, only in a stepped portion formed on the surface of p-type Si substrate 1.

Further, the dose of this high concentration n-type impurity ion implantation may be different from that of the second embodiment described above, if the sheet resistance of the source region 8 can be made sufficiently low in the step portion described above. It is also possible.

In addition, in the above two embodiments, the present invention is applied to EFR.
Although the case where it is applied to the production of OM has been described, the present invention is applicable to EEPROM (Electrically
Erasable and programmable
It is also possible to apply this method to the production of 3D (read only memory).

〔Effect of the invention〕

As described above, according to the present invention, after selectively removing the field oxide film in the periphery of the portion that will become the source region of the memory transistor using the control gate as a mask, impurities are added to form the source region and the drain region. Since the ion implantation is carried out, it is possible to further reduce the minimum rule on the source region side, and thereby it is possible to achieve a high integration density of memory cells.

In addition, since the second impurity is ion-implanted at a high concentration into the semiconductor substrate in the portion that will become the source region,
It is possible to prevent an increase in sheet resistance in the source region,
This makes it possible to prevent the characteristics of the memory transistor from deteriorating even when the memory transistor has an LDD structure.

[Brief explanation of drawings]

1A to 1C are EPROs according to an embodiment of the present invention.
FIG. 2 is a plan view of an EFROM manufactured by the EPROM manufacturing method shown in FIG. 1A to FIG. 1C, and FIG. 3A to FIG. 4 is a cross-sectional view illustrating a step-by-step process for manufacturing an EPROM according to another embodiment of the present invention, and FIG. 4 is a plan view showing a conventional EFROM manufactured by a double cell alignment method.
Fig. 5 is a cross-sectional view taken along the line ■-V in Fig. 4, and Fig. 6 is a cross-sectional view of the main parts of a conventional EFROM manufactured by the double cell alignment method when the memory transistor has an LDD structure. be. Explanation of main symbols in the drawings 1: p-type St substrate, 2: field oxide film, 3: gate insulating film, 4: coupling insulating film, 6: resist pattern, 8: source region, 9 drain region, 1
3: n+ type semiconductor region, FG: floating gate, CG: control gate.

Claims (1)

[Claims] 1. A memory transistor has a structure in which a control gate is stacked on a floating gate with an insulating film interposed therebetween, and the floating gate and the control gate are self-aligned in the channel length direction of the memory transistor. In the method for manufacturing a semiconductor non-volatile memory formed in a conventional manner, a field oxide film in a peripheral area of a portion that will become a source region of the memory transistor is selectively removed using the control gate as a mask, and then a source region and a drain region are formed. 1. A method for manufacturing a semiconductor nonvolatile memory, characterized in that ion implantation of impurities is performed to achieve the desired effect. 2. A semiconductor comprising a memory transistor having a structure in which a control gate is stacked on a floating gate via an insulating film, and the floating gate and the control gate are formed in a self-aligned manner in the channel length direction of the memory transistor. A method for manufacturing a non-volatile memory, comprising: using the control gate as a mask, implanting ions of a first impurity into a semiconductor substrate at a low concentration in a portion that will become a source region and a drain region of the memory transistor; A step of ion-implanting a second impurity at a high concentration into the semiconductor substrate at a portion where the semiconductor substrate becomes A method for manufacturing a semiconductor nonvolatile memory, comprising the step of implanting ions of a third impurity at a high concentration into the semiconductor substrate in a region and a portion to become the drain region.