JPH03211837A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03211837A JPH03211837A JP2007357A JP735790A JPH03211837A JP H03211837 A JPH03211837 A JP H03211837A JP 2007357 A JP2007357 A JP 2007357A JP 735790 A JP735790 A JP 735790A JP H03211837 A JPH03211837 A JP H03211837A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- inspection
- passivation
- caused
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、半導体装置における検査用電極の構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of inspection electrodes in semiconductor devices.
[従来の技術]
従来の半導体装置における検査用電極の構造は検査した
い配線の一部に検査用の針を立てるのに十分な面積を持
った電極を設けるといった構造をしていた。[Prior Art] The structure of a test electrode in a conventional semiconductor device is such that an electrode having a sufficient area for setting a test needle is provided on a part of the wiring to be tested.
[発明が解決しようとする課U及び目的]しかしながら
前述の従来技術では、検査用の電極が配線と同じ層にあ
るためアルミのシンター上がりで測定するためにヒルロ
ックが発生し、ショートする可能性がある。またパッシ
ベーションをつける前に測定しなければならないため、
測定中に埃などが付着することにより不良が発生する恐
れがあると同時に、パッシベーションをつけた後に発生
する応力等による不良の解析が不可能である。更に前述
の従来技術では検査用の電極が配線と同じ層にあり、ま
た面積が配線に比べて大きいため配線とシリコン基板の
間の電気的容量が大きく実際の半導体装置の動作速度と
の差が出てしまうといった問題点を有する。[Problem U and purpose to be solved by the invention] However, in the above-mentioned conventional technology, since the test electrode is on the same layer as the wiring, hillocks may occur due to the measurement being carried out on the aluminum sinter, and there is a possibility of short-circuiting. be. Also, since it is necessary to measure before applying passivation,
There is a risk that defects may occur due to adhesion of dust during measurement, and at the same time, it is impossible to analyze defects due to stress, etc. that occur after passivation is applied. Furthermore, in the conventional technology described above, the inspection electrode is on the same layer as the wiring, and the area is larger than the wiring, so the electrical capacitance between the wiring and the silicon substrate is large, resulting in a difference in operating speed of the actual semiconductor device. There is a problem that it comes out.
そこで本発明は測定中に落ちた埃などによる不良やシン
ター後のアルミのヒルロックによるショートを防止する
だけでなくパッシベーションを原因とする応力等による
不良の検査が可能であるとともに実際の半導体装置との
回路の動作速度の差の少ない優れた半導体装置を提供す
ることを目的とする。Therefore, the present invention not only prevents defects caused by dust falling during measurement and short circuits caused by hillocks of aluminum after sintering, but also enables inspection of defects caused by stress caused by passivation, and also makes it possible to detect defects caused by stress caused by passivation. It is an object of the present invention to provide an excellent semiconductor device with little difference in operating speed of circuits.
[課江を解決するための手段]
本発明の半導体装置の配線構造は、層間絶縁膜と、前記
層間絶縁膜の上方に形成された配線と、前記配線の上方
に形成されたパッシベーション膜と、前記パッシベーシ
ョン膜の上方に形成された検査用電極と、前記検査用電
極と前記配線を接続するスルーホールを有することを特
徴とする。[Means for Solving the Problems] The wiring structure of the semiconductor device of the present invention includes an interlayer insulating film, a wiring formed above the interlayer insulation film, a passivation film formed above the wiring, It is characterized by having an inspection electrode formed above the passivation film and a through hole connecting the inspection electrode and the wiring.
[実施例]
本発明の半導体装置の配線構造の一つの実施例の断面図
を第1図(a)に示す。101はシリコン基板、102
は層間絶縁膜、103は配線、104はパッシベーショ
ン膜、105は検査用電極、106は検査用電極と配線
を接続するスルーホール、 107はパッドである。[Example] A cross-sectional view of one example of the wiring structure of a semiconductor device of the present invention is shown in FIG. 1(a). 101 is a silicon substrate, 102
103 is an interlayer insulating film, 103 is a wiring, 104 is a passivation film, 105 is a test electrode, 106 is a through hole for connecting the test electrode and the wiring, and 107 is a pad.
本発明の半導体装置の配線構造の一つの実施例の平面図
を第1図(b)に示す。103は配線、105は検査用
の電極、106は配線と検査用電極を接続するためにパ
ッシベーション膜に開けられたスルーホール、107パ
ツドである。A plan view of one embodiment of the wiring structure of a semiconductor device of the present invention is shown in FIG. 1(b). 103 is a wiring, 105 is an electrode for inspection, 106 is a through hole made in the passivation film to connect the wiring and the electrode for inspection, and 107 is a pad.
本発明の半導体装置の一つの実施例の平面図を第2図に
示す。201はトランジスタ部分、202は配線、20
3は検査用電極である。第2図のように測定したい配線
のすぐ近くにトランジスタがある場合、配線上に検査用
電極を設けると検査用電極に検査用針を当てた際に下に
あるトランジスタに圧力がかかりトランジスタ特性が変
化することがある。したがってこのような場合、第2図
の様にスルーホールによって配線との接続を取ってから
トランジスタの無いところに検査用電極を設ける事によ
りこのような問題点をを解決する。FIG. 2 shows a plan view of one embodiment of the semiconductor device of the present invention. 201 is a transistor part, 202 is a wiring, 20
3 is an electrode for inspection. If a transistor is located very close to the wiring you want to measure, as shown in Figure 2, if a testing electrode is placed on the wiring, when a testing needle is applied to the testing electrode, pressure will be applied to the transistor underneath, which will affect the transistor characteristics. Subject to change. Therefore, in such a case, such a problem can be solved by establishing a connection with the wiring through a through hole and then providing a test electrode in a place where there is no transistor, as shown in FIG.
本発明の半導体装置の一つの実施例の平面図を第3図に
示す。301は配線、302は検査用電極である。第3
図のように何本か平行している配線の内の一つを測定し
たい場合、測定したい配線のすぐ上に検査用電極を設け
ると検査用針を当てた際に下にある配線に応力がかかり
、配線に悪影響を与えることがある。したがってこのよ
うな場合は第3図のようにスルーホールによって配線と
の接続を取ってから下に配線の無いところに検査用電極
を設けることによりこの様な問題点を解決する。A plan view of one embodiment of the semiconductor device of the present invention is shown in FIG. 301 is a wiring, and 302 is an electrode for inspection. Third
When you want to measure one of several parallel wires as shown in the figure, placing a test electrode directly above the wire you want to measure will reduce stress on the wire below when the test needle is applied. This may cause damage to the wiring. Therefore, in such a case, such a problem can be solved by establishing a connection with the wiring through a through hole as shown in FIG. 3, and then providing a testing electrode in a place where there is no wiring underneath.
以下、詳細は工程を追いながら説明していく。Details will be explained below as we follow the process.
まず、ジャンクション等を形成したシリコン基板101
上に層間絶縁膜として酸化珪素膜102を膜厚約400
0人形成し、その上方に配線103をアルミニウムで膜
厚約5000人形成し、その後全面にパッシベーション
膜として窒化珪素膜をCVD法により膜厚約1μm形成
した後、前記配線上にスルーホールを開孔し、そのスル
ーホールの上方に検査用電極を膜厚的1μmのアルミニ
ウムで形成する。First, a silicon substrate 101 with junctions etc. formed thereon.
A silicon oxide film 102 with a thickness of approximately 400 mm is formed thereon as an interlayer insulating film.
After that, a wiring 103 made of aluminum with a thickness of about 5,000 is formed above it, and then a silicon nitride film with a thickness of about 1 μm is formed as a passivation film on the entire surface by CVD method, and a through hole is opened on the wiring. A test electrode is formed above the through hole using aluminum having a thickness of 1 μm.
以上、本発明を実施例を基に説明したが本発明は上記実
施例に限定される物ではなく、その要旨を逸脱しない範
囲で種々変更可能であることは言うまでもない。例えば
配線構造は実施例のアルミ−N配線に限られる物ではな
く二層以上の構成であってもよい。また、ここでは層間
絶縁膜には酸化珪素を、配線にはアルミニウムを、パッ
シベーション膜には窒化珪素を使用しているがその要旨
を逸脱しない範囲で種々変更可能であることは言うまで
もない。Although the present invention has been described above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the spirit thereof. For example, the wiring structure is not limited to the aluminum-N wiring of the embodiment, but may have a structure of two or more layers. In addition, although silicon oxide is used for the interlayer insulating film, aluminum is used for the wiring, and silicon nitride is used for the passivation film, it goes without saying that various changes can be made without departing from the spirit of the invention.
[発明の効果]
以上、述べたように本発明の半導体装置の検査用電極の
構造によれば、パッシベーション膜をつけた後で測定す
るために測定中に落ちた埃などによる不良や、シンター
後のアルミのヒルロックによるショートを防止するだけ
でなく、パッシベーションを原因とする応力等による不
良の検査が可能であるとともに、配線とシリコン基板の
間の容量が従来方法に比べて少なくなるので実際の半導
との回路の動作速度の差が少なくなるという効果を有す
る。[Effects of the Invention] As described above, according to the structure of the inspection electrode for a semiconductor device of the present invention, since the measurement is performed after attaching a passivation film, defects caused by dust etc. that fell during the measurement, and defects after sintering. In addition to preventing short circuits due to aluminum hillocks, it is also possible to inspect defects caused by stress caused by passivation, and because the capacitance between the wiring and the silicon substrate is reduced compared to conventional methods, it is possible to This has the effect of reducing the difference in operating speed of the circuit with the conductor.
第1図(a)は、本発明の半導体装置の一実施例を示す
断面図である。第1図(b)は、本発明の半導体装置の
一実施例を示す平面図である。第2図は、本発明の半導
体装置の一実施例を示す平面図である。第3図は、本発
明の半導体装置の一実施例を示す平面図である。
101・・・シリコン基板
102・・・層間絶縁膜
201・・・トランジスタ
103.202.301・・・配線
104・・・バッジベージコン膜
105.203.302・・・検査用電極106・・・
スルーホール
107・・・パッド
以上FIG. 1(a) is a sectional view showing an embodiment of the semiconductor device of the present invention. FIG. 1(b) is a plan view showing an embodiment of the semiconductor device of the present invention. FIG. 2 is a plan view showing an embodiment of the semiconductor device of the present invention. FIG. 3 is a plan view showing an embodiment of the semiconductor device of the present invention. 101...Silicon substrate 102...Interlayer insulating film 201...Transistor 103.202.301...Wiring 104...Badgecon film 105.203.302...Inspection electrode 106...
Through hole 107...More than pad
Claims (1)
と、前記配線上に形成されたパッシベーション膜と、前
記パッシベーション膜上に形成された検査用電極と、前
記検査用電極と前記配線を接続するスルーホールを有す
ることを特徴とする半導体装置。an interlayer insulating film, a wiring formed above the interlayer insulating film, a passivation film formed on the wiring, an inspection electrode formed on the passivation film, and an inspection electrode and the wiring. A semiconductor device characterized by having a through hole for connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007357A JPH03211837A (en) | 1990-01-17 | 1990-01-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007357A JPH03211837A (en) | 1990-01-17 | 1990-01-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03211837A true JPH03211837A (en) | 1991-09-17 |
Family
ID=11663710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007357A Pending JPH03211837A (en) | 1990-01-17 | 1990-01-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03211837A (en) |
-
1990
- 1990-01-17 JP JP2007357A patent/JPH03211837A/en active Pending
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