JPH03212116A - Digital signal-processing method and apparatus therefor - Google Patents

Abstract

PURPOSE:To improve the operating accuracy of digital data by separating noise from analog input signal through sampling and analog/digital converting an analog signal. CONSTITUTION:When the analog signal of an analog sensor 100 is inputted to a sample holder 101, the signal is sampled and held by the sample holder 101 and held data is outputted to A/D converter 102. The A/D converter 102 outputs data obtained by the conversion of input data into digital data to a digital filter 103. The digital filter 103 applies filter processing to the input data, extracts data with specific frequency components from the input data group and outputs the extracted data to a digital processing data 104. The digital processing part 104 performs a processing operation on the basis of the input data and outputs an operation result.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a digital signal processing method and an apparatus thereof;
In particular, the present invention relates to a digital signal processing method and apparatus suitable for converting analog data into digital data.

[Conventional technology]

As a conventional device of this kind, for example, the Journal of the Institute of Electrical Engineers of Japan 10
As described in Issue 5, No. 12, page 12 et seq., those used in power system digital protection relays are known. This device is composed of an input section, a processing section, a setting section, and a power supply section, and this input section is equipped with a digital filter equipped with an analog filter for high frequency removal, a sample and hold circuit, a multiplexer, an A/D converter, and a buffer. A signal processing device is provided. According to this device, the harmonic component superimposed on the fundamental wave of the analog input signal is removed by the analog filter, and the output signal of the analog filter is
The analog signal is sampled at a frequency of 00 Hz and converted into a digital signal. A configuration is adopted in which the voltage and current magnitude or impedance of the power system is determined from this digital signal and the relay is operated.

[Problem to be solved by the invention]

In the above conventional technology, harmonic components and disturbance noise superimposed on an analog input signal can be removed by an analog filter.

Noise generated after the analog filter, such as disturbance noise and noise associated with quantization errors in the A/D converter, is not taken into account, and there is a problem in that these noises cause errors in the calculated values of digital data. In other words, since the sampling frequency is 600Hz, the frequency range where disturbance noise due to sampling and noise due to quantization error occur overlaps with the passband of the analog filter (frequency range of the analog input signal). It is not possible to separate the noise associated with the quantization error and the quantization error, and these noises cause calculation errors. For this reason, it has not been possible to sufficiently improve the resolution performance of the A/D converter.

An object of the present invention is to provide a digital signal processing method that can improve the calculation accuracy of digital data by separating disturbance noise and noise accompanying quantization errors from analog input signals, and a device applying the method. .

[Means to solve the problem]

In order to achieve the above object, the present invention, as a first method, samples an analog signal and converts it into digital data, subjects this digital data to filter processing using a digital filter, and calculates the filtered digital data. During processing, the stopband of the digital filter is set to a frequency band higher than the passband of the analog signal, and the sampling frequency is set to a frequency where the noise generation area due to disturbance noise and quantization error is above the stopband of the digital filter. The set digital signal processing method is adopted.

As a second method including the first method, a digital signal processing method is adopted in which a frequency 1/N (N: an integer of 2 or more) times the sampling frequency is set as the zero point frequency of the digital filter.

As a third method including the second method, a digital signal processing method is adopted in which the zero point frequency and attenuation characteristic of a digital filter are set according to actual measured values of noise accompanying disturbance noise and quantization error.

The fourth method, which includes the second method, is a digital filter that calculates the area and size of noise caused by disturbance noise and quantization error, and sets the zero point frequency and attenuation characteristics of the digital filter based on the calculated values. This method employs a signal processing method.

The fifth method, which includes the second method, is digital signal processing that spectrally analyzes the area and size of noise caused by disturbance noise and quantization error, and sets the zero point frequency and attenuation characteristics of the digital filter based on the analysis results. This method was adopted.

A sixth method that includes any one of the first to fifth methods.
As a method, a digital signal processing method is adopted in which an analog signal is sampled at a cycle shorter than the calculation cycle of digital arithmetic processing.6 The first device includes a sample hold means for sampling and holding an analog signal; analog-to-digital conversion means for converting data held by the sample and hold means into digital data;
The digital filter means includes a digital filter means that performs filter processing on the digital data output from the digital conversion means, and a digital processing means that performs arithmetic processing based on the digital data output from the digital filter means. The sampling frequency of the sample and hold means is set to a frequency band higher than the passband of the analog signal, and the sampling frequency of the sample and hold means is set to a frequency at which a noise generation area due to disturbance noise and quantization error is equal to or higher than the stopband of the digital filter means. This is a configuration of a digital signal processing device.

As a second device including the first device, the zero point frequency of the digital filter means is 1/N (N
: an integer of 2 or more) times the frequency of the digital signal processing device.

The third device includes a sample-hold means for sampling and holding an analog signal indicating the amount of electricity in the power system, an analog-to-digital conversion means for converting the data held by the sample-and-hold means into digital data, and an analog-to-digital converter for converting the data held by the sample and hold means into digital data. Digital filter means performs filter processing on digital data output from the conversion means, and digital calculation processing means performs fault determination in the power system based on the digital data output from the digital filter means. The sampling frequency of the sample and hold means is set to a frequency band higher than the passband of the analog signal, and the sampling frequency of the sample and hold means is set to a frequency at which a noise generation area due to disturbance noise and quantization error is equal to or higher than the stopband of the digital filter means. This is a configuration of the power system digital signal processing device that has been set up.

As a fourth device including the third device, the zero point frequency of the digital filter means is 1/N (N
: an integer of 2 or more) times the frequency of the power system digital signal processing device.

The fifth device includes a sample-hold means for sampling and holding an analog signal related to a physical quantity to be analyzed, an analog-to-digital conversion means for converting the data held by the sample-and-hold means into digital data, and an analog-to-digital conversion means. The digital filter means includes a digital filter means that performs filter processing on the output digital data, and a digital processing means that performs spectrum analysis based on the digital data output from the digital filter means.

The stopband of the digital filter is set to a frequency band higher than the passband of the analog signal, and the sampling frequency of the sample and hold means is set such that the area where disturbance noise and noise accompanying quantization errors occur is higher than the stopband of the digital filter means. This is a digital signal analysis device configured to have a frequency set to .

As a sixth device including the fifth device, the zero point frequency of the digital filter means is 1/N of the sampling frequency (
N: An integer of 2 or more.

A seventh device includes a sample hold means for sampling and holding an analog signal related to audio, an analog-to-digital conversion means for converting the data held by the sample and hold means into digital data, and a digital converter for outputting the output from the analog-to-digital conversion means. The digital filter means is equipped with a digital filter means that performs filter processing on data, and a digital processing means that performs echo cancellation processing on the digital data output from the digital filter means. The audio signal processing device is configured such that the sampling frequency of the sample and hold means is set to a frequency at which a noise generation area due to disturbance noise and quantization error is equal to or higher than the stopband of the digital filter means. This is what I did.

As an eighth device including the seventh device, the zero point frequency of the digital filter means is 1/N (N
: an integer greater than or equal to 2) times the frequency.

A ninth device includes a sample-hold means for sequentially sampling and holding a plurality of analog signals, and an analog-digital conversion means for converting the data held by the sample-hold means into digital data;
Digital filter means performs filter processing on digital data output from the analog-to-digital conversion means; and digital processing means performs arithmetic processing based on the digital data output from the digital filter means. The sampling frequency of the sample and hold means is set to a frequency band higher than the passband of the analog signal, and the sampling frequency of the sample and hold means is set to a frequency at which a noise generation area due to disturbance noise and quantization error is equal to or higher than the stopband of the digital filter means. This is a configuration of a digital data recording device that has been set up.

As a tenth device including the ninth device, the zero point frequency of the digital filter means is 1/N(
(N: an integer greater than or equal to 2) times the frequency of the digital data recording device.

The eleventh device includes a sample hold means for sampling and holding an analog signal related to audio, an analog-to-digital conversion means for converting the data held by the sample and hold means into digital data, and a digital converter for outputting the output from the analog-to-digital conversion means. digital filter means for filtering the data;
and digital processing means for performing arithmetic processing based on the digital data output from the digital filter means.

The digital filter means is set to a frequency band in which the stopband of the digital signal is higher than the passband of the analog signal, and the sampling frequency of the sample and hold means is set to a frequency band in which the noise generation area due to disturbance noise and quantization error is set to a frequency band that is higher than the passband of the analog signal. This is a digital audio device in which the frequency is set to be above the stopband of the device.

As a twelfth device including the eleventh device, the zero point frequency of the digital filter means is 1/N of the sampling frequency.
(N: an integer of 2 or more) times the frequency of the digital audio device.

[Effect]

Analog signals can be converted to 1/N of the sampling frequency by sampling and analog/digital conversion.
(N is an integer greater than or equal to 2) becomes a discrete signal of frequency. Therefore, if sampling is performed at high speed, it is possible to increase the frequency of total noise such as disturbance noise and noise accompanying quantization error. Therefore, by setting the sampling frequency to a frequency at which the total noise generation region is equal to or higher than the stopband of the digital filter, it becomes possible to generate the total noise in the stopband of the digital filter. If the stopband of the digital filter is set to a frequency band higher than the passband of the analog signal, the total noise can be removed by the digital filter. This makes it possible to increase the S/N ratio of digital data and obtain highly accurate data.

Also, when setting the attenuation characteristics of digital data,
By setting the zero point frequency of the digital filter to a frequency that is 1/N of the sampling frequency, it becomes possible to significantly reduce the total noise.

In addition, since the frequency components of noise components and noise associated with quantization errors are random, by analyzing these frequencies and setting the attenuation characteristics of the digital filter based on the analysis results, the error can be reduced according to the noise generation state. becomes possible.

In addition, when sampling analog signals, if the analog signal is sampled at a cycle shorter than the calculation cycle of digital arithmetic processing, errors can be significantly reduced, and the resolution is higher than that of the analog/digital conversion means. can be obtained.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, a sample holder 101, an A/D converter 102. Digital filter 1o3. The digital processing unit 104 constitutes a digital signal processing device, and an analog signal from the analog sensor 100 is input to the sample holder 101. analog sensor 100
For example, the converter converts various analog data such as current, voltage, speed, pressure, and temperature into voltage.

When the analog signal from the analog sensor 100 is input to the sample holder 101, it is sampled and held by the sample holder 101, and the held data is output to the A/D converter 102. A
/D converter 102 converts input data into digital data and outputs the converted data to digital filter 103. The digital filter 103 performs filter processing on the input data, extracts data of a specific frequency component from the input data group, and outputs the extracted data to the digital processing section 104. The digital processing unit 104 performs various processing operations based on input data and outputs the operation results.

Here, when the output signal of the analog sensor 100 was measured, it was determined that the signal component of the analog signal contained a high-order harmonic component, as shown in (A) of FIG. Ta. Namely.

The analog signal contains noise induced in a power supply or the like as a noise component, so-called disturbance noise. Such disturbance noise is caused by the output of the sample holder 101 and the
This also occurs at the input section of the /D converter 102. When such an analog signal is sampled at a sampling frequency fs=600Hz, the waveform becomes as shown in FIG. 3(B).

When frequency analysis is performed, noise is generated within the passband of the analog signal, as shown in FIG. 3(C). This noise component is l/N of the sampling frequency fS (N is 2
It was confirmed that this phenomenon occurs depending on the frequency (an integer greater than or equal to).

Therefore, in this embodiment, as shown in FIG. 2, the stop band T2 of the digital filter 103 is set to a frequency band higher than the pass band T1 of the analog signal, and the sampling frequency fs of the sample holder 101 is set to a frequency band higher than the pass band T1 of the analog signal. The frequency is set at a frequency where the noise generation region due to the quantization error is equal to or higher than the stopband 12 of the digital filter 103. That is, frequencies f4 to f2
When the passband is defined as the passband, the frequency range f2 to 1/2fs where a lot of noise occurs is set to be the stopband T2. Furthermore, when setting the characteristics of the digital filter 103, it is sufficient to consider the frequency range handled by the sampling theorem to be less than half of the sampling frequency fs. - All you need to do is set the gain characteristics.

In the above configuration, as shown in FIG. 3(D),
When sampling was performed at the sampling frequency fs = 3 kHz, as shown in (E) in FIG. It was measured to occur within T2. That is, it becomes possible to separate the total noise from the analog signal, and it becomes possible to perform highly accurate digital signal processing calculations.

Next, an example developed from FIG. 1 will be described using FIG. 4.

This embodiment differs only in the digital filter 200, and other components are the same as those in the previous embodiment, so the same components are given the same reference numerals and their explanation will be omitted.

Total noise including disturbance noise and noise due to quantization error is generated at a frequency of 1/N (N is an integer) of the sampling frequency fs. Therefore, (A) and (B) in Figure 5
), the zero point frequencies F1 to F6 of the digital filter 200 are adjusted in accordance with the frequency of the noise component 202.
By setting , the noise can be further attenuated.

in this case.

The zero point frequency of the digital filter 200 is a frequency included in the stopband T2 and the sampling frequency f
It is also possible to select all the frequencies for which s is a 17 integer, or to select only the zero point frequencies with high noise levels based on the actual measured value of the noise level.

Furthermore, since the total noise is generated randomly, it is also possible to set the zero point frequency by predicting in advance the frequency at which a large amount of total noise will occur. Furthermore, as will be described later, it is also possible to detect the frequency at which noise occurs and adaptively change the configuration and characteristics of the digital filter 200 so that the detected frequency becomes the zero point frequency of the digital filter 200.

Furthermore, if the A/D converter 102 is configured with a resolution of 12 bits, if the digital filter 200 has the characteristics shown in FIG. can be obtained.

Next, an embodiment of the digital filter 200 will be described based on FIGS. 6 and 7.

6 and 7 show typical block conceptual configurations of the digital filter 200, and FIG. 6 shows an IIR type (I n
finite-extent I pulse Re
5ponse) filter, and Fig. 7 shows an FIR type (F
1nite-extent I pulse Re
5ponse) filter.

In FIG. 6, when the first order is second order, the filter has addition blocks 07 301, 302, 303, 304, filter coefficient blocks 305, 306, 307 degrees 308, 309, and the signal Wn is delayed by one time period T. delay block 310
, a delay block 311 that delays the signal Wn-1 by one time.
The input signal Xn is configured to perform filter processing on the input signal Xn to generate filter output data Yn.

The above filter can be expressed as an arithmetic expression as follows (1).

It is expressed by (2).

Wn=Xn+Wn-1・B1+Wn-2・B2-...(
1) Yn=Wn-AO+Wn-1・A1+Wn-2・A
2...(2) In the above configuration, by adjusting the filter coefficients 305 to 309, various filters shown in the following equations (3) to (7) can be realized.

(Low-pass filter) (Band-pass filter) (Bypass filter) (Notch filter) Here, r=2・cos2πf0・T T: Sampling period fo: Stopping frequency (all-pass filter) Note that Z is a transfer function; Corresponds to S in analog system (s = j w, z = e'').

The filter shown in FIG. 7 includes addition blocks 320, 321,
Filter coefficient blocks 322, 323° 324, delay block 325 that delays input signal X'n by one time, delay block 326 that delays signal X'n-1 by one time.
It is configured to perform filter processing on the input signal X'n and output the negative data Y'n.

The filter in the above configuration is expressed by the following equation (8)
It can be expressed by the formula.

X'n=A'O・X'n+A'l ・X'n-1+A'
2.X'n-2 (8) In order to obtain the desired attenuation characteristics, the above-mentioned filters are connected in cascade.

In this example, when using each of the above-mentioned filters,
As will be described later, the input signal is filtered by digital filter means using a DSP (digital signal processor), and arithmetic processing is repeatedly performed every sampling period T based on predetermined filter coefficients.

Therefore, time-sharing filter processing can be performed in software according to the number of input points.

It becomes possible to respond to increases or decreases in the number of input points, changes in characteristics, and standardization of printed circuit boards. In other words, conventionally, when a signal system for 12 channels is required, 12 channels are required as an analog filter, but by using the filter of this embodiment, the filter can be configured in software according to the number of channels. become.

Also, since filter processing can be performed without using an analog filter, it is similar to an analog filter.

There are no factors such as initial value deviations of elements such as resistors and capacitors, fluctuations in element values due to ambient temperature, and element deterioration due to reduction changes, making it possible to achieve higher performance and eliminate adjustment.

Furthermore, an external inspection circuit is not required, and internal software can handle changes in characteristics, which greatly shortens the manufacturing process and eliminates the need for maintenance.

Next, an embodiment will be described in which the frequency components of the error are horizontally compared and the configuration and characteristics of the digital filter 200 are changed to further reduce the error.

First, an example of changing the characteristics of the digital filter 200 will be described with reference to FIG.

The digital filter 200 shown in FIG. 8 is an IIR type filter, and includes filter coefficient blocks 305, 307,
The configuration can be determined by the 309 coefficients. For example, when the filter is configured as a low-pass filter, the coefficient AO of the filter coefficient block 305 is 1.0.
, coefficient A1 of filter coefficient block 307=2. ○, it is sufficient to set the coefficient A2 of the filter coefficient block 309 to 1.0, and to configure a notch filter in order to provide a zero point, the coefficient AO = 1.0 and the coefficient A2 = 2cos (1
1n T and coefficient A2=1.0. (However, ω
. =2πfn, fn: zero point frequency) The characteristics of the filter, such as the center frequency f and the selectivity Q, are changed by changing the coefficients Bl and B2 of the filter coefficients 306 to satisfy the desired characteristics, as shown in block 400. This can be achieved by

In (A) to (C) of FIG. 9, a low-pass filter 402,
Examples of frequency-gain characteristics of the bandpass filter 403 and the notch filter 403 are shown.

Next, detailed processing contents of the embodiment shown in FIG. 4 will be explained based on FIGS. 10 and 11.

In FIG. 10, frequency analysis of the error is performed in the initial processing shown in block 511, filter coefficients designed to reduce the error are derived, and based on this, block 512
This is an example of performing normal processing. The specific contents will be explained below.

First, in step 500, when storing digital data in the data memory, initial settings such as clearing the data memory are performed, and it is determined whether or not digital data has been input from the A/D converter 102 (step 5o1). ). When the digital data is input (step 5o2), the digital data is n pieces 1, for example, 51
It is determined whether two items have been input (step 503).
).

Step 501 until n pieces of digital data are input.
The processes from 503 to 503 are continued, and when the number of data reaches n, spectrum analysis is performed on these data (step 504).

This spectrum analysis is performed using FFT calculation (fast Fourier transform). Through this spectrum analysis, the frequency of noise occurring in a region other than the passband T1 is detected. Thereafter, filter coefficients are derived so that the detected frequency becomes the zero point frequency of the digital filter 200 (step 505). Specifically, when setting the zero point frequency using a notch filter, the filter coefficients can be determined by the following equations (9) to (13).

AO=1.0...(9)...(lO)...(11) A1=2cosω, T A2=1. 0 However, ωn: 2πf, fn: Zero point frequency ωo: 2π
fo fo: L or new station wave number Q: Selectivity T: The characteristics and configuration of the filter are determined at the stage of initial processing so as to set the frequency where an error occurs to zero using an arithmetic expression that is longer than the sampling period. That is, the number of stages of filters to be connected in cascade is determined. In reality, the frequency of errors that occur does not change significantly, so there is no practical problem even if the characteristics and configuration of the filter are set at the initial stage.

Next, the process moves to block 512, and as online processing, it is determined whether or not there is a data input interruption (step 506), and if there is an interruption, data is input (step 507).

Thereafter, digital filter processing is performed using the digital filter coefficients obtained at the initial time to reduce errors (step 508). A digital operation is performed based on the filtered input data (switch 509), and data according to the operation result is output (step 510).

Figure 11 shows that, whereas the embodiment shown in Figure 10 performs error frequency analysis at the initial stage and sets filter coefficients according to the analysis results, error frequency analysis is performed for each sampling and filter coefficients are set. This is an adaptive change that significantly reduces the frequency component of constant errors.

A specific example will be explained below.

First, initial settings such as clearing the data memory are executed (step 600), and it is determined whether there is a data input interrupt (step 601). If there is a data input interruption, data is input (step 602), and spectrum analysis is performed online based on this input data (step 603). A frequency analysis of the error is performed by this spectrum analysis, and according to the analysis result, the coefficients of the digital filter are determined so as to reduce the frequency components of the detected noise (step 604). Thereafter, filter coefficients are determined and filter processing is applied to the input data (step 605). Next, digital calculations are performed based on the filtered data (step 606), and the calculation results are output (step 607). These series of operations are repeated every cycle T to calculate digital data.

In the case of this embodiment, since the configuration and characteristics of the filter are adaptively changed, it is possible to reduce noise according to the occurrence of randomly generated disturbance noise and noise due to quantization error. Highly accurate digital calculation processing can be achieved.

FIG. 12 shows a block configuration in which the digital signal processing device according to the present invention is applied to a power digital protection relay device.

The device shown in FIG. 12 is configured by dividing the processing function related to the protection relay into nine types of units, and among these units, the digital signal processing device according to the present invention is applied to the analog input crab unit 700. There is. And each of these units is a system control unit 705 . Analog input unit 700 and relay calculation unit 701 that perform A/D conversion and digital filter processing of analog input
, sequence processing unit 702, setting/display processing unit 706, digital input/output crab unit 703. It is composed of an accident detection unit 709, an auxiliary relay unit 704, and a front panel unit 710.

-L units 700, 701, 702, 704, 705, and 706 are each connected via a general-purpose system bus B1.

Further, the sequence processing unit and the digital input/output unit 703 are connected by an input/output I10 bus B2 different from the general-purpose system bus B1.

Furthermore, the relay calculation section 70 in the accident detection unit 709
7 and the sequence processing unit 708 are connected by an input/output I10 bus B3, which is different from the above-described buses B1 and B2.

Note that the system includes a power supply device (not shown), which drives each unit.

Next, the outline of the power digital protection relay device will be explained based on FIGS. 13 to 16.

In step 2001, information from the power system, eg, voltage and current of the power transmission line, is input.

Furthermore, analog quantities are converted into digital quantities.

In step 2002, an electrical quantity for accident detection or control is derived. To derive this amount of electricity, the voltage and current magnitude at the time of a power system fault, and the impedance Z to the fault point are
, resistance R, reactance X, direction of the accident point, frequency at the time of the accident, etc.

In step 2003, the amount of electricity derived in step 2002 is compared with a predetermined set value. As a result of comparative judgment,
If it is determined that it is an accident, the process advances to step 2004.

In step 2004, it is determined whether the accident condition determined in step 2003 continues, and if so, the process proceeds to step 2005. Step 20
In 05, it was determined that there was an accident, so that information is stored.

In step 2006, system sequence processing (sometimes in combination with external conditions and timers) is performed based on the operations of the various relays stored in step 2005, and if an accident is determined, the circuit breaker is shut off. It issues commands. Step 2007 is a device inspection/monitoring process.

The digital control protection device for electric power repeatedly executes the above-described process within n times (n is an integer) the sampling period T of the analog input.

FIG. 14 shows characteristic examples of a known reactance relay (for one element) and a Mori relay (for one element).

In the figure, jx is the inductive reactance component of the impedance.

Further, in step 2002, the above relay elements are
Fifty elements are processed, and the sequence processing in step 2006 performs the desired sequence processing corresponding to the system based on the outputs of these relay elements. Furthermore, Zl and Z2 shown in FIG. 14 are set values, and in the case of a protection relay, these values determine the protection range. This value can be changed online from outside the device by a human in the event of a change in the power system or a corresponding change in the protection range.

FIG. 15 shows an example of the processing flow of the reactance relay shown in FIG. 14, and FIG. 16 shows an example of processing waveforms corresponding to each processing step in FIG. 15. Reference numerals 81 to S7 correspond to each other.

In the case of this reactance relay, first, voltage and current data are input (step SL, 2), various calculations are performed on these data (steps 83 to S7), and the calculation results are compared with a set value (step S8). Here, if the calculation result is larger than the set value, a counter (not shown) for checking the duration of the abnormal state is incremented by +1 (step 9).
).

Next, it is checked whether the count value of this counter has become larger than a predetermined count value (step 510).

Here, if the count value of the counter is larger than the predetermined count value, it is determined that the relay should be operated, and the output of the element relay is set to 1 (step 5ll).

On the other hand, if the count value has not reached the predetermined value, the output of the element relay is set to 0 and is not operated (step 51).
2).

By the way, in step S8, if the calculation result is smaller than the set value, the counter is cleared (step 513), and naturally the output of the element relay is 0 (step 514).

Next, an analog input crab unit of a power digital protection device to which the present invention is applied will be explained.

In Fig. 17, 1101-1 to 1101-N are low-pass filters (mainly to prevent aliasing errors caused by sampling) that input analog signals inl to inN input from the outside and remove harmonics superimposed on the input signals. (hereinafter abbreviated as LPF). 1102-1
~1102-N is a sample hold (hereinafter abbreviated as S/H) circuit, 1103 is a multiplexer (hereinafter abbreviated as MPX), and 1104 is an analog-to-digital converter (hereinafter abbreviated as A/H).
(abbreviated as D) circuit, 1105 is dual port RAM
This is a buffer memory for A/D conversion data using (DPRAM).

1100 is DSP (Digital Signa)
l Processor), 1107 is a program memory (ROM) for storing the DSP infrastructural information,
LB is a local bus, 1109 is a dual port data memory for receiving and passing data to and from the system bus, 111
0 is a system bus interface circuit, and B1 is a system bus.

1106 is a timing generation circuit, and S/H circuit 1
102-1 to 1102-N11 Controls the operations of 102-N1, A/D circuit 1104, and buffer memory 11o5. It also issues an interrupt signal to DSPIloo.

In the embodiments shown above, examples were shown in which individual ICs and LSIs were combined.

By the way, it is possible to integrate individual ICs and LSIs into one LSI.

For example, in FIG. 17, the analog section LPF
, S/H, MPX and one A/D converter (7) L
S I 4. By integrating DSP, ROM, buffer memory and data memory into one LSI,
Significant miniaturization and compactness of the circuit can be achieved.

Alternatively, it is easy to understand that the IC and LSI of each function shown in FIG. 17 may be integrated into one LSI to achieve further miniaturization and compactness.

The digital filter operation explained earlier is shown in 1 in Fig. 17.
This is carried out using the DSP shown in 100. Namely.

As mentioned above, the digital filter operation requires a large number of repetitions of product-sum operations on decimal point data, so SP is suitable because it allows for high-speed product-sum operations.

DSP has fixed-point arithmetic type and floating-point arithmetic type, and both can be applied as a processor that executes the digital filter operation of the present invention, but DSP can ensure a wide dynamic range and needs to be particularly aware of overflow and underflow. It is desirable to use a floating point arithmetic type DSP that does not require this.

Next, this DSP will be described.

FIG. 18 shows a detailed diagram of the configuration of an embodiment of the DSP.

As shown in the figure, the DSP of this embodiment includes an address register 1200 for specifying the address of external memory, a data register 1201 used as a parallel port, a data RAM 1203, an m-bit x m-bit high-speed parallel multiplier 1204, and an instruction ROM 1205. , ALU (Arithmetic
Logic Unit) 1207, a register 1208 such as an accumulator, and a control circuit 12 that controls interrupts of external control signals (a, b, C, etc.), etc.
09, and an internal bus 1210 within the DSP.

The multiplier 1204 multiplies the contents of the input signals A and B during one instruction cycle, and the result C is
It is output to internal bus 1210.

Further, the ALU 1207 adds and subtracts the data from the internal bus 1210 and the data in the register 1208, and writes the result to the register 1208.

As is well known, DSPs can perform high-speed numerical operations on fixed and floating point data by being able to perform multiply-accumulate operations within one instruction cycle and by being able to perform pipeline processing. It is characterized by what it can do. This allows input data related to multiple input points to be filtered in real time. In this respect, a general-purpose microprocessor that does not have a built-in floating-point arithmetic unit has a slow processing speed, so it cannot be applied.

FIG. 19 shows an example of processing timing for the analog human crab knit shown in FIG. 17. As shown in the figure, analog-containing crab knits can be used in the following three ways depending on the system to be applied.
It is now possible to handle cases of seeds.

First, as shown in FIG. 19(B), for example, the digital filter calculation is performed at a 3kHz cycle, and after the digital filter calculation of 5 samples is completed, the calculation results are controlled and
Transfer to protection calculation unit.

This makes it possible to synchronize with the arithmetic unit with a 600 Hz cycle.

In the second case, as shown in figure (C), the digital filter calculation is performed at a 3kHz cycle, and the calculation result is also 3kHz.
The data is transferred to the control/protection calculation unit at a frequency of Hz.

In the third case, as shown in Figure (D), the control/protection calculation is performed at a 3 kHz cycle along with the digital filter calculation. That is, the DS shown in FIG.
P performs both filter calculation and control/protection calculation. This makes it possible to speed up the calculation process in the second and third cases.

Next, an example of the characteristic improvement effect obtained by applying the present invention to a power digital protection relay will be described.

FIG. 20 is applied to backup protection of power transmission lines, etc. This shows the phase characteristics of a reactance relay. Of these, FIG. 20(A) shows the phase characteristics of the conventional method (applied with an analog filter), and FIG. 20(B) shows the phase characteristics of the method to which the present invention is applied. The calculation of the reactance relay in both types uses exactly the same algorithm.

The calculation formula and conditions for the reactance relay are shown below.

ΣCI-Z-V)I ・Z>K ・−・−
(14) Here, ■ = current value, V: voltage value, Z: setting value, K: comparison value, N: integration number setting value 1 Ω Frequency 50Hz Current 5A As is clear from Figure 20, the conventional method is , the incomplete motion region between the non-motion region and the motion region is wide. That is, this indicates that the operating impedance error is large. In this embodiment, the operating impedance error (error between the operating impedance and the settled impedance) on the characteristic angle (90° phase angle) is 3 to 4%.

On the other hand, in the system to which the present invention is applied as shown in FIG. 20(B), the incomplete operation range between the non-operation area and the operation area is narrow. That is, this shows that the operating impedance error is much smaller than that of the conventional system.

In this embodiment, the operating impedance error on the characteristic angle is 1% or less.

FIG. 21 shows an example of the operating impedance characteristics of the reactance relay described above.

In FIG. 21, 1500a and 1500 indicated by dotted lines
Characteristics 1501a and 1501b shown by solid lines represent the operational impedance characteristics of the present invention.

As is clear from this characteristic diagram, it is clear that the operating impedance characteristics according to the present invention have a narrower imperfect operating range than the conventional method, and can achieve extremely high precision (high sensitivity). On the other hand, it is possible to increase the sensitivity by 3 to 5 times.

Figure 22 shows the resistance R up to the accident point based on the differential equation.
and 1 at the input part of the distance relay for calculating the reactance value.
It shows the phase characteristics when the present invention is applied.

Figure 22 (A) is an example of characteristics obtained by the conventional method, and (B)
is an example of the characteristics according to the present invention.

As is clear from the figure, the characteristics to which the present invention is applied are as follows.
It is understood that the width of the incomplete operation region between the operation region and the non-operation region is very narrow, and high precision (high sensitivity) can be achieved.

FIG. 23 shows an example of a processing block configuration for detecting an effective voltage value of a power system to which the present invention is applied. Each block is processed by the DSPIloo shown in FIG. 17 described above. This is applied, for example, to a voltage/reactive power control device for a power system.

In FIG. 23, a block 1701 is a digital filter processing block to which the present invention is applied. This block attenuates harmonics and offsets superimposed on the input signal Vi, as well as disturbance noise and quantization errors.

In particular, the filter coefficients are set so that the frequencies of low-order harmonics that are n times (integer multiples) of the fundamental wave and the above-mentioned disturbance noise and quantization error are at or near the zero point frequency of the digital filter.

Try to obtain a large amount of attenuation.

Next, using the filtered data, the frequency of the signal is determined in block 1702.

By the way, since the frequency of the input data, that is, the frequency of the power system fluctuates (±1 to 3 Hz), it is necessary to correct the gain that fluctuates with the frequency characteristics of the digital filter.

Therefore, in the block 1703, gain correction of the input data is performed using the frequency determined in the block 1702.

Next, the peak value of the gain-corrected and filtered input data is determined in a block 1704.

For example, the peak value can be determined by a method of holding the peak value or by performing calculations as shown in the following equation.

sinωΔt (15) Δ7: Sampling interval ω=2πf f: Detected frequency Next, using the above peak value, the effective value is determined in block 1705, and for further accuracy, By performing averaging processing on blocks 1706, the effective value of input data can be determined with an accuracy of 0.01% or less.

Naturally, in order to achieve this high precision.

It goes without saying that the digital filter to which the present invention is applied, shown in block 1701, is essential.

Next, an embodiment of another power system voltage effective value detection method to which the present invention is applied will be described using FIG. 24.

The outline of the process is to sample the input signal, perform A/D conversion, digital filtering, and obtain the effective voltage value in synchronization with an external synchronization signal corresponding to the frequency of the input signal from the power system. In other words, the sampling frequency is adaptively changed according to external conditions, the filter characteristics are changed, and the effective voltage value is determined with high precision using the same algorithm (for example, squaring and integrating data for one cycle). . This is applied, for example, to a static type non-active power compensator for a power system.

In FIG. 24, in step 1800, it is determined whether there is a data input interrupt. At this time, the interrupt signal is synchronized with the frequency of the input signal from the power grid, as described above.

If there is an interrupt, data is input in step 18o1.

Thereafter, in step 1802, digital filter calculation processing to which the present invention is applied is performed.

That is, the frequencies at which disturbance noise and quantization errors occur are set in the stopband of the digital filter so as not to adversely affect the voltage effective value detection shown in step 18o3.

In step 1803, for example, the following calculation is performed to obtain the effective value of the voltage.

■=ΣV n2...
(16) In this case, since the sampling frequency is changed according to the frequency of the input signal, the above algorithm may be constant regardless of the frequency of the input signal.

In step 1804, the detected effective voltage value is output.

FIG. 25 shows an example of the frequency-gain characteristics of the digital filter shown in step 1802.

For example, the characteristic 18o5 is changed to the characteristic 1806 by the amount of change in the frequency of the input signal from the power system.

Here, the frequency at which disturbance noise and quantization error occur is also
Since it changes in proportion to the sampling frequency, the effect of reducing these errors does not change. Therefore, it goes without saying that the effective voltage value can be detected with very high accuracy.

Next, an embodiment of a digital signal processing system to which the present invention is applied will be described.

First, the system shown in FIG. 26 is a signal analysis system.

In this example, physical quantities (displacement, velocity, pressure, temperature, etc.)
is converted into a potential by the transducer 3001. The output of this transducer 3001 is typically digitized at regular time intervals. That is, the A/D converter 3002 converts it into a digital quantity.

This digital amount is subjected to spectrum analysis using, for example, a spectrum analyzer 3004, and frequency analysis of amplitude, phase, power, energy, etc. is performed. In this case, if the present invention is applied to spectrum analysis, quantization errors caused by A/D conversion can be significantly reduced, and highly accurate spectrum analysis can be performed. Furthermore, if high frequency components of A/D converted data are removed or specific signal frequency components are extracted using the digital filter 3004, highly accurate data can be obtained.

Note that 3005 includes a correlator for determining a correlation function between the captured signal and other signals.

In FIG. 26, the present invention can be applied to the filtering part after A/D conversion, and a highly accurate signal analysis system (eg, spectrum analyzer) can be constructed.

The system shown in FIG. 27 is a configuration example of an audio signal processing device, that is, a CODEC (modulator/demodulator).

The analog sense 4001 captures the audio signal, the A/D converter 40o2 converts the signal to A/D, the digital signal processor 4003 performs processing such as echo cancellation, and the D/A converter 4004 converts the signal to D.
/A conversion and change to analog signal. Then, the analog controller 40o5 executes analog control using the analog signal.

In FIG. 27, the present invention can be applied to A/D conversion and echo cancellation processing by a digital signal processor.

The system shown in FIG. 28 is an example of the configuration of a digital data recorder.

In FIG. 28, a plurality of analog input signals are taken in by an analog sensor 5001, and these signals are switched by an analog multiplexer 5002.

The A/D converter 5003 sequentially performs A/D conversion, the digital signal processor 50Q4 performs digital signal processing, and this data is stored in the recorder 500S. In FIG. 28, the present invention can be applied to the A/D conversion and digital signal processor parts, allowing faithful storage of input signals.

The system shown in FIG. 29 is an example of a digital audio device. In this system, a sound source 6001 is processed by an analog processing unit 6002, this signal is A/D converted by an A/D converter 6003, and this data is processed by a processing unit 6004.
The data is digitally processed and recorded by a recorder 6005. When reproducing sound, a digitally recorded signal 7001 is processed by a processing unit 7002, and this data is D/A converted by a D/A converter 7003.

The analog signal is processed by the processing unit 7004, and the speaker 70
The sound is output from o5.

In FIG. 29, the present invention can be applied to the A/D conversion and digital processing parts of the recording system, which enables faithful recording of the sound source and improves the signal-to-noise ratio (
S/N ratio) can be significantly improved.

〔Effect of the invention〕

According to the present invention, the frequency domain of noise due to disturbance noise and quantization error can be set as the stopband of a digital filter, so that the following effects can be obtained.

(1) Resolution higher than that of the applied A/D converter can be achieved.

(2) It is possible to extract a highly accurate and stable input signal that is not affected by disturbance noise or noise caused by quantization errors.

(3) By applying it to a power system protection device, the imperfect operating range can be made very narrow, and highly accurate protection calculations can be performed.

(4) By applying it to voltage effective value detection in power systems, it is possible to obtain the voltage effective value with a detection accuracy of 0.01% or less, which greatly improves voltage/reactive power control devices and static non-active power compensators. Accuracy can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a characteristic diagram of the digital filter shown in FIG. 1, FIG. 3 is a diagram for explaining the conventional example and the sampling method of the present invention, and FIG. 4 is a block diagram showing another embodiment of the present invention.
Figure 5 is a characteristic diagram of the digital filter shown in Figure 4;
The figure is a block diagram of an IIR type filter, Figure 7 is a block diagram of an FIR type filter, Figure 8 is a diagram showing an application example of the IIR type filter, and Figure 9 is a frequency diagram when using the filter shown in Figure 8. The characteristic diagram, FIGS. 10 and 11 are flowcharts for explaining the operation when the present invention is applied to an adaptive filter, respectively, and FIG. 12 is a block diagram of a power system control/protection device to which the present invention is applied. , FIG. 13 is a flow chart for explaining the operation of FIG. 12, and FIG.
The figure is a phase characteristic diagram of the power system control and protection device, Figure 15 is a flowchart to explain the action of the reactance relay, Figure 16 is an operation waveform diagram corresponding to the processing flow in Figure 15, and Figure 17 is the main Block configuration diagram of analog input crab unit of power system control/protection device to which the invention is applied, Part 1
Figure 8 is a block configuration diagram of the DSP, Figure 19 is a diagram for explaining the operation timing of the analog input crab unit, and Figure 2.
FIG. 0 is a phase characteristic diagram of a power system control/protection device to which the present invention is applied. Fig. 21 is an operating impedance characteristic diagram of a reactance relay to which the present invention is applied, Fig. 22 is a phase characteristic diagram of a distance relay to which the present invention is applied, and Fig. 23 is a diagram of voltage effective value detection in a power system to which the present invention is applied. Processing block diagram, 24th
The figure is a flowchart for explaining the operation of FIG.
Part 25 @ is a frequency characteristic diagram of the device shown in Fig. 23, and Fig. 26
The figure is a block diagram of a signal analysis device to which the present invention is applied.
FIG. 27 is a block configuration diagram of an audio signal processing device to which the present invention is applied, FIG. 28 is a block configuration diagram of a digital data recorder to which the present invention is applied, and FIG. 29 is a block configuration diagram of a digital audio device to which the present invention is applied. It is a diagram. 100... Analog sensor, 101 Sample holder, 102 A/D converter, 103°20
0...Digital filter, 104...Digital processing section.

Claims (1)

[Claims] 1. When sampling an analog signal and converting it into digital data, applying filter processing to this digital data using a digital filter, and performing arithmetic processing on the filtered digital data, the stop band of the digital filter is A digital signal processing method in which a frequency band is set higher than the passband of an analog signal, and a sampling frequency is set to a frequency where the noise generation area due to disturbance noise and quantization error is above the stopband of a digital filter. 2. 1/N of sampling frequency (N: integer greater than or equal to 2)
2. The digital signal processing method according to claim 1, wherein the double frequency is set as the zero point frequency of the digital filter. 3. The digital signal processing method according to claim 2, wherein the zero point frequency and attenuation characteristic of the digital filter are set in accordance with actual measured values of disturbance noise and noise accompanying quantization error. 4. The digital signal processing method according to claim 2, wherein the generation area and magnitude of noise accompanying disturbance noise and quantization error are determined by calculation, and the zero point frequency and attenuation characteristic of the digital filter are set based on the calculated values. 5. The digital signal processing method according to claim 2, wherein the generation area and magnitude of noise caused by disturbance noise and quantization error are spectral analyzed, and the zero point frequency and attenuation characteristic of the digital filter are set based on the analysis results. 6. The digital signal processing method according to claim 1, 2, 3, 4 or 5, wherein the analog signal is sampled at a shorter period than the calculation period of the digital calculation process. 7. Sample and hold means for sampling and holding analog signals; analog-to-digital conversion means for converting the data held by the sample and hold means into digital data; and filter processing on the digital data output from the analog-to-digital conversion means. The digital filter means includes a digital filter means and a digital processing means for performing arithmetic processing based on the digital data output from the digital filter means, and the digital filter means has a stop band of the digital filter set to a frequency band higher than a pass band of the analog signal. . A digital signal processing device, wherein the sampling frequency of the sample and hold means is set to a frequency at which a noise generation area due to disturbance noise and quantization error is equal to or higher than a rejection band of the digital filter means. 8. The digital signal processing device according to claim 7, wherein the zero point frequency of the digital filter means is set to a frequency 1/N (N: an integer of 2 or more) times the sampling frequency. 9. Sample and hold means for sampling and holding an analog signal indicating the amount of electricity in the power system; analog-to-digital conversion means for converting the data held by the sample and hold means into digital data; comprising digital filter means for filtering digital data; and digital arithmetic processing means for determining faults in the power system based on the digital data output from the digital filter means;
The digital filter means is set to a frequency band in which the stopband of the digital filter is higher than the passband of the analog signal, and the sampling frequency of the sample and hold means is such that the noise generation area due to disturbance noise and quantization error is set to a frequency band that is higher than the passband of the analog signal. A power system digital signal processing device that is set to a frequency that is above the stopband of the means. 10. The power system digital signal processing device according to claim 9, wherein the zero point frequency of the digital filter means is set to a frequency 1/N (N: an integer of 2 or more) times the sampling frequency. 11. Sample and hold means for sampling and holding an analog signal related to the physical quantity to be analyzed; analog-to-digital conversion means for converting the data held by the sample and hold means into digital data; and digital data output from the analog-to-digital conversion means. comprising digital filter means for performing filter processing on the filter, and digital processing means for performing spectrum analysis based on the digital data output from the digital filter means,
The digital filter means is set to a frequency band in which the stopband of the digital filter is higher than the passband of the analog signal, and the sampling frequency of the sample and hold means is such that the noise generation area due to disturbance noise and quantization error is set to a frequency band that is higher than the passband of the analog signal. A digital signal analyzer whose frequency is set to be above the stopband of the means. 12. The digital signal analysis device according to claim 11, wherein the zero point frequency of the digital filter means is set to a frequency 1/N (N: an integer of 2 or more) times the sampling frequency. 13. Sample and hold means for sampling and holding analog signals related to audio; analog-to-digital conversion means for converting data held by the sample and hold means into digital data;
The digital filter means includes digital filter means for performing filter processing on the digital data output from the digital conversion means, and digital processing means for performing echo cancellation processing on the digital data output from the digital filter means. The sampling frequency of the sample and hold means is set to a frequency band higher than the passband of the digital filter means, and the sampling frequency of the sample and hold means is set to a frequency at which a noise generation area due to disturbance noise and quantization error is equal to or higher than the stopband of the digital filter means. Audio signal processing device. 14. The audio signal processing apparatus according to claim 13, wherein the zero point frequency of the digital filter means is set to a frequency 1/N (N: an integer of 2 or more) times the sampling frequency. 15. A sample-hold means for sequentially sampling and holding a plurality of analog signals, an analog-to-digital conversion means for converting the data held by the sample-and-hold means into digital data, and a filter for the digital data output from the analog-to-digital conversion means. The digital filter means is equipped with a digital filter means for performing processing, and a digital processing means for performing arithmetic processing based on the digital data output from the digital filter means. , and the sampling frequency of the sample and hold means is set to a frequency at which a noise generation area due to disturbance noise and quantization error is equal to or higher than a rejection band of the digital filter means. 16. The digital data recording device according to claim 15, wherein the zero point frequency of the digital filter means is set to a frequency 1/N (N: an integer of 2 or more) times the sampling frequency. 17. Sample and hold means for sampling and holding analog signals related to audio; analog-to-digital conversion means for converting data held by the sample and hold means into digital data;
The digital filter means includes a digital filter means that performs filter processing on the digital data output from the digital conversion means, and a digital processing means that performs arithmetic processing based on the digital data output from the digital filter means. The sampling frequency of the sample and hold means is set to a frequency band higher than the passband of the analog signal, and the sampling frequency of the sample and hold means is set to a frequency at which a noise generation area due to disturbance noise and quantization error is equal to or higher than the stopband of the digital filter means. digital audio equipment. 18. The digital audio device according to claim 17, wherein the zero point frequency of the digital filter means is set to a frequency 1/N (N: an integer of 2 or more) times the sampling frequency.