JPH03212733A - Memory command processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a memory command processing device, and particularly to a memory command processing device suitable for use in memory command processing during execution of a microprogram.

(Prior Art) Conventionally, when a microprogram (firmware) performs memory read/write processing, the intended data write/write is executed at the next timing when a memory command is specified.

FIG. 3 shows an example of a conventional microaddress processing flow for memory access by a microprogram. In this figure, the case of reading memory is particularly illustrated.

Now, when a memory read command is issued after processing, the memory is accessed at this timing without performing address calculation or setting of address-related registers. Then, in process C at the next timing, the memory data accessed in the previous step is sent and latched into an external buffer. In other words, memory data can be read at the next timing specified by the memory read command. The same thing holds true for the relationship between process e and process f. Therefore,
When a memory read command is issued after processing e, memory data is actually obtained at the next timing of processing f.

(Problem to be Solved by the Invention) In conventional processing methods, memory commands or frequently used software instructions require processing steps such as specifying a memory address and reading data, resulting in a large number of processing steps. This not only takes time, but also causes deterioration in the processing performance of the CPU.

The present invention has been made in view of the above, and its purpose is to:
An object of the present invention is to provide a memory command processing device that can shorten the processing time of memory commands when executing a microprogram by processing memory commands in advance.

[Structure of the invention]

(Means for Solving the Problems) A memory command processing device of the present invention includes: a first memory that stores a portion of a microprogram other than memory commands; a second memory that stores a memory command of the microprogram; a sequencer that provides a microaddress n currently being executed to a first memory and a microaddress n+1 to be executed next to the second memory; and a sequencer that holds and decodes an output instruction code of the first memory. a first latch/decoder that supplies the control operation unit; and a second latch/decoder that holds and decodes the output instruction code of the second memory.
a latch/decoder, an address calculation/latch that calculates and latches a memory address from the output of the second latch/decoder, and an address calculation/latch that calculates and latches a memory address based on the output of the second latch/decoder and the output of the address calculation/latch. , and memory control means for pre-processing memory commands.

(Function) The sequencer gives the microaddress n currently being executed to the first memory, and gives the microaddress n+1 to be executed next to the second memory. The portion of the first memory excluding the memory command of the microprogram is given to the first latch/decoder means, and this output instruction code is held, decoded, and given to the control calculation unit to execute the current process. In parallel with this, a microprogram memory command is provided from the second memory to the second latch/decoder. As a result, this output instruction code is held and decoded, and the decoding result is used for address operation/
It is given to the latch, and the memory address is calculated and latched. Furthermore, the memory commands are processed in advance by providing the outputs of the second latch/decoder and address calculation/latch to the memory control means.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a memory command processing device according to an embodiment of the present invention. In FIG. 1, memory 1 is composed of ROM or RAM, and stores firmware (microinstructions). Latch 2 is connected to memory 1 and latches the currently executing microinstruction. The instruction decoder 3 decodes the microinstruction latched by the latch 2, transmits the instruction to the arithmetic control unit 11, and causes it to perform necessary processing.

The memory 4 is composed of ROM or RAM, and stores firmware containing only memory commands.

The latch 5 is connected to the memory 4 and latches the microinstruction of the memory command to be executed next.

The instruction decoder 6 decodes the microinstruction latched by the latch 5 and sends an instruction based on the microinstruction of the memory command to be executed next to the address calculation unit 7 and the memory control unit 10.

The address calculation unit 7 executes memory address calculation according to instructions from the instruction decoder 6. The latch 8 temporarily latches the address obtained by the address calculation section 7. The sequencer 9 outputs the microaddress currently being executed and the microaddress to be executed next (the microaddress currently being executed+1) to the memories 1 and 4 for control.

Next, the operation of the above configuration will be explained according to an example of the processing flow shown in FIG.

Sequencer 9 stores the micro address of process A in memory 1.
Suppose we want to output to . Thereby, the memory 1 outputs the instruction code to the latch 2 according to the given microaddress, and causes the latch 2 to hold the instruction code. The instruction decoder 3 decodes the instruction code latched by the latch 2, transmits the instruction to the arithmetic control section 11, and causes it to execute control. In parallel with the above operations, the sequencer 9 writes a message in the memory 4 that is 1 higher than the currently executing micro address n (the micro address given to the memory 1).
Outputs the microaddress n+1 which is the one preceding. This microaddress n+1 corresponds to process B. Memory 4 stores the given micro address n+1
Latch the instruction code (memory related instructions only) according to 5
Output and hold. The instruction decoder 6 decodes the memory-related instruction code latched by the latch 5, and transmits the instruction to the address calculation section 7 and the memory control section 10 for control. The address calculation unit 7 calculates a memory address in accordance with the supplied memory-related command, causes the latch 8 to hold the result, and transfers the result to the memory control unit 10.

In this way, the execution process of process A corresponding to the instruction to be executed currently is executed in the system from the memory 1, latch 2, and instruction decoder 3 to the arithmetic control unit 11.

On the other hand, regarding memory-related instructions in process B that correspond to the next instruction to be executed, memory 4, latch 5
, the instruction decoder 6, the address calculation unit 7, the latch 8, and the memory control unit 10 perform advance processing. As a result, when the process progresses and enters process B, memory-related processes have already been completed in the preceding process, so memory data can be obtained immediately.

The preceding processing as described above is also executed between successive processing, for example, processing C and processing. As a result, advance processing is always performed regarding memory-related processing. As a result, even if there are many memory commands, it is possible to process them in a timely manner.

〔Effect of the invention〕

As described above, according to the present invention, since memory commands are processed in advance, the actual memory command processing time can be significantly reduced, and this allows memory commands to be used frequently. This makes it possible to process even simple software instructions at high speed, making it possible to significantly improve the processing performance of the CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory command processing device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a processing flow using a microaddress to explain the operation of the configuration of FIG. 1, and FIG. The figure is an explanatory diagram showing an example of a conventional processing flow using microaddresses. 1.4...Memory, 2,5.8...Latch, 3.6
...Instruction decoder, 7...Address calculation section, 9...
- Sequencer, 10... memory control section, 11... arithmetic control section.

Claims (1)

[Scope of Claims] A first memory that stores a portion of a microprogram other than memory commands; a second memory that stores memory commands of the microprogram; and a microaddress n currently being executed in the first memory. and a sequencer that gives a micro address n+1 to be executed next to the second memory; a first latch/decoder that holds and decodes an output instruction code of the first memory and provides it to a control calculation section; , a second latch/decoder that holds and decodes an output instruction code of the second memory; an address calculation/latch that calculates and latches a memory address from the output of the second latch/decoder; The output of the latch/decoder and the address operation/
A memory command processing device comprising: memory control means for pre-processing a memory command based on an output of a latch.