JPH03212735A - Instruction processing system for microprocessor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction processing method of a microprocessor, and particularly to improving its processing performance.

[Prior art] Figure 4 shows, for example, the Institute of Electronics, Information and Communication Engineers technical report ICU38.
106 is a block diagram showing a pipeline processing mechanism of a conventional microprocessor described in US Pat. In the figure, 7 is the conventional instruction fetch stage (hereinafter abbreviated as IF stage), 2 is the instruction decode stage (hereinafter abbreviated as D stage), and 8 is the effective address of the operand specified in the decoded instruction code. 4 is the conventional operand address calculation stage (hereinafter abbreviated as A stage) that performs calculations, 4 is an operand fetch stage (hereinafter abbreviated as F stage) that fetches operands from memory, and 5 is an operation specified in the instruction code for the operand. This is an instruction execution stage (hereinafter abbreviated as E stage) for executing.

Next, the operation will be explained.

IF stage 7 fetches instructions from memory and outputs them to D stage 2. The D stage 2 decodes the instruction code input from the IF stage 7 and outputs the decoding result to the A stage 8. The A stage 8 calculates the effective address of the operand specified in the instruction code, performs address indirection if necessary, and outputs the calculated operand address to the F stage 4. F stage 4 uses the operand address input from A stage 8 to fetch an operand from memory. The fetched operand is output to E stage 5. The E stage 5 executes the operation specified in the instruction code on the operand input from the F stage 4. Furthermore, if necessary, the calculation results are stored in an external memory not clearly shown in the figure.

Next, the manner in which instructions are processed on the pipeline will be explained using FIG. At the IF stage 7, an instruction fetch address is output and an instruction fetch is performed in a minimum of two clocks. Immediately after the instruction is fetched, it is decoded and the operation specified by the instruction is performed through subsequent pipeline processing. D
In stage 2, instruction decoding is completed in two clocks for each minimum instruction unit, and instruction information is sent to A stage 8. The A stage 8 also sends instruction information to the F stage 4 in a process of at least two clocks, and the F stage 4 also sends instructions to the E stage 5 in a process of a minimum of two clocks.

Finally, in the E stage 5, the operation is executed by taking a minimum of two clocks, or even more time in the case of a complicated instruction. In this way, execution of one instruction requires at least 10 clocks.

Normally, the IF stage 7 has an instruction cache, and when an instruction is fetched to an address registered in the cache, the instruction fetch is completed in one clock instead of two clocks accessing the external memory. Due to the effect of the instruction cache, instruction fetching can be completed in one clock, so the apparent processing power is improved.

[Problems to be Solved by the Invention] Conventional microprocessors are configured and operate as described above, and therefore require at least one clock for instruction fetch and two clocks for instruction decoding in order to process instructions registered in the instruction cache. Requires a clock. However, there is a demand for even higher speeds.

This invention was made to solve the above-mentioned problems, and its purpose is to improve the processing ability of a microprocessor.

[Means for Solving the Problems] The instruction processing method of the microprocessor according to the present invention is as follows:
A storage means is provided for storing a decoding result of an instruction and a fetch destination address of the instruction in association with each other, and when an instruction is fetched, the fetch destination address is used to refer to the storage means, and when the addresses match, the memory is stored in the storage means. The subsequent processing is executed using the decoded results obtained.

[Operation: In this invention, if the instruction fetch destination address is registered in the storage means that caches the decoding results, the instruction fetching and decoding processing, which would otherwise require three clocks, can be completed in one clock. This allows for faster processing.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a pipeline processing mechanism of a microprocessor in an embodiment of the present invention. In the figure, 1 is an IF stage that fetches an instruction and simultaneously accesses (references) a decode cache memory (described later), 2 is a D stage that decodes an instruction, and 3
4 is the A stage that calculates the effective address of the operand specified in the decoded instruction code, usually using the output of D stage 2, and when the decode cache hits, the output of the decode cache memory. F stage 5 fetches an operand from memory, and E stage 5 executes an operation specified in the instruction code on the operand.

Furthermore, 6 is a decode cache memory (storage means) that stores the decoding result of an instruction and the start address (fetch destination address) where the instruction is stored in association with each other.

Next, the operation will be explained.

IF stage 1 fetches instructions from memory and outputs them to D stage 2. The D stage 2 decodes the instruction code input manually from the F stage 1 and outputs the decoding result to the A stage 3. At the same time, the start address where the decoded instruction is stored and the decode result are registered in the decode cache memory 6. The A stage 3 calculates the effective address of the operand specified in the instruction code, performs address indirection if necessary, and outputs the calculated operand address to the F stage 4. F stage 4 uses the operand address input from A stage 3 to fetch an operand from memory. The fetched operand is output to E stage 5. The E stage 5 executes the operation specified in the instruction code on the operand input from the F stage 4. Furthermore, if necessary, the calculation result is stored in memory. The decode result and the start address value of the instruction are registered in the decode cache memory 6.

Next, the manner in which instructions are processed by pipeline processing will be explained using FIGS. 2 and 3. In IF stage 1, an instruction fetch destination address is output, and the instruction fetch is normally performed in a minimum of two clocks.

At this time, the decode cache memory 6 is also referenced at the same time, and if the instruction registered in the decode cache memory 6 is to be fetched, instead of fetching the instruction and decoding the immediately following instruction, the instruction is fetched in one clock as shown in FIG. The decode result is sent from the decode cache memory 6 to the A stage 3, and the operation specified by the instruction is performed through pipeline processing. If the contents registered in the decode cache memory 6 and the address at which the instruction was fetched are different, as shown in FIG. Instruction decoding is completed and instruction information is sent to A stage 3. The A stage 3 also sends instruction information to the F stage 4 in a minimum of two clocks, and the F stage 4 also sends instructions to the E stage 5 in a minimum of two clocks. Finally, in the E stage 5, the operation is executed by taking a minimum of two clocks, or even more time in the case of a complicated instruction. If the decode cache misses, it will take at least 10 clocks to execute one instruction as shown in Figure 3, but if the decode cache hits, the execution of one instruction will take a minimum of 10 clocks as shown in Figure 2. The minimum number of locks required is 7 clocks.

This results in instruction fetch and decoding being processed in one clock by referring to the decode cache, and A stage 3. F stage 4. This is because two clocks are required for each E stage 5 process.

Due to its nature, the decode cache memory 6 cannot be expected to have a very large capacity. In such a case, in order to maximize the effectiveness of the limited decode cache memory 6,
Only the instruction fetch immediately after execution of a jump or branch instruction is registered so that it becomes effective when an operation that disturbs the regular movement of the pipeline, such as a jump or branch instruction, occurs. Since an instruction fetch immediately after execution of a jump or branch instruction always fetches the start address of the instruction, it matches well with the nature of the decode cache in which the start address of the instruction is registered.

In the above embodiment, the present invention is applied to a microprocessor having a pipeline processing mechanism, but the effects can be expected even when applied to a microprocessor without a pipeline processing mechanism.

[Effects of the Invention] As described above, according to the present invention, by caching the instruction decoding results, it is possible to realize faster processing of the microprocessor.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the internal pipeline of a microprocessor according to an embodiment of the present invention, FIG. 2 is a conceptual diagram of instruction processing when the decode cache is hit in the microprocessor according to the present invention, and FIG. FIG. 4 is a block diagram showing the internal pipeline of a conventional microprocessor; FIG. 5 is a conceptual diagram of instruction processing in a conventional microprocessor. be. 1 is the instruction fetch (TF) stage, 2 is the instruction decode (D) stage, and 3 is the operand address calculation (A).
Stage 4 is operand fetch (F) stage 5
6 is an instruction execution (E) stage, and 6 is a decode cache memory (storage means). In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] In a microprocessor that decodes an instruction fetched from a memory and executes processing specified by the instruction based on the decoding result, the decoding result of the instruction and the fetch destination address of the instruction are stored in association with each other. A storage means is provided, and when an instruction is fetched, the fetch destination address is used to refer to the storage means, and when the addresses match, the decoding result stored in the storage means is used to execute subsequent processing. Microprocessor instruction processing method.