JPH03212744A - Information processing equipment operation measurement device - Google Patents

Abstract

PURPOSE:To individually measure periods from start addresses up to end addresses within a previously determined appearance frequency range by controlling time measurement in accordance with the contents of a counter for counting up the number of times of detecting the coincidence of start addresses. CONSTITUTION:In the case of measuring the time from the start address appearing in the n-th times up to the end address corresponding to the start address during the execution of a series of programs, a coincidence circuit 7 is set up so as to output a logic '1' signal during the period that the contents of a counter 6 are 'n'. At the time of initialization, an FF 3, the counter 6 and a timer counter 50 are respectively reset. In each detection of a coincidence detecting signal from a start address coincidence detecting part 1, the FF 3 is turned from OFF to ON and the number of times of turning from OFF to ON is counted up dy the counter 6. During the period from 'n' to 'n+1' in the contents of the counter 6, the circuit 7 outputs the logic '1' signal, and when the output of the FF 3 is logic '1', pulses from clock generator 51 are inputted to the counter 50 and counter up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing equipment operation measuring device that measures the operation of information processing equipment.

[Prior Art] As a prior art to this invention, for example, Japanese Patent Laid-Open No. 61-18
There are those described in JP-A-050 and JP-A-62-236047.

FIG. 7 corresponds to FIG. 1 of Japanese Unexamined Patent Publication No. 6118050, and in the figure, (10) and (20> are respectively a match detection section, (11) is a start address setting section, and (21) is an end address setting section. , (3) is a flip-flop, (4) is an AND gate, (50) is a timer counter, and (51) is a clock generator.

Start address setting section (11) and end address setting section (2)
In 1), the start address and end address of the control operation whose required time is to be measured are respectively set. The flip-flop (3) is reset at the time of initialization.

Execution address signals for reading command statements for executing a series of control operations are input in parallel to the coincidence detection units (10) and (20). When the execution address matches the start address, a match detection signal is output from the match detector (10) and the flip-flop (3) is set.

Thereafter, when the execution address matches the end address, a match detection signal is output from the match detection section (20) and the flip-flop (3) is reset.

While the flip-flop (3) is in the set state, the gate (4) is in the on state, allowing clock pulses from the clock generator (51) to pass through, and the passed clock pulses are counted by the timer counter (50). . Since the timer counter (50) is reset at the time of initialization, the contents of the timer counter (50) after changing the execution address within a predetermined range indicate the elapsed time from the start address to the end address.

FIG. 8 is an operation time chart showing the operation of the circuit shown in FIG.
The outputs of the coincidence detectors (10) and (20) are shown, and the time during which the gate (4) is in the on state is shown as "time measurement". However, the flip-flop (3) is shown as being triggered at the rising point of the input pulse.

As the output clock of the clock generator (51) in FIG. 7, the clock of the target device in FIG. 8 may be used, or a separate clock generator (51) may be provided.

[Problems to be Solved by the Invention] Since the conventional information processing equipment operation measurement device as described above is configured as described above, the information processing equipment operates between the start address and the end address that the information processing equipment first passes during operation. It is only possible to measure the time of . However, in general, in information processing equipment, the same start address and corresponding end address appear multiple times in a series of programs, and the time from the start address to the end address differs depending on the point of appearance. is common, so it becomes insufficient to simply measure the time between the first passed starting address and ending address.

An invention made to solve this problem is disclosed in Japanese Patent Application No. 62-264342 entitled "Computer Load Measuring Device". In this invention, the time measured multiple times is accumulated, but although it is possible to determine the total time or average time with such a method,
There is a problem in that it is not possible to measure the time required at any given point of departure or to measure the degree of variation in the required time depending on the point of departure.

The present invention has been made to solve this problem, and provides an information processing equipment operation measurement device that can separately measure the time from a start address to a corresponding end address within a predetermined number of occurrences range. The purpose is to

[Means for Solving the Problems] An information processing equipment operation measuring device according to the present invention is provided with a counter that counts the number of times a match of start addresses is detected, and controls time measurement according to the contents of this counter. It is something.

[Operation] In the present invention, by controlling time measurement according to the contents of a counter that counts the number of times a match of start addresses is detected, it is possible to obtain data for an arbitrary range of times.

[Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the first invention according to this application. In FIG. 1, the same reference numerals as in FIG. 7 indicate the same or corresponding parts, and (1) is a start address matching detection unit ,
(2) is an end address match detection unit, and a start address match detection unit (1) detects 10) and (11) in FIG.
The end address match detection unit (2) is configured by (20) and (20) in FIG.
21) are collectively expressed. (6)
indicates a counter, and (7) indicates a - number circuit.

Note that the gate (4), clock generation circuit (51), and timer counter (50) will be collectively referred to as a timer (5).

When you want to measure the time from the start address that appears the nth time during the execution of a series of programs to the corresponding end address, the -number circuit (7) is a counter (6).
It is set to output a logic "1" signal while the content of is n.

The flip-flop (3), counter (6), and timer counter (50) are each reset at the time of initialization.

Each time a coincidence detection signal is detected from the start address coincidence detection section (1), the flip-flop (3) is turned from off to on, and the number of times the flip-flop (3) is turned from off to on is counted by a counter (6). From the time when the content of the counter (6) reaches n until the next time it reaches n+1, 1 (7) is calculated by the logic "-" several times.
During the period in which the output of the flip-flop (3) is logic "1", the pulses from the clock generation circuit (51) are input to the timer counter (50) and counted.

FIG. 2 is an operation time chart showing the operation of the circuit of FIG. 1, and the clock, execution address, and start address matching of the target device correspond to the parts with the same names in FIG. 8. And the starting address - the number of times counter is the counter (
6), the pulse at the end of measurement is output from the end address match detection unit (2), and is output corresponding to each pulse indicated as start address match, but the second
In the figure, only the nth time is shown.

FIG. 3 is a block diagram showing an embodiment of the second invention according to this application, in which the same reference numerals as in FIG. This is to measure each time separately.

In FIG. 3, (71) and (72) are negative number circuits, and (73) and (74) are registers, respectively, in which an upper limit value m+1 and a lower limit value are set. (75) is a flip-flop, and (52) is a delay circuit.

The flip-flop (75) is reset at the time of initialization, set when the content of the counter (6) reaches k, and reset when the content of the counter (6) reaches m+1.

That is, while the content of the counter (6) is ~m, the flip-flop (75) outputs a signal of logic rl to turn on the gate (4) and operate the timer (5).

Furthermore, in order to prevent the timer counter (50) from accumulating, after the measurement for that time is completed by the match detection signal from the end address match detector (2), the timer counter is sent via the delay circuit (52). (5o) is reset to prepare for the next measurement.

In the circuit shown in Fig. 3, when k = 1 (that is, when measuring from the first time to m times), the parts corresponding to -number circuits (71) and (72) are simplified. be able to. FIG. 4 is a block diagram showing another embodiment of the second invention, in which the same reference numerals as in FIG. 3 indicate the same or corresponding parts, and (60) is a brisset counter.

Also, all the parts omitted in FIG. 4 are the same as in FIG. 3.

At the time of initialization, the preset counter (60) is preset to a value m, and the flip-flop (75) is set. The preset counter (60) is connected to count down the output of the flip-flop (3) at the time of the -match detection signal of the end address match detection section (2ON, see Figure 3), and the contents gradually decrease. ,0
When this happens, an overflow pulse is output to reset the flip-flop (75).

FIG. 5 is an operation time chart showing the operation of the circuit shown in FIG. 4, in which execution address, start address match, and end address match correspond to the same names in FIG. 8, and the measurement start pulse is determined by this pulse. Initialization is performed and measurement is started, and the period between the start and end addresses is also expressed as a count enable, indicating the opposite logic of the Q terminal of the flip-flop (3), and the remaining number of measurements is counted by the preset counter (60
). Also, the end of the measurement is the flip-flop (
75) shows the opposite logic of the Q terminal.

When measuring data separately for each time using the circuit shown in FIG. 3, it is necessary to store these data separately. Techniques for writing data to or reading data from memory are well known, so a description thereof will be omitted.

FIG. 6 is a block diagram showing the timing of data writing. In FIG. 6, the same symbols as in FIG. 3 indicate the same or corresponding parts, and (53), (54), and (55) are delay circuits, respectively; (8) is a latch.

After the measurement for that time is completed by the coincidence detection signal from the end address coincidence detection section 2), an appropriate delay is given by the delay circuit (53), and then the contents of the timer counter (50) are latched (8). At the same time, the address counter (not shown) is incremented by 1, and after that process is completed,
The timer counter (50) is delayed by the delay circuit (54).
) to reset. The contents of the latch (8) may be written to a memory (not shown) at the time of output of the delay circuit (55).

Note that although the above embodiment describes the case of detecting a match of addresses, the same applies to the case of detecting a match of data signals or a match of timing signals inside an information processing device.
This invention can be applied.

[Effects of the Invention] As explained above, the present invention has the advantage that it is possible to separately measure the time from the start address to the end address within a predetermined number of appearances range.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the first invention;
FIG. 3 is a block diagram showing an embodiment of the second invention; FIG. 4 is a block diagram showing another embodiment of the second invention; 5 is an operation time chart showing the operation of the device shown in FIG. 4, FIG. 6 is a block diagram showing the timing of data writing in the circuit shown in FIG. 3, FIG. 7 is a block diagram showing the conventional device, FIG. 8 is an operation time chart showing the operation of the apparatus shown in FIG. In the figure, (1) is a start address match detection section, (2> is an end address match detection section, (3) is a flip-flop,
(4) is an AND gate, (5) is a timer, (50) is a timer counter, (51) is a clock generator, and (6) is a counter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A start address match detection unit that detects a point in time when an execution address of an information processing device matches a predetermined start address; an end address match that detects a point in time when the execution address matches an end address corresponding to the start address; a detection unit, a flip-flop that is set by the match detection signal of the start address match detection unit and reset by the match detection signal of the end address match detection unit; resets the flip-flop at the time of initialization; A counter that counts the number of transitions from a reset state to a set state; when the counter is reset at the time of initialization and the predetermined number of times is n (n is a positive integer), the count value of the counter is n. The period is an information processing device operation comprising means for outputting a logic "1" signal, and a timer for measuring the time while the flip-flop is set while the logic "1" signal is being output. measuring device. (2) A start address match detection unit that detects a point in time when an execution address of an information processing device matches a predetermined start address; an end address match that detects a point in time when the execution address matches an end address corresponding to the start address; a detection unit, a flip-flop that is set by the match detection signal of the start address match detection unit and reset by the match detection signal of the end address match detection unit; resets the flip-flop at the time of initialization; A counter that measures the number of transitions from a reset state to a set state, when the above counter is reset at the time of initialization and the predetermined number of times is m and k (m and k are positive integers and k<m), the above A means for outputting a logic "1" signal during a period when the count value of the counter is between k and m+1; a period during which this logic "1" signal is output, a time during which the flip-flop is in the set state; An information processing equipment operation measuring device comprising: a timer for measuring each time; and means for processing the measured values of the timer. (3) The information processing equipment operation measuring device according to claim 2, wherein the means for processing the measured values of the timer comprises means for storing each of these measured values in a storage section.