JPH03212750A - Memory data maintainability checking system - Google Patents

Abstract

PURPOSE:To check the maintainability of data in an instruction area and to improve reliability by converting an instruction into a dummy NOP instruction by a diagnostic NOP instruction and executing the dummy NOP instruction to execute the memory reading test of an instruction area. CONSTITUTION:The diagnostic NOP instruction and a diagnostic NOP releasing instruction are previously and respectively set up in the leading and final addresses of a program in the instruction area of the memory. When a diagnostic NOP flag 100 is set up by specifying diagnostic NOP setting, all instructions to be decoded by an instruction decoding circuit 70 are processed as NOP instructions. Since the memory reading test of the instruction area of the memory 20 is executed, maintainability of data in the instruction area of the memory 20 can be checked prior to the execution of the program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing system, and in particular to an information processing system in which an instruction area and a data area are separated and parity check and ECC (Error Control) are performed.
r Correcting C.

The present invention relates to a memory data integrity check method in an information processing system in which the integrity of data (instructions in an instruction area and narrowly defined data in a data area) is checked (confirmed) when reading out a memory by checking or the like.

[Conventional technology]

In order to improve the integrity of data in the memory of an information processing system, a parity bit or ECC pin is added to each data of an arbitrary number of pins when writing to the memory, and the data is written at the same time as the data, and a parity check and E
A commonly used method is to perform a CC check to detect a 1-bit or 2-bit data error (in the case of an ECC check, 1-bit data is also corrected).

When the above method is used to improve the integrity of memory data, the following memory data integrity check method is used.

First, when the information processing system is initially started up, a write/continue test is performed on the data area of the memory to confirm the integrity of the data in the data area.

Furthermore, regarding the 6i L's of data integrity in a data area after the information processing system is started up, a write/continue test is performed on a specific data area using a special diagnostic processor.

On the other hand, regarding the instruction area of the memory, a method has been used in which the integrity of the data is checked by reading out the instructions as data in the data area after starting up the information processing system.

[Problem to be solved by the invention]

In the conventional memory data integrity checking method described above,
When checking the integrity of data (instructions) in the instruction area, there is a drawback that the complicated process of reading out the instructions as data in the data area must be performed.

In addition, in an information processing system that has a memory in which the instruction area and data area are completely independent, it is impossible to read the contents (instructions) of the instruction area as data, so conventional memristor integrity checks This method has the disadvantage that the integrity of data in the instruction area cannot be confirmed until the instruction is executed.

In view of the above points, an object of the present invention is to diagnose N0P (No.
By executing the instruction (data in the instruction area) as a pseudo NOP instruction using the instruction (0Peration) and performing a memory succession test in the instruction area, the integrity of the data in the instruction area can be easily checked before executing the instruction ( check)
An object of the present invention is to provide a memory data integrity checking method that can perform a memory data integrity check.

[Means to solve the problem]

The memory data integrity check method of the present invention has an instruction area and a data area separated, and parity check and E
In an information processing system that includes a memory in which data is checked during memory reading such as a CC check, and a microprocessor that controls the memory, a diagnostic NOP flag that is set by a diagnostic NOP setting instruction and reset by a diagnostic NOP cancellation instruction is provided. , issues a diagnostic NOP setting instruction by decoding the diagnostic NOP instruction to set the diagnostic NOP flag, and NOPs subsequent instructions with the diagnostic NOP instruction based on the setting of the diagnostic NOP flag.
A diagnostic NOP command setting means in the command decoding circuit that handles the command as a command, and this diagnostic N.

A diagnostic NOP that holds a diagnostic NOP command next address based on a diagnostic NOP setting instruction issued from the P command setting means.
An instruction that issues a diagnostic NOP release instruction by decoding the address register and the diagnostic NOP release instruction, resets the diagnostic NOP flag, and stores the next address of the diagnostic NOP instruction held in the diagnostic NOP address register in the instruction address register. and diagnostic NOP command canceling means within the decoding circuit.

[Effect]

In the memory data integrity checking method of the present invention, diagnosis N
The OP flag is set by the diagnostic NOP setting instruction and reset by the diagnostic NOP release instruction, and the diagnostic NOP instruction setting means in the instruction decoding circuit issues a diagnostic NOP setting instruction by decoding the diagnostic NOP instruction, sets the diagnostic NOP flag, and performs diagnosis. A diagnostic NOP instruction based on the setting of the NOP flag treats subsequent instructions as NOP instructions, and the diagnostic NOP address register is set as a diagnostic NOP instruction based on a diagnostic NOP setting instruction issued from the diagnostic NOP instruction setting means.
Holds the instruction next address and uses the diagnostic NOP in the instruction decoding circuit
The command canceling means decodes the diagnosis NOP cancellation command.
Issues an OP release instruction, resets the diagnostic NOP flag, and returns the diagnostic NO held in the diagnostic NOP address register.
Store the P instruction next address address in the instruction address register.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the memory data integrity checking method of the present invention.

The memory data integrity check method of this embodiment includes a microprocessor 10, a memory 20, an instruction address bus 40, an instruction data bus 50, and an error check circuit 1.
30.

Microprocessor IO is an instruction address register 30
, an instruction register 60, an instruction decoding circuit 70 (inside the instruction decoding circuit 70, a diagnostic NOP command setting means 71 and a diagnostic NOP command canceling means 72 are newly added compared to the conventional technology), and a diagnostic NOP instruction circuit 70. Setting instruction signal line 80, diagnosis NOP cancellation instruction signal line 90, diagnosis NOP flag 100, diagnosis NOP instruction signal line 110, diagnosis NOP
The address register 120 is configured to include an address register 120.

Next, the operation of the memory data integrity check system of this embodiment configured as described above will be explained.

The microprocessor 10 has an instruction address register 30
The instruction address set in the instruction address bus 4
0 to the memory 20, and reads the instruction from the instruction area of the memory 20 via the instruction data node 50.

Parity bits or ECC bits are added to data (including instructions) in memory 20 for the purpose of ensuring data integrity. The error check circuit 130 is
Parity check or ECC check is performed using this parity via) or ECC bit, and when an error is detected, error interrupt processing is executed.

The instructions read out via the instruction data 50 are stored in an instruction register 60 within the microprocessor 10.

The instruction decoding circuit 70 decodes the contents of the instruction register 60 and executes the instruction based on the decoding.

Here, when the diagnostic NOP command setting means 71 in the command decoding circuit 70 decodes the diagnostic NOP command, it performs the following processing.

First, a diagnostic NOP setting instruction is issued to the diagnostic NOP setting instruction signal vA80.

By issuing this diagnostic NOP setting instruction, the diagnostic NOP flag 100 is set, and the address of "diagnostic NOP instruction address + 1" (herein, this address is referred to as the diagnostic NOP instruction next address) is stored in the diagnostic NOP address register 120. do.

Furthermore, the diagnostic NOP flag 1 is set by the diagnostic NOP setting instruction.
If set to 00, the diagnosis NOP based on that set.
Due to the diagnostic NOP instruction via the instruction signal NlA110,
Subsequent instructions (instruction decoding circuit 7 via instruction register 60)
All instructions decoded by 0 are treated as NOP instructions.

As a result, the diagnosis NOP command setting means 71
After the OP instruction is decoded, the instructions in the instruction area of the memory 20 are read out address by address, and a parity check or an ECC check (memory read test) is performed by the error check circuit 130.

If a diagnostic NOP cancellation instruction exists among the instructions being read out in this way, the diagnostic NOP instruction cancellation means 72 in the instruction decoding circuit 70 decodes the diagnostic NOP cancellation instruction and performs the following processing. .

First, a diagnostic NOP cancellation instruction is issued to the diagnostic NOP cancellation instruction signal line 90.

With this diagnosis NOP cancellation instruction, the diagnosis NOP flag 10
0 is reset, the contents of the diagnostic NOP address register 120 (diagnostic NOP instruction next address) are stored in the instruction address register 30, and the instructions in the instruction area of the memory 20 are re-executed from the diagnostic NOP instruction next address.

As can be seen from the above operations, a diagnostic NOP instruction is set in advance at the first address of the program (a set of instructions) in the instruction area of the memory 20, and a diagnostic NOP release instruction is set at the last address. By this, memory 20
A memory continuation test is performed in the instruction area of the memory 20 (parity check or ECC check is performed by the error check circuit 130), and the integrity of the data (instructions) in the instruction area of the memory 20 is verified before program (instruction) execution. It can be confirmed.

〔Effect of the invention〕

As explained above, the present invention ensures the integrity of data in the instruction area (a program that is a set of instructions) by executing the instruction as a pseudo NOP instruction using the diagnostic NOP instruction and performing a memory read test of the instruction area. It is possible to easily perform f111 verification (check) before executing a program, which has the effect of improving the reliability of the information processing system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 10... Microprocessor, 20... Memory, 30... Instruction address register, 40... Instruction address bus, 50... Instruction data bus, 60... Instruction register, 70... - Command decoding circuit, 71... Diagnostic NOP command setting means, 72... Diagnostic NOP command canceling means, 80... Diagnostic NOP setting instruction signal line, 90... Diagnostic NOP canceling instruction signal line, 100... Diagnostic NOP flag, 110...Diagnostic NOP instruction signal line, 120...Diagnostic NOP address register, 130...Error check circuit.

Claims (1)

[Scope of Claims] An information processing system comprising a memory in which an instruction area and a data area are separated and data checks such as a parity check and an ECC check are performed during memory reading, and a microprocessor that controls the memory. A diagnostic NOP flag is set by a diagnostic NOP setting instruction and reset by a diagnostic NOP cancellation instruction; A diagnostic NOP instruction setting means in an instruction decoding circuit that treats subsequent instructions as NOP instructions based on the diagnostic NOP instruction, and a diagnostic NOP issued from this diagnostic NOP instruction setting means.
A diagnostic NOP address register holds the next address of the diagnostic NOP command based on the setting instruction, and a diagnostic NOP release command is issued by decoding the diagnostic NOP release command and the diagnostic NOP
A diagnostic N in the instruction decoding circuit that resets the P flag and stores the diagnostic NOP instruction next address held in the diagnostic NOP address register in the instruction address register.
1. A memory data integrity check method comprising: OP command release means.