JPH03212799A - Two-wire type gauge - Google Patents
Two-wire type gaugeInfo
- Publication number
- JPH03212799A JPH03212799A JP915490A JP915490A JPH03212799A JP H03212799 A JPH03212799 A JP H03212799A JP 915490 A JP915490 A JP 915490A JP 915490 A JP915490 A JP 915490A JP H03212799 A JPH03212799 A JP H03212799A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- signal
- terminal
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、負荷側から2線の伝送線を介して電源の供給
を受けて測定すべき物理量を電気信号に変換しこれをマ
イクロプロセッサにより信号処理をして伝送線を介して
負荷に電流信号として伝送する2線式計器に係り、特に
この2線式計器の環境条件の異常を検出するように改良
された2線式計器に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention receives power from the load side via a two-wire transmission line, converts a physical quantity to be measured into an electrical signal, and converts this into an electrical signal using a microprocessor. The present invention relates to a two-wire meter that processes signals and transmits them as a current signal to a load via a transmission line, and particularly relates to a two-wire meter that has been improved to detect abnormalities in the environmental conditions of the two-wire meter.
〈従来の技術〉
第8図は従来のいわゆる2線式計器の構成の概要を示す
構成図である。<Prior Art> FIG. 8 is a block diagram showing an outline of the structure of a conventional so-called two-wire meter.
マイクロプロセッサを含む2線式計器10は、負荷11
側から直流電源12により2線の伝送線J2+ 、12
を介し入力端子T + 、T 2を通じて電流の供給を
受けてこの電流から回路電源を作ると共に測定すべき物
理量を検出してこれを電流信号の変化として、同一の伝
送線I+ 、12を通じて例えば4〜20mAの統一さ
れた統一電流ILの形で負荷11に伝達する。A two-wire instrument 10 including a microprocessor is connected to a load 11
The two-wire transmission line J2+, 12 is connected by the DC power supply 12 from the side.
A current is supplied through the input terminals T+ and T2, and this current is used to generate a circuit power supply, and the physical quantity to be measured is detected and converted into a change in the current signal through the same transmission line I+ and 12, for example, 4. It is transmitted to the load 11 in the form of a uniform unified current IL of ~20 mA.
このうち最小の電流は4mAであるが、通常この電流は
ゼロ点の調整・確認のため3.2mA〜3.6mA程度
での動作が要求され、2線式計器10での消費電流に対
する制限が大きい。特に、最近は多機能化の要求を満た
すためこの2線式計器10にマイクロコンピュータが導
入されその電力に対する要求が厳しくなっている。Among these, the minimum current is 4 mA, but normally this current is required to operate at around 3.2 mA to 3.6 mA for zero point adjustment and confirmation, and there is a limit on the current consumption in the two-wire meter 10. big. In particular, recently, a microcomputer has been introduced into the two-wire meter 10 in order to meet the demand for multi-functionality, and the requirements for its power have become stricter.
その電源回路の具体的な構成の1例を第9図に示す。An example of a specific configuration of the power supply circuit is shown in FIG.
入力端子T1、T2には端子電圧7丁として通常10V
程度が供給され、マイクロプロセッサ14の電源電圧V
cは5vなので、この電圧差を利用して供給電流を増加
させるためにスイッチングレギュレータ13が用いられ
ている。Input terminals T1 and T2 are normally 10V as 7 terminal voltages.
level is supplied, and the power supply voltage V of the microprocessor 14
Since c is 5V, the switching regulator 13 is used to increase the supplied current by utilizing this voltage difference.
スイッチングレギュレータ13はその入力端子T1、T
2の両端にコンデンサC1が接続され、スイフチSW、
とコイルし、との直列回路を介してマイクロプロセッサ
14の電源回路に接続され、コイルし、の両端にはダイ
オードD、とコンデンサC2の一端がそれぞれ接続され
、これ等の他端は入力端子T2に接続されている。The switching regulator 13 has its input terminals T1, T
A capacitor C1 is connected to both ends of the switch SW,
The coil is connected to the power supply circuit of the microprocessor 14 through a series circuit with the coil, and one end of a diode D and a capacitor C2 are connected to both ends of the coil, and the other end of these is connected to the input terminal T2. It is connected to the.
この電源電圧vcは制御回路15で検出され内蔵された
所定の基準値と比較されて比較信号が例えばアンドゲー
トに印加され、このアンドゲートの他端に印加されてい
る内蔵された発振器からの周波数の高い発振周波数を比
較信号でオン/オフ制御してこのアンドゲートの出力端
に得られるスイッチング信号によりスイッチSW1をオ
ン/オフ制御する。This power supply voltage vc is detected by the control circuit 15 and compared with a predetermined built-in reference value, and a comparison signal is applied to, for example, an AND gate, and a frequency signal from a built-in oscillator that is applied to the other end of the AND gate is applied. The high oscillation frequency of is controlled on/off by the comparison signal, and the switch SW1 is controlled on/off by the switching signal obtained at the output terminal of this AND gate.
スイッチSW1が閉じられるとコイルL1に電流が注入
され、次にスイッチSW、が開かれると、この間はコイ
ルし、に蓄積されたエネルギがダイオードD1を介して
放出され電源電圧vcが作られる。When the switch SW1 is closed, a current is injected into the coil L1, and when the switch SW is then opened, the energy stored in the coil during this time is released through the diode D1 to create the power supply voltage vc.
この場合の電源電圧Vcは制御回路15に内蔵されてい
る基準電圧を変更してスイッチSW1の開閉時間を変え
て任意に変えることができる。The power supply voltage Vc in this case can be arbitrarily changed by changing the reference voltage built into the control circuit 15 and changing the opening/closing time of the switch SW1.
く本発明が解決しようとする課題〉
しかしながら、端子電圧7丁と統一電流Iしについては
、例えば12V≦V、≦45V、4mA≦工し≦20m
Aなどの動作範囲の仕様であるが、これを外れた場合で
も異常な動作をしないことが要求される。特に、VT
< 12 V、 I 1 <4 mAのように信号処理
回路としてのマイクロプロセッサ14に十分な電力を供
給できない場合にも異常動作を防止する必要がある。Problems to be Solved by the Present Invention> However, regarding the terminal voltage 7 and the unified current I, for example, 12V≦V, ≦45V, 4mA≦work≦20m
Although it is a specification of an operating range such as A, it is required that no abnormal operation occurs even if the operating range is outside this range. In particular, V.T.
It is necessary to prevent abnormal operation even when sufficient power cannot be supplied to the microprocessor 14 as a signal processing circuit, such as <12 V and I 1 <4 mA.
演算増幅器などのアナログ回路のみで信号処理回路を構
成しているときにはこの様な異常時の出力をダウンさせ
るのは比較的容易であったが、マイクロプロセッサが信
号処理回路として使用されるときには初期化(リセット
)と警報が確実に実行されないと異常動作を起こす機会
が多くなり、安定性を欠くという問題がある。When a signal processing circuit consists of only analog circuits such as operational amplifiers, it is relatively easy to reduce the output in the event of an abnormality like this, but when a microprocessor is used as a signal processing circuit, it is difficult to initialize the circuit. If (reset) and alarms are not reliably executed, there will be a problem of increased chances of abnormal operation and lack of stability.
く課題を解決するための手段〉
本発明は、以上の課題を解決するために、負荷側がら2
線の伝送線を介して電源の供給を受けて?l!’I定す
べき物理量を電気信号に変換しこれをマイクロプロセッ
サにより信号処理をして伝送線を介して負荷に電流信号
として伝送する2線式計器において、伝送線の両端に発
生する端子電圧のレベルを変換して第1電圧を作るスイ
ッチングレギュレータと一端子電圧を安定化して第2電
圧を作る安定化電源回路と、この第2電圧によって動作
し端子電圧の投入・停止・低下と第1電圧の監視を実行
して初期化信号と警報信号とを出力する自己診断回路と
、第1電圧によって動作し初期化信号と警報信号により
制御されるマイクロプロセッサを含む信号処理手段とを
具備するようにしたものである。Means for Solving the Problems> In order to solve the above problems, the present invention provides two solutions from the load side.
Receiving power supply through line transmission line? l! In a two-wire meter that converts the physical quantity to be determined into an electrical signal, processes the signal using a microprocessor, and transmits it as a current signal to the load via a transmission line, the terminal voltage generated at both ends of the transmission line is measured. A switching regulator that converts the level and creates a first voltage, a stabilizing power supply circuit that stabilizes one terminal voltage and creates a second voltage, and a stabilizing power supply circuit that operates based on this second voltage and turns on, stops, and lowers the terminal voltage and the first voltage. and a signal processing means including a microprocessor operated by the first voltage and controlled by the initialization signal and the alarm signal. This is what I did.
く作 用〉
スイッチングレギュレータにより伝送線の両端に発生す
る端子電圧のレベルを変換して第1電圧を作ると共に安
定化電源回路により端子電圧を安定化して第2電圧を作
る。Function> A switching regulator converts the level of the terminal voltage generated at both ends of the transmission line to create a first voltage, and a stabilizing power supply circuit stabilizes the terminal voltage to create a second voltage.
自己診断回路はこの第2電圧によって動作し端子電圧の
投入・停止・低下と第1電圧の監視を実行して初期化信
号と警報信号とを出力する。The self-diagnosis circuit is operated by this second voltage, turns on, stops, and lowers the terminal voltage, monitors the first voltage, and outputs an initialization signal and an alarm signal.
そして、マイクロプロセッサはこの第1電圧によって動
作され初期化信号と警報信号により制御されるようにし
て環境条件の異常を検出する。The microprocessor is operated by the first voltage and controlled by the initialization signal and the alarm signal to detect abnormal environmental conditions.
〈実施例〉
以下、本発明の実施例について図を用いて説明する。第
1図は本発明の1実施例の構成を示すブロック図である
。なお、第8図と第9図に示す回路と同一の機能を有す
る要素には同一の符号を付して適宜にその説明を省略す
る。<Examples> Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Note that elements having the same functions as the circuits shown in FIGS. 8 and 9 are designated by the same reference numerals, and their explanations will be omitted as appropriate.
16は2線式計器であり、この2線式計器16はスイッ
チングレギュレータ13、安定化電源回路17、自己診
断回路18、およびマイクロプロセッサを含む信号処理
回路19などにより構成されている。そして、信号電圧
Vsは入力端子T。Reference numeral 16 denotes a two-wire meter, and the two-wire meter 16 includes a switching regulator 13, a stabilized power supply circuit 17, a self-diagnosis circuit 18, a signal processing circuit 19 including a microprocessor, and the like. The signal voltage Vs is applied to the input terminal T.
とT2にそれぞれ接続された伝送線1+ −12に直列
に接続された抵抗R1の両端で検出されて信号処理図#
r19に出力され、ここで信号処理がなされて出力端子
T0に出力される。Signal processing diagram #
The signal is output to r19, where it undergoes signal processing and is output to output terminal T0.
スイッチングレギュレータ13は端子電圧vTが入力さ
れ、これをレベル変換して信号処理回路1つに第1電圧
として回路電圧Vcを出力するが、端子電圧VTの入力
に対して回路電圧Vcの立上りが遅くしかも負荷電流も
大きいので、回路電圧■cが安定になるのは安定化電源
回路17より一般に後になる。The switching regulator 13 receives the terminal voltage vT, converts the level of this, and outputs the circuit voltage Vc as a first voltage to one signal processing circuit, but the rise of the circuit voltage Vc is slow with respect to the input of the terminal voltage VT. Moreover, since the load current is large, the circuit voltage (2) c generally becomes stable after the stabilized power supply circuit 17.
安定化電源回路17は端子電圧■Tが入力され、その出
力端に第2電圧として定電圧■kを出力する。この安定
化電源回路17は、トランジスタQ1、抵抗R2、ツェ
ナダイオードD2などで構成されている。そして、端子
電圧vTが抵抗R2とツェナダイオードD2との直列回
路に印加されてツェナダイオードD2の両端に発生した
ツェナー電圧を基準として動作し対応する定電圧vKを
出力端に出力するが、この安定化電源回路17は端子電
圧V丁が回路が動作出来る電圧まで上がると直ちに動作
して定電圧■にを自己診断回路18に出力することがで
きる。The stabilized power supply circuit 17 receives the terminal voltage ■T as input, and outputs a constant voltage ■k as a second voltage to its output terminal. This stabilized power supply circuit 17 includes a transistor Q1, a resistor R2, a Zener diode D2, and the like. Then, the terminal voltage vT is applied to the series circuit of the resistor R2 and the Zener diode D2, and the Zener diode D2 operates based on the Zener voltage generated across the terminals, and outputs the corresponding constant voltage vK to the output terminal. The constant voltage power supply circuit 17 operates immediately when the terminal voltage V rises to a voltage at which the circuit can operate, and can output a constant voltage to the self-diagnosis circuit 18.
なお、第1図では安定化電源回路17としてトランジス
タを用いる構成として説明したが、このトランジスタQ
1は必ずしも必要ではなく、抵抗R2とツェナダイオー
ドD2の直列回路としてこのツェナダイオードD2の両
端の電圧を定電圧Vkとする構成としても良い。In addition, in FIG. 1, the configuration is explained in which a transistor is used as the stabilized power supply circuit 17, but this transistor Q
1 is not necessarily necessary, and a series circuit of a resistor R2 and a Zener diode D2 may be used, and the voltage across the Zener diode D2 may be set to a constant voltage Vk.
自己診断回路18は、抵抗R3、R4、R5、R6、コ
ンデンサC3、ヒステリシスを持つインバータQ2、R
/SフリップフロップFF1、比較器Q3、基準電圧源
E1などで構成されるリセット信号発生回路20と、抵
抗R7、R8、基準電圧源E2、比較器Q4などで構成
される異常検知回路21などで構成されている。The self-diagnosis circuit 18 includes resistors R3, R4, R5, R6, a capacitor C3, and inverters Q2 and R6 with hysteresis.
/S flip-flop FF1, comparator Q3, reference voltage source E1, etc., and a reset signal generating circuit 20, resistors R7, R8, reference voltage source E2, comparator Q4, etc., and an abnormality detection circuit 21, etc. It is configured.
まず、リセット信号発生回路20について説明する。First, the reset signal generation circuit 20 will be explained.
定電圧vKを抵抗R3とR4で分圧した分圧電圧がイン
バータQ2の入力端に印加される。インバータQ2の出
力端はR/Sフリヅプフロッ1FF1のセット端子Sに
接続されている。このリセット端子Rは、スイッチング
レギュレータ13の出力である回路電圧Vcを抵抗R5
とR6で分圧された分圧電圧が非反転入力@(+)に印
加され反転入力端(−)には基準電圧E1が印加された
比較器Q3の出力端が接続されている。そして、R/S
フリップフロップFFIの出力端Qからリセット信号R
3が信号処理回路19に出力されている。A divided voltage obtained by dividing the constant voltage vK by resistors R3 and R4 is applied to the input terminal of the inverter Q2. The output terminal of the inverter Q2 is connected to the set terminal S of the R/S flip-flop 1FF1. This reset terminal R connects the circuit voltage Vc, which is the output of the switching regulator 13, to the resistor R5.
The divided voltage divided by and R6 is applied to the non-inverting input @(+), and the output terminal of the comparator Q3 to which the reference voltage E1 is applied is connected to the inverting input terminal (-). And R/S
Reset signal R from output terminal Q of flip-flop FFI
3 is output to the signal processing circuit 19.
以上の構成で、電源が投入されるとインバータQ2を介
してR/SフリップフロップFF1がセットされる。With the above configuration, when the power is turned on, the R/S flip-flop FF1 is set via the inverter Q2.
一方、回路電圧■cは端子電圧vTが立ち上がっても暫
くの間は正規の電圧とはならず、このためR/Sフリッ
プフロッ1FFIのリセット端子Rはローレベルに保持
されその出力端Qからマイクロプロセッサを含む信号処
理回路19にリセット信号(初期化信号)R8を与え続
けている。しかし、回路電圧VCがある値、例えば信号
処理図B19が動作する最低電圧に対応する基準電圧E
1を越えると比較器Q3の出力がハイレベルに反転しR
/SフリップフロップFFIのリセット端子Rをハイレ
ベルにしてその出力端Qに出ていたリセット信号R5を
解除する。この回路電圧VCの最低の値としては例えば
4.75Vなどが選択される。以上のようにしてマイク
ロプロセッサは確実に初期化される。On the other hand, the circuit voltage c does not become a normal voltage for a while even if the terminal voltage vT rises, so the reset terminal R of the R/S flip-flop 1FFI is held at a low level and the output terminal Q is connected to the microprocessor. The reset signal (initialization signal) R8 continues to be applied to the signal processing circuit 19 including the. However, the circuit voltage VC has a certain value, for example, the reference voltage E corresponding to the lowest voltage at which the signal processing diagram B19 operates.
When it exceeds 1, the output of comparator Q3 is inverted to high level and R
The reset terminal R of the /S flip-flop FFI is set to high level, and the reset signal R5 outputted to its output terminal Q is released. For example, 4.75V is selected as the lowest value of this circuit voltage VC. As described above, the microprocessor is reliably initialized.
次に、異常検知回路21について説明する。通常、スイ
ッチングレギュレータ13などにはコンデンサが含まれ
ているので外部電源が低下しても直ぐに回路が死ぬこと
はない。Next, the abnormality detection circuit 21 will be explained. Normally, the switching regulator 13 and the like include a capacitor, so even if the external power supply drops, the circuit will not die immediately.
そこで、この異常検知回路21が外部電源としての直流
電源12の電圧の異常低下を早期に検知して警報信号A
Lを信号処理回路1つに出力する。Therefore, this abnormality detection circuit 21 detects an abnormal drop in the voltage of the DC power supply 12 as an external power supply at an early stage and sends an alarm signal A.
Output L to one signal processing circuit.
この異常低下を検知する値としては、例えば仕様最低電
圧などが選定され、これは基準電圧E2で設定される。As a value for detecting this abnormal drop, for example, a specified minimum voltage is selected, and this is set by the reference voltage E2.
信号処理回路19はこの警報信号ALを検知すると重要
なパラメータの退避、或いは動作の固定などを行い異常
動作を防止する。When the signal processing circuit 19 detects this alarm signal AL, it saves important parameters or fixes the operation to prevent abnormal operation.
第2図はリセット信号発生回路の第2の実施例を示す回
路図である。FIG. 2 is a circuit diagram showing a second embodiment of the reset signal generating circuit.
これは、回路電圧Vcが、例えば4.75V以下なら電
源投入直後と想定される場合に、回路電圧■cの検知が
電源投入を兼ねるように構成したものである。This is configured so that if the circuit voltage Vc is, for example, 4.75 V or less, it is assumed that the power has just been turned on, and the detection of the circuit voltage c also serves as the power-on.
比較器Q4の出力をインバータQ5を介してリセット信
号R3を取り出す。なお、比較器Q4にはヒステリシス
を持たせるために抵抗R9で正帰還がかけられている。A reset signal R3 is taken out from the output of the comparator Q4 via an inverter Q5. Note that positive feedback is applied to the comparator Q4 through a resistor R9 to provide hysteresis.
第3図はリセット信号発生回路の第2の実施例を示す回
路図である。FIG. 3 is a circuit diagram showing a second embodiment of the reset signal generating circuit.
この実施例はマイクロプロセッサなどは回路電圧Vcが
4.75V以上になっても一定時間以上はリセットをか
け続ける必要がある。この様な場合に遅延回路によりリ
セット時間を長くするように構成したものである。In this embodiment, even if the circuit voltage Vc becomes 4.75V or more, it is necessary to continue resetting the microprocessor for a certain period of time or more. In such a case, a delay circuit is used to lengthen the reset time.
オア回路Q6の入力の一端にはリセット信号R8が、そ
の他端には遅延回路りして所定時間τだけ遅延された遅
延信号ΔR3がそれぞれ入力され、オア回路Q6でこれ
等の論理和か演算されてこの出力端に得られたリセット
信号R3−により信号処理回路1つをリセットする。The reset signal R8 is input to one end of the input of the OR circuit Q6, and the delayed signal ΔR3 delayed by a predetermined time τ by a delay circuit is input to the other end, and the OR circuit of these signals is operated in the OR circuit Q6. One signal processing circuit is reset by the reset signal R3- obtained at the output terminal of the lever.
この場合のタイミング図を第4図に示す。(イ)に示す
リセット信号R3に対して(ロ)に示す遅延時間τだけ
遅延された遅延信号ΔR3により(ハ)に示すようにリ
セット信号R3−のパルス幅が拡大されている。A timing diagram in this case is shown in FIG. The pulse width of the reset signal R3- is expanded as shown in (c) by the delay signal ΔR3 which is delayed by the delay time τ shown in (b) with respect to the reset signal R3 shown in (a).
第5図は第3図に示す遅延回路DLの第2の実施例を示
す回路図である。FIG. 5 is a circuit diagram showing a second embodiment of the delay circuit DL shown in FIG. 3.
この場合は、インバータQ7、抵抗RIO、コンデンサ
C4、ヒステリシスを持つインバータQ8により遅延回
路を構成している。In this case, a delay circuit is configured by an inverter Q7, a resistor RIO, a capacitor C4, and an inverter Q8 with hysteresis.
第6図はリセット信号発生回路の第3の実施例を示す回
路図である。FIG. 6 is a circuit diagram showing a third embodiment of the reset signal generating circuit.
この場合は、R/SフリップフロップFF2.2n+1
カウンタCTを用いて構成した場合を示している。In this case, R/S flip-flop FF2.2n+1
A case is shown in which a counter CT is used.
リセット信号R3はR/SフリッグフロッグF■パ2の
セット端子Sに入力されると共にカウンタCTのリセッ
ト#!Rに入力される。一方、カウンタCTのクロック
f@CLにはタロツク信号CLKが入力され、その計数
結果は出力端QπからR/SフリップフロップFF2の
リセット端子Rに出力され、その出力端Qから遅延され
たリセット信すjjS−が出力される。The reset signal R3 is input to the set terminal S of the R/S flip frog F■P2 and reset #! of the counter CT. input to R. On the other hand, the tally clock signal CLK is input to the clock f@CL of the counter CT, the counting result is output from the output terminal Qπ to the reset terminal R of the R/S flip-flop FF2, and the delayed reset signal is output from the output terminal Q. SjjS- is output.
リセット信号R3かローレベルになってからタロツク信
号CLKを2n数えて立ち上がり、その出力をR/Sフ
リップフロップFF2のリセット端子Rに印加する。こ
れによりその出力端Qがら出される反転されたリセット
信号R3−により信号処理回路19のリセットが解除さ
れる。After the reset signal R3 becomes low level, the tarlock signal CLK is counted 2n and rises, and its output is applied to the reset terminal R of the R/S flip-flop FF2. As a result, the reset of the signal processing circuit 19 is canceled by the inverted reset signal R3- outputted from the output terminal Q.
第7図は異常検知回路の他の実施例を示す回路図である
。FIG. 7 is a circuit diagram showing another embodiment of the abnormality detection circuit.
この実施例は仕様より遥かに低い電圧を下回ったときに
警報信号としてタウン信号DWNをも出力できるように
構成したものである。This embodiment is configured so that a town signal DWN can also be output as an alarm signal when the voltage falls below the specification.
端子電圧vTを抵抗R8、R11、R12で分圧し、抵
抗R8とR11との接続点の電圧を電圧E2が印加され
た比較器Q9の反転入力端(−)に印加して、その出力
端から信号処理回路19にタウン信号DWNを出力する
。Terminal voltage vT is divided by resistors R8, R11, and R12, and the voltage at the connection point of resistors R8 and R11 is applied to the inverting input terminal (-) of comparator Q9 to which voltage E2 is applied, and from its output terminal. A town signal DWN is output to the signal processing circuit 19.
また、異常信号の検知としては第1図に示すスイッチン
グレギュレータ13のスイッチSW、をオンにするデユ
ーティが規定以上になったときには負荷電流が入力電流
に比べて多くなっているので、これを検出して警報信号
としても良い。In addition, to detect an abnormal signal, when the duty of turning on the switch SW of the switching regulator 13 shown in Fig. 1 exceeds the specified value, the load current is larger than the input current, so this is detected. It can also be used as a warning signal.
〈発明の効果〉
以上、実施例と共に具体的に説明したように本発明によ
れば、自己診断回路はマイクロプロセッサより早く立ち
上がる第2電圧で動作するので、電源投入のときに確実
に初期化をすることができ、また外部電源の低下・停電
を検出しているのでマイクロプロセッサ側で異常動作を
防止する対策が容易に行うことができる。さらに、第2
電圧は簡単な安定化電源で構成するので電力利用率が低
いか、これを利用するのは自己診断回路だけであり、信
号処理回路はスイッチングレギレータの第1電圧を使う
ので全体として電力の有効利用が可能となり、2線式計
器で重要な回路の低電力化を図ることができる。<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, the self-diagnosis circuit operates with the second voltage that rises earlier than the microprocessor, so it is possible to ensure initialization when the power is turned on. Moreover, since a drop in the external power supply or a power outage is detected, it is possible to easily take measures to prevent abnormal operation on the microprocessor side. Furthermore, the second
The voltage is configured with a simple stabilized power supply, so the power utilization rate is low. Only the self-diagnosis circuit uses this, and the signal processing circuit uses the first voltage of the switching regulator, so the overall power efficiency is low. This makes it possible to reduce the power consumption of important circuits in two-wire meters.
第1図は本発明の1実施例の構成を示すブロック図、第
2図はリセット信号発生回路の第2の実施例を示す回路
図、第3図はリセット信号発生回路の第2の実施例を示
す回路図、第4図は第3図に示す回路の動作を説明する
タイミング図、第5図は第3図に示す遅延回路の第2の
実施例を示す回路図、第6図はリセット信号発生回路の
第3の実施例を示す回路図、第7図は異常検知回路の他
の実施例を示す回路図、第8図は従来の2線式計器の構
成の概要を示す構成図、第9図は第8図に示す電源回路
の具体的な構成の1例を示すブロック図である。
10.16・・・2線式計器、11・・・負荷、12・
・・直流電源、13・・・スイッチングレギュレータ、
14・・・マイクロプロセッサ、17・・・安定化電源
回路、18・・・自己診断回路、19・・・信号処理回
路、20・・・リセット信号発生回路、21・・・異常
検知回路。FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of a reset signal generation circuit, and FIG. 3 is a second embodiment of the reset signal generation circuit. 4 is a timing diagram explaining the operation of the circuit shown in FIG. 3, FIG. 5 is a circuit diagram showing a second embodiment of the delay circuit shown in FIG. 3, and FIG. 6 is a reset circuit diagram. A circuit diagram showing a third embodiment of the signal generation circuit, FIG. 7 is a circuit diagram showing another embodiment of the abnormality detection circuit, and FIG. 8 is a configuration diagram showing an outline of the configuration of a conventional two-wire meter. FIG. 9 is a block diagram showing one example of a specific configuration of the power supply circuit shown in FIG. 8. 10.16...2-wire meter, 11...Load, 12.
...DC power supply, 13...Switching regulator,
14... Microprocessor, 17... Stabilized power supply circuit, 18... Self-diagnosis circuit, 19... Signal processing circuit, 20... Reset signal generation circuit, 21... Abnormality detection circuit.
Claims (1)
定すべき物理量を電気信号に変換しこれをマイクロプロ
セッサにより信号処理をして前記伝送線を介して前記負
荷に電流信号として伝送する2線式計器において、前記
伝送線の両端に発生する端子電圧のレベルを変換して第
1電圧を作るスイッチングレギュレータと、前記端子電
圧を安定化して第2電圧を作る安定化電源回路と、この
第2電圧によって動作し前記端子電圧の投入・停止・低
下と前記第1電圧の監視を実行して初期化信号と警報信
号とを出力する自己診断回路と、前記第1電圧によって
動作し前記初期化信号と前記警報信号により制御される
前記マイクロプロセッサを含む信号処理手段とを具備す
ることを特徴とする2線式計器。Power is supplied from the load side via a two-wire transmission line, and the physical quantity to be measured is converted into an electrical signal, which is processed by a microprocessor and transmitted as a current signal to the load via the transmission line. In a two-wire meter, a switching regulator converts the level of a terminal voltage generated at both ends of the transmission line to generate a first voltage, and a stabilizing power supply circuit stabilizes the terminal voltage to generate a second voltage. a self-diagnosis circuit that operates based on the second voltage and executes turning on, stopping, and lowering the terminal voltage and monitors the first voltage to output an initialization signal and an alarm signal; A two-wire meter comprising an initialization signal and a signal processing means including the microprocessor controlled by the alarm signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP915490A JP2753592B2 (en) | 1990-01-18 | 1990-01-18 | 2-wire instrument |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP915490A JP2753592B2 (en) | 1990-01-18 | 1990-01-18 | 2-wire instrument |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03212799A true JPH03212799A (en) | 1991-09-18 |
| JP2753592B2 JP2753592B2 (en) | 1998-05-20 |
Family
ID=11712703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP915490A Expired - Lifetime JP2753592B2 (en) | 1990-01-18 | 1990-01-18 | 2-wire instrument |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2753592B2 (en) |
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| Publication number | Publication date |
|---|---|
| JP2753592B2 (en) | 1998-05-20 |
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