JPH03212803A - Dc erasure circuit - Google Patents

Abstract

PURPOSE:To simplify constitution and to prevent an erasure rate from being lowered even when the output voltage of a power source is fluctuated by making a polarity inversion signal to flow to the coil of an erasure magnetic head by using one DC power source. CONSTITUTION:A recorded track is erased by connecting the coil 73 of the erasure magnetic head 71 to one DC power source 80 via plural switches and resistors and permitting a current whose direction is inverted alternately and whose magnitude is decreased gradually to flow on the coil 73 of the erasure magnetic head. In other words, the constitution can be simplified since one DC power source 80 is used, and also, the amplitude of the current decreasing gradually is changed accordingly even when the output voltage of the DC power source 80 is fluctuated, which generates no change of a ratio of amplitude. In such a way, a high erasure rate can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a recording device using a magnetic recording medium, in which a circuit for erasing recorded tracks, particularly a coil of an erasing magnetic head, is connected via a plurality of switches and resistors. This invention relates to a DC erasing circuit that, when connected to a DC power supply, causes a current to flow whose direction is alternately reversed and whose magnitude gradually decreases.

[Conventional technology]

For example, when recording and reproducing an NTSC color video signal or a color video signal output from a video camera or floppy disk camera, the signal is separated into a luminance signal and a color difference signal, and then FM modulated and recorded on a magnetic tape. The modulation signal is recorded on a recording medium such as a magnetic disk, and the modulated signal read from the recording medium is FM demodulated to reproduce the luminance signal and the color difference signal that appears line-sequentially.The color difference signal is converted into a color signal, and the luminance signal and I am trying to reproduce the color signal.

It is desirable that such a recording/reproducing apparatus using a floppy disk has a simple configuration and is inexpensive.

Therefore, it is desirable that the erasing circuit for erasing recorded tracks on a floppy disk has a simple configuration. Therefore, it has been proposed to use a DC cancellation circuit using a DC power supply.

FIG. 6 shows the configuration of an example of a conventional DC canceling circuit. One end of the coil 2 of the erasing magnetic head 1 is connected to the switch 3.
It is connected to the positive terminal of the first DC power supply 4 through the terminal, and the negative terminal of this first DC power supply is grounded. The output voltage of this DC power supply 4 is, for example, 5V. The other end of the coil 2 is connected to a switch 5 and a resistor 6 connected in series, and a switch 7 connected in series.
It is connected to the positive terminal of a second DC power supply 9 through a parallel circuit with a resistor 8 and a resistor 8, and the negative terminal of this second DC power supply is grounded. Further, the other end of the coil 2 is grounded through a parallel circuit including a switch 10 and a resistor 11 connected in series, and a switch I2 and a resistor 13 connected in series.

FIG. 7 shows the operation timing of the switches of the conventional DC erasing circuit shown in FIG. 6 and the current flowing through the coil of the erasing head. The switch 3 is kept on at all times during the erase operation period, and when the switch 5 is first turned on for a period of 2T, the voltage from the second DC power supply 9 passes through the resistor 6 and the switch 5 to the coil 2, and from the left to the right in FIG. A current flows through. Next, when the switch 5 is turned off and the switch 10 is turned on for a period T, the first DC power supply 4
A current flows from the coil 2 through the switch 10 and the resistor 11. That is, current flows through the coil 2 from right to left. Next, by turning off the switch IO and keeping the switch 7 on for a period T, a current flows from the second DC power supply 9 to the coil 2 from the left to the right via the resistor 8 and the switch 7. Further, by turning off the switch 7 and turning on the switch 12 for a period T, the coil 2,
Current flows through switch 12 and resistor 13. This current flows through the coil 2 from right to left.

In this way, switches 5.10. By sequentially turning on 7.12, a current whose direction is alternately reversed can be caused to flow through the coil 2 of the erasing head I. In this case, the output voltage value of the DC power supply 4.9 and the resistance 6.9 are adjusted such that the magnitude of the current flowing through the coil 2 gradually decreases. 8
．． 11. Set the resistance value of 13. Further, the period of time for reversing the polarity of the current flowing through the coil 2 needs to be short so that the polarity reversal is performed at a high frequency outside the frequency band of the recording signal, and can be set to, for example, 0.5 milliseconds.

[Problem to be solved by the invention]

The above-described conventional DC erasing circuit requires the first and second DC power supplies 4 and 9 as power sources, which has the disadvantage that the configuration is complicated. Generally, the output voltage of a power supply fluctuates due to temperature fluctuations, so the current flowing through the coil 2 of the erasing head l also fluctuates. When the current flowing through the coil 2 fluctuates in this way, the magnitude of the erasing magnetic field also fluctuates, making it impossible to obtain a sufficient erasing rate, which has the drawback of adversely affecting the signal that will be recorded on the same track next time. In particular, recording still images using the above-mentioned floppy disk has the disadvantage that the quality of reproduced images deteriorates. Further analysis of such erasing defects revealed that large erasing defects occur particularly when the ratio of the values of the currents flowing through the coil of the erasing head changes.

An object of the present invention is to eliminate the above-mentioned drawbacks, reduce the required number of DC power supplies to one, and enable erasure with a high erasure rate despite fluctuations in the output voltage of this DC power supply. The present invention attempts to provide a DC cancellation circuit.

[Means and effects for solving the problem] The DC erasing circuit of the present invention connects the coil of the erasing magnetic head to one DC power source through a plurality of switches and resistors, so that the coil of the erasing magnetic head has no direction. This is characterized in that the recorded track is erased by passing a current that is alternately inverted and whose magnitude gradually decreases.

According to such a DC erasing circuit according to the present invention, since one DC power supply is used, the configuration is simple, and even if the output voltage of the DC power supply fluctuates, the current gradually decreases. The amplitudes change correspondingly, so that a high erasure rate can be obtained since the ratio of the amplitudes does not change.

〔Example〕

FIG. 1 is a block diagram showing the overall configuration of an embodiment of a color video signal recording and reproducing apparatus to which a DC erasing circuit according to the present invention is applied. It uses a disk. In this example, three types of input terminal sections 12, 12 and 13 are provided so that various color video signals can be processed.◇The first input terminal section II has a so-called S The second input terminal section 12 is provided with a terminal for receiving a luminance signal and color signals of the three primary colors supplied from a VTR or other video signal source, and the third input terminal section 13 is provided with a terminal to receive an input. The NTSC
A terminal is provided to receive a composite color television signal according to the system. A color video signal supplied to one of the input terminals is selected by a manual switch provided in the input circuit 14, and from this selected video signal, a luminance signal Y and a color difference signal that appears line-sequentially, that is, an RY signal. and B-Y
Generate a signal. These luminance signals and color difference signals are supplied to the FM modulation circuit 15. The FM modulation circuit 15 frequency-modulates the luminance signal and the color difference signal and then supplies them to the mixer 16 . Here, the system controller 17
A DPSK modulation circuit (Differential Ph
control information signals obtained by modulation by the control information signals (shift keying) 18 are combined to generate a frequency multiplexed signal.

Information regarding this frame includes, for example, field recording or frame recording identification code, track number to be recorded, date information, and the like. The output signal of this mixer 16 is amplified to a predetermined level in a recording circuit 19 and subjected to predetermined processing, and then supplied to a magnetic head 21 via a recording/reproduction switch 20 controlled by a system controller 17. The information is recorded on a predetermined track of a magnetic recording medium, that is, a floppy disk 22. Immediately before this recording, the track is erased by an erasing magnetic head 71. This erasing pad 71 is connected to a DC erasing circuit 72 of the present invention. This DC erasing circuit 72 is driven and controlled by the system controller 17. As described above, in the mixer 16, the luminance signal Y and the color difference signal R
Since -Y or B-Y and the information signal are mixed, they are recorded on the same track in a frequency multiplexed relationship. Magnetic head 22 and erase head 71
A predetermined track of the floppy disk 22 is accessed by a head access mechanism 23 connected to the system controller 17. Further, the floppy disk 22 is rotationally driven at a speed of, for example, 3600 RPM by a spindle motor 25 that is drive-controlled by a spindle motor drive circuit 24 connected to the system controller 17. In this way, one frame of the video signal can be recorded on a predetermined track of the floppy disk 22. In this case, in field recording, one field of image signals is recorded on one track, and in frame recording, one frame of image signals is recorded using two tracks.

In the above explanation, it is assumed that the input color video signal is separated into the luminance signal Y and the color signal C, but in the NTSC composite color television signal supplied to the input terminal section 13, the luminance Since the signal and color signal are not separated, it is necessary to separate them. For this purpose, the input circuit 14 is provided with a Y/C separation circuit whose operation is controlled by the system controller 17.

For reproduction, the recording/reproduction changeover switch 20 is switched to the reproduction side P by the system controller 17 which responds to the user's operation on the operation unit 40. Further, the floppy disk 22 is rotationally driven by a spindle motor 25, and the magnetic head 21 is accessed to a predetermined track by a head access mechanism 23. a frequency multiplexed signal read by the magnetic head 21;
That is, the luminance signal Y, the color difference signal R-Y or B-Y that appears line-sequentially, and the control information signal, that is, DPSK data, are supplied to the reproduction circuit 41 via the switch 20. This reproducing circuit 41 is configured to digitally convert the envelope of the reproduced signal, supply the signal thus obtained to the system controller 17, and detect the presence or absence of recording. That is, if this envelope signal is not present, it can be determined that no signal is recorded on the track.

On the other hand, if an envelope exists, the reproduced signal is
The signal is supplied to the M demodulation circuit 42 and the DPSK demodulation circuit 43. In the FM demodulation circuit 42, the reproduced RF signal is demodulated to obtain a luminance signal Y and a RY signal or a B-Y signal, and these luminance signals and color difference signals are sent to input terminals 45 and 46 of an output signal processing circuit 44. supply to.

In the DPSK demodulation circuit 43, the frequency 1 in the reproduced RF signal is
D for a carrier of 3L+(f, horizontal scanning frequency)
The control information data subjected to PSK modulation is demodulated, and the demodulated control data signal is sent to the system controller 17.
supply to. This control data includes an identification code for field recording/frame recording, and the system controller 17 controls related circuits in accordance with this identification code. Regarding the recording and reproduction of control information data using the PSK modulation method, for example, Japanese Patent Laid-Open No. 62-2198
It is disclosed in Publication No. 53.

FIG. 2 shows the detailed configuration of the output signal processing circuit 44. The luminance signal Y supplied from the FM demodulation circuit 42 to the input terminal 45 of the output signal processing circuit 44 is sent to the A/D converter 5.
After converting the signal into a digital signal at 0, the signal is supplied to a signal compensation circuit 51 for luminance signal, and subjected to signal compensation such as dropout compensation and skew correction. The skew correction in this example is
When forming an image using a field image signal, in order to accommodate the fact that the starting point of screen scanning is alternately shifted by 1/2 horizontal scanning period (1/2H) in successive fields, the switching point between successive fields of the image signal is In response to this, processing is performed to give a delay of 1/2H to every other field.

The luminance signal subjected to signal compensation in this manner is stored in the field memory 53 via the data conversion circuit 52. The output of this field memory 53 is output from a normal/multi selector switch 54 that switches between a normal mode in which one frame is displayed on one screen and a multimode in which multiple frames are reduced and displayed on one screen. Supplies the side contacts. The output signal of the signal compensation circuit 5I is directly supplied to the normal side contact of this switch 54. The output signal of the normal/multi changeover switch 54 is supplied to the D/A converter 55 to generate an analog luminance signal Y, which is sent to the output terminal 5.
Output to 6.

On the other hand, the color difference signal, R-Y signal, or B-Y signal output from the input terminal 46 of the output signal processing circuit 44 is
After converting it into a digital signal in a converter 57, it is supplied to a signal compensation circuit 58 for color signals to perform dropout compensation,
After performing processing such as skew correction, the data conversion circuit 5
9 and stored in the field memory circuit 60. The color signal read from the field memory circuit 60 is supplied to the multi-side contact of the normal/multi changeover switch 61. The output signal of the signal compensation circuit 58 is directly supplied to the normal side contact of this switch 61. This switch 6
The color signal output from 1 is supplied to a color signal reproduction circuit 62, and the color signal C reproduced by this circuit is supplied to a D/A converter 63 and outputted to an output terminal 64 as an analog color signal.

The data conversion circuits 52 and 59 that process the luminance signal and color signal described above are connected to the system controller 1 which responds when the multi-screen function is selected on the operation unit 40.
According to the control signal from 7, the brightness signal and color signal are compressed so as to correspond to each screen section corresponding to the type of multi-screen, for example, 2×2 or 5×5.

FIG. 3 shows a detailed configuration of one embodiment of the DC cancellation circuit 72 according to the present invention. In this example, both ends of the coil 73 of the erasing head 71 are grounded via switches 74 and 75, respectively. A switch 76 and a resistor 77 are connected in series at the connection point between the coil 73 and the switch 75.
It is connected to the positive terminal of a DC power source 80 through a parallel circuit with a switch 78 and a resistor 79 connected in series. The negative terminal of this DC power supply 80 is grounded.

Further, the connection point between the coil 73 and the switch 74 is connected to the positive terminal of the DC power supply 80 through a parallel circuit including a switch 81 and a resistor 82 connected in series, and a switch 83 and a resistor 84 connected in series.

FIG. 4 shows the opening/closing timing of the switches 76, 7B, 81, 83, and FIG. 5 shows the current flowing through the coil 73 of the erasing head 71 at that time. First, the switch 74 is turned on for a period of 2T, and the switch 76 is turned on. At this time, current flows from the DC power supply 80 through the resistor 77, switch 76, coil 73, and switch 74. That is, the coil 73
Current will flow from left to right. Next, switches 74 and 76 are turned off, and switches 75 and 81 are turned on for period T. At this time, the resistor 82. Switch 81. Current flows through coil 73 and switch 75. That is, current flows through the coil 73 from right to left. Next, switch 75
and 81 are turned off, and switches 74 and 7 are turned off.
8 is turned on for a period T. As a result, the DC power supply 80 is connected to the resistor 79, the switch 78 . Current flows through coil 73 and switch 74. At this time, current flows through the coil 73 from left to right. Next, switch 74
and 78 are turned off, and switches 75 and 83 are turned on for a period T. This allows the DC power source 80 to be connected to the resistor 84° switch 83. Coil 73 and switch 75
Current flows through the That is, current flows through the coil 73 from right to left. In this way, a current whose direction is alternately reversed can be passed through the coil 73 of the erasing head 71 as shown in FIG. In this case, the resistors 77 and 79 are set such that the amplitude of the current flowing through the coil 73 gradually decreases.
．． Select values 82 and 84. In the present invention, since only one DC power supply 80 is used as described above,
Configuration becomes easy. Furthermore, even when the output voltage of the DC power supply changes, the amplitude of the current flowing through the coil 73 changes at the same rate, so the ratio thereof does not change. therefore,
Even if the output voltage of the DC power supply fluctuates, the erasing rate does not decrease, and erasing can always be performed in an optimal state.

As shown in FIG. 1, the reproduced color signal C output from the output signal processing circuit 44 is supplied to a color signal output terminal 86 via a switch 85. Further, the reproduced luminance signal Y output from the output signal processing circuit 44 is supplied to a mixer 87, where it is superimposed with a character signal supplied from a character generator 88 controlled by the system controller 17, and a luminance signal output terminal 89 supply to. The switch 85 is controlled by a character generator 88 so that the color signal is suppressed during the period in which the character signal is superimposed on the luminance signal. That is, during this period, a predetermined potential of the DC power supply 90 is supplied to the color signal output terminal 86. In this way, the output terminals 86 and 89 are provided with a color signal C and a luminance signal Y1 or S which are separated from each other.
In order to obtain an NTSC composite color television signal, the luminance signal and the color signal are supplied to a mixer 91 and combined, and the composite color television signal is output to an output terminal 92. Configure. In this way, the signals outputted to the output terminals 86, 89 and 92 can be supplied to a television monitor to reproduce a color image, or can be supplied to a color printer to create a color print.

The present invention is not limited to the embodiments described above, but can be modified and modified in many ways. For example, in the above-described embodiment, the present invention is applied to a recording/reproducing device using a floppy disk, but the present invention can also be applied to other types of recording devices. Furthermore, the specific circuit configuration is not limited to the one shown in Fig. 3; it is possible to use a single DC power source to flow a current whose polarity is alternately reversed through the coil of the erasing head. Any configuration is fine as long as there is one. Further, in the above-described embodiment, the polarity of the current flowing through the coil of the erasing head is reversed four times, but the number of times is not limited to four and can be arbitrarily determined.

[Effects of the Invention] In the DC erasing circuit of the present invention described above, a single DC power supply is used to send a polarity reversal signal to the coil of the erasing magnetic head, so the configuration is simple, inexpensive, and the power supply is reduced. Even when the output voltage fluctuates, the amplitude ratio of the current does not change, so the erasing rate does not decrease, and signals can be well recorded on the erased tracks.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a recording/reproducing device equipped with a DC erasing circuit according to the present invention, and FIG. 2 is a circuit diagram showing the detailed configuration of the output signal processing circuit shown in FIG. FIG. 3 is a circuit diagram showing the detailed configuration of the DC erasing circuit of the present invention shown in FIG. 1, FIG. 4 is a timing diagram showing the opening and closing timing of the switch, and FIG. FIG. 6 is a circuit diagram showing the configuration of a conventional DC erasing circuit. FIG. 7 is a diagram showing the opening/closing timing of a switch and the current flowing through a coil to explain its operation. 14... Input circuit 15... FM modulation circuit 1
7... System controller 19... Recording circuit 20... Recording/playback changeover switch 21... Recording/playback magnetic head 22... Floppy disk 23... Head access mechanism 24... Motor drive circuit 25 ...Motor 41...
・Reproduction circuit 42...FM demodulation circuit 44...
Output signal processing circuit 71... Erasing magnetic head 72... DC erasing circuit 7
3...Coil 74, 75.78.78.81.83...Switch 7
7, 79.82.84...Resistor 80...DC power supply 86...Color signal output terminal 89...Brightness signal output terminal 92...NTSC signal output terminal Fig. 4 Fig. 5 Fig. 7

Claims (1)

[Claims] 1. The coil of the erasing magnetic head is connected to one DC power supply through multiple switches and resistors, and a current whose direction is alternately reversed and whose magnitude gradually decreases is passed through the coil of the erasing magnetic head to record. A direct current erasing circuit characterized in that it is configured to erase a track that has already been erased.