JPH03212888A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device for a computer, and more particularly to a semiconductor memory device that reads and writes data according to specified rules.

[Conventional technology]

In conventional semiconductor storage devices (memory), the memory for reading and writing data is RAM (-) random access memory.
ROM (read-only memory), which is a read-only memory for data;
As described in Publication No. 7, a memory capable of reading and writing data at the same time was a DAIR φ boat memory.0 [Problem to be solved by the invention] When reading and writing data, for example, when reading and writing are performed alternately, this has been achieved through software control, so no consideration has been given to hardware protection of data that is regularly read and written. The main object of the present invention is to provide a semiconductor memory device that continuously writes data according to the regular reading and writing rules. The purpose of this is to realize data protection using hardware.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a semiconductor memory device with an M, an output/write rule control section, and a read/write switch.In addition, for error detection by data protection,
A port provided with an interrupt line is also provided with a mode switch for registering read/write rules. [Function] In the semiconductor memory device R (memory), the read/write rule control unit controls reading and writing of data in the data storage unit. control the rules of For example, read and write are alternated, and after reading five times, writing is performed twice. This can be combed back.

In addition, in order to register such a rule, a mode line is provided, the access of the data bus of the read/write rule control unit and the data storage unit is switched at the same address, and the above order rules etc. are applied to the continuous write rule control unit. register.

Furthermore, if there is a read or write of data that violates these rules, an interrupt line is provided to notify that an error has occurred.Thus, the read or write of data to the semiconductor memory device is registered. It operates according to the rules, and if the rules are violated, an interrupt is sent to notify that a sheller has occurred, so data can be protected by hardware and the data will not be destroyed. An embodiment will be explained with reference to the drawings. Fig. 2 shows an embodiment of a combinator system using a semiconductor storage device (memory) that regularly performs reading and writing according to the present invention. 1 is a semiconductor memory device according to the present invention that regularly performs reading and writing, and 2 is a RAM.

3 is ROM, 4 is MPU (micro processor),
5 is CRT (cathode ray chip), 6 is KB
(key board), 7 is DISK, 8 is serial, 9 is system bus, and 10 is local bus.

In the figure, MPUI is ROM1. Using RAM1, CRT5. to B6. Controls DISK7 and MPU2
is ROM2. 0 to control serial 8 using RAM2
Here, the MPUI side is called the system, and the MPU2@ is called the serial. When the semiconductor memory device of the present invention that regularly performs reading and writing is replaced with a conventional RAM, the RAM1 on the system side
The control and data flow when transmitting data using serial 8 are shown in the same figure, as well as in Figures 3 and 4.
The process will be described below using the flowchart shown in the figure.

MPU 1 writes the data in RAM 1 to RAM 1 according to chart 70 in Figure 3 (21), and then checks whether RAM 1 can be occupied (22). Check the flag (25)
If it is a write-flag, data is written to RAM 1 (24).

Then, read/write fist 7 lag is set to read/write 7 lag, and 25) the occupation of RAM 1 is released (26).

Also, when RAM 1 cannot be occupied, wait processing (2t
After 3), perform the occupancy process (22) again.
c% Light - When it stops at 7 lag, it is already 1 RAM
(22), so we want to release it. 29) After the waiting process (50), we start again from the occupancy process (22). On the other hand, MPU 2 transfers the data in RAM 1 to 1 according to the flowchart in Figure 4. Read data from the RAM (31). Check whether RAM 1 can be occupied (52) If it can be occupied, check the primary read/write flag (53) If it is a read flag, RAM 1
Read data from (34). Then, the read/write flag is set as the write flag, and the RA of (55) 1 is set as the write flag.
M's exclusive possession is released (36). Also, when 10RAIJ cannot be occupied, unlike MPtJl, MPU2 is serial-only, so the occupancy process is performed again without waiting processing (32).
Do this. Further, if it is not a read flag, it already occupies one RAM (32), so it is released, and since the MPU 2 is dedicated to serial, it starts again from the occupancy process (32) without waiting.

An embodiment of a semiconductor memory device 1 that regularly performs reading and writing according to the present invention will be described with reference to FIG.

In the figure, 1 is a semiconductor memory device, 10 is a read/write switch that alternately performs reading/writing, and 1
1 is a conventional RAM, 12 is an address bus on the system side,
13 is an address bus on the serial side, 14 is a data bus for writing on the system side, 15 is a data bus for reading on the serial side, 16 is an exception interrupt line for writing on the system side, and 17 is an exception interrupt line for reading on the serial side. ,
Reference numeral 18 indicates a write line on the system side, and reference numeral 19 indicates a lead line on the serial side. In this semiconductor memory device R1, reading and writing are performed alternately by the read/write changeover switch 10. Now, the first
In the state shown in the figure, writing on the system side is permitted, and an exception interrupt is generated for reading on the serial side. Finally, if the system side sends a write signal to the write line 18, sends an address to the address bus 12, and sends data to the data bus, data is written to the RAM 1t. Conversely, the read signal is sent from the serial side to the read line 18. 19, the signal outputs an interrupt signal to the read exception interrupt R17.

Furthermore, when the connection of the switch 10 is changed, the read/write relationship is reversed.

Note that since the system side and the serial side have separate MPUs, they can operate asynchronously.

Therefore, when this semiconductor storage device 1 is placed at 1 in FIG. 2, the control and data flow when transmitting data in RAlj on the system side using the serial 8 are shown in the same figure and in FIG. 5. , will be described below using the 70-chart of FIG.

The MPU 1 writes the data in the RAMI to the semiconductor memory device 1 according to the flowchart in FIG. 5 (40) O
')t! t. As explained above, the semiconductor memory device 1 has a function to perform reading and writing alternately and a function to generate an exception interrupt when this is violated, so that sudden υ
, write (41) and end (42). At this time, if the semiconductor memory device 1 is in a state where writing is possible as shown in FIG. 1, the write operation is performed and the process ends; however, if the semiconductor memory device 1 is in a state where reading is possible, a write exception interrupt occurs.

The interrupt processing for this exceptional interrupt is as shown in FIG. 5, where the p(43)%ab address is used as the handler (46) and the process returns (45). The handler was in that state! Depending on F14, scheduler (47), end (48), or
One of the writes to the semiconductor storage device 1 is executed again.

On the other hand, data in the MPU2d semiconductor memory device 1 is transferred to the sixth
Data is read from the semiconductor memory device 1 according to the chart 70 in the figure (51). Similar to MPU1, this process begins with a read (52) and ends (53). At this time, if the semiconductor memory device 1 is not like the one shown in FIG. 1 and is in a state where reading is possible, the read operation is performed and the process ends; however, at this time, if it is in a state where writing is possible, a read exception interrupt occurs. Then, control is transferred to interrupt processing (54). In this interrupt processing, the returned address is returned to the semiconductor memory device 1.
(55) and return (56).

The reason for this is that %MPU2 is serial-only.

FIG. 5 shows a case where the semiconductor memory device 1 of the present invention shown in FIG. 1 is used instead of the conventional method shown in FIGS. 5 and 4.

The method shown in FIG. 6 has less software overhead and is faster.

Furthermore, the semiconductor memory device 1 is not limited to the embodiment shown in FIG. 1, but may also include embodiments shown in FIGS. 7 and 8.

First, FIG. 7 shows a semiconductor memory device 1 in which writing is performed alternately in the case of a single MPtl.

In the figure, 61 is an address bus, 62 is a data bus, 63 is a RAM, 64 is a write line, 65 is a read line, and 6
6 is an OR circuit, 67 is an interrupt line, and 68 is a read/write switch for alternately performing read/write.

Now, when a signal is sent to the write line, the switch 68 is connected, so data is written to the RAM 65. Conversely, when a signal is sent to the lead wire, the switch is turned off, so data cannot be continuously output from the RAM 65, and a signal is sent through the OR circuit 66 to the interrupt line 67. The semiconductor memory device 1 alternately performs the following operations.

Next, the embodiment shown in FIG. 8 will be described.

In the figure, 70 is a data storage section, 71 is a read/write rule control section, 72 is an address bus, 73 is a data bus, 74 is a read permission line, 75 is a write permission line, 76 is a write line, 77 is a read line, Reference numeral 78 indicates an interrupt line, and reference numeral 79 indicates a mode line. This semiconductor memory device registers an arbitrary write-in rule and performs reading and writing in accordance with this rule. If this rule is violated, an interrupt will be generated.

Then, to register an arbitrary continuous write rule, when the mode signal is set to the registered state and a write signal is issued, the address bus 72,
Data bus 73 accesses read/write rule control section 71 . Then, when data necessary for registration is written, the mode signal is set to the read/write state, and the address bus 72 and data bus 73 access the data storage section 70. When a read or write signal is sent, the output write rule control unit determines whether or not to accept the read or write. Also, write permission 75 is sent in response to the write signal. After that, the data record section y
Based on the value of the address bus 72, the data of o is successively written using the data bus 73.

As described above, a semiconductor memory device 1 capable of implementing arbitrary read/write rules is realized.

Furthermore, it is easily possible to form the semiconductor memory device 1 shown in FIGS. 1, 7, and 8 into a chip. [Effects of the Invention] The present invention is composed of nine parts as described above, so the following will be explained below. It produces the effects described in . That is, lead/
By providing a write changeover switch, the semiconductor storage device (memory) can read and write regularly. Also, by providing a read/write rule control section, the semiconductor storage device (memory) can perform reading and writing regularly. Reading and writing can be carried out regularly. - By providing an interrupt line, errors in erroneous access to data can be detected.

Further, by providing a mode line, reading and writing rules can be registered.

Furthermore, by using the semiconductor storage device (memory) of the present invention, it is possible to reduce the scale of software development and improve performance.

Furthermore, by using the semiconductor storage device (memory) of the present invention, data can be protected by hardware.

[Brief explanation of drawings]

1, 7, and 8 are explanatory diagrams of a semiconductor memory device in which reading and writing are performed regularly according to a 15A embodiment of the present invention, and FIG.
The figure is a block diagram of a computer system using Figure 1, Figures 3 and 4 are flowcharts of a control method when using conventional RAM, and Figures 5 and 6 are based on Figure 1. It is a 20-chart of the control method when. 1... Semiconductor storage device (memory), 11... RAM
. 12.15 Address bus, 14.15 Data bus, 16 Write interrupt line.

Claims (1)

[Scope of Claims] 1. In a semiconductor memory device that performs reading and writing, a mechanism for registering arbitrary reading and writing rules, a reading and writing control unit that controls reading and writing using the registered rules, and a reading and writing that violates the rules. A semiconductor memory device characterized by providing an interrupt for detecting an error in writing.