JPH03212889A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a first-in, first-out (hereinafter abbreviated as FIFO) type semiconductor memory device.

2. Description of the Related Art In recent years, with the advancement of semiconductor process technology, semiconductor memory devices have been used to a remarkable degree. In particular, FIFO type semiconductor memory devices have attracted attention in the field of video, and Y/Cefi circuits for digital signal processing have attracted attention (
It has become a must-have.

A conventional semiconductor memory device will be explained below.

FIG. 3 shows an example of a conventional semiconductor memory device.

FIFO type semiconductor memory devices used in the video field are I
It is often used in H delay lines, etc. (This conventional example is an example of a case with a storage capacity of 2H for performing arithmetic processing in the vertical direction of one screen, and is a circuit for only 1 bit. Figure 31
．． 32 is an I configured with a FIFO type semiconductor memory device.
H delay circuit, 33 is a dynamic link type unit storage circuit composed of three transistors, 34 is a write address signal line, 35 is a read address signal line, 36 is an address control circuit, 37 is a write data signal line, 38 are read data signal lines, and three are arithmetic circuits.

The operation of the semiconductor memory device configured as described above will be described below.

The input data is written into the unit storage circuit specified by the write address signal line 34. Further, data is selected and output from the unit storage circuit of the column specified by the read address signal line 35. The unit memory circuit 33 composed of three transistors is composed of N-ch transistors, and the write address signal line 34 or the read address signal line 35 is high (“H”).
) level, respectively, the write data signal line 37
Data is written from or transferred to the read data signal line 8.

Delay circuits 31 and 32 are unit storage circuits 33 for IH lines.
It further has an arithmetic circuit 39 for calculating data delayed by each delay circuit 31 and 32, and performs signal processing in the vertical direction of the screen by calculating data for three lines of the screen. It is.

Problems to be Solved by the Invention However, in the above-mentioned conventional techniques, input data and
When designing a monolithic semiconductor integrated circuit in order to input the output of each IH delay circuit to an arithmetic circuit, each IH delay line occupies a large area in the design, so the input data to the arithmetic circuit and the output of each delay line are When wiring for inputting data is provided, the area of the wiring becomes large, which poses a problem in that the design efficiency of the semiconductor integrated circuit is reduced.

The present invention solves the above-mentioned conventional problems, and consists of a delay circuit using a FIFO type storage circuit with a storage capacity of two rows of data in two stages per bit, upper and lower stages, and a write data signal line. And by providing a read data selection circuit that can output the data of the read data signal line,
It is an object of the present invention to provide a semiconductor memory circuit in which the wiring area of signal lines for inputting to an arithmetic circuit can be almost eliminated.

Means for Solving the Problems In order to achieve this object, the semiconductor memory circuit of the present invention has the following features:
A plurality of unit memory circuits are arranged on one address signal line,
Further, two rows of unit memory circuits are prepared for one bit, and each row of the unit memory circuits has an output data selection circuit so that data on the write data signal line and the read data signal line can be taken out. .

Function: With this configuration, it is possible to extract data with multiple delay amounts from one delay circuit, and the design of the arithmetic circuit is easy.
The design area of the row delay line circuit can be reduced.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory device in one embodiment of the present invention. In FIG. 1, 1 is a unit storage circuit;
2 is an address control circuit, 3 is an input data selection circuit, 4 is an output data selection circuit, 5 is a write address signal line, 6
7 is a read address signal line, 7 is a write data selection circuit, and 8 is an arithmetic circuit.

The operation of this embodiment having the above configuration will be explained below. The signal processing circuit of this embodiment is an example in which only one bit of a signal processing circuit in the vertical direction of the screen using a delay circuit that performs FIFO operation is used in the video field.

The write address signal line 5 and the read address signal line 6 are alternately set to "H" at a constant cycle, and the input data is input for 18 minutes per row, and the total number of unit storage circuits (28
This circuit is used to obtain delayed output data (minutes).

When writing data, one of the switches in the input data selection circuit 3 is turned on, the write data selection circuit is turned off, and the write data signal line (10
Input data is transferred to the unit memory circuit a or 10b), and the data is written into one of the unit memory circuits by the write address signal line 5. At that time, the switch of the write data selection circuit 7 to which input data is not connected (the switch of the input data selection circuit 3 is turned off) is turned on, and the unit storage device of that row is connected to the read data. It will be written to itself again, and a refresh operation will be performed.

When reading data, data is transferred from the unit storage device 1 designated by the read address signal line 6 to the read data signal I (9a or 9b).

As described above, the write data and read data of each row of the unit storage circuit are input to the output data selection circuit, and as outputs, the currently written data, the data delayed by 2H (data 2H ago), and IH delayed data (data before IH) can be obtained.

Table 1 shows the two switches 3a of the input data selection circuit 3.
and 3b on/off and each write data signal line and read data signal line (9a).

9b, 10a, 10b) are shown.

OH: Current input data IH: IH delayed data 2H: 2H delayed data Table 1 As described above, according to this embodiment, three outputs are simultaneously obtained from the delay circuit having a 2H unit memory circuit. Therefore, it can be connected to subsequent arithmetic circuits without considering the wiring area.

Furthermore, in FIG. 2, the output of the output data selection circuit 14 is 1.
Here is an example. The configuration is the same as that of the embodiment shown in FIG. 1 except for the number of outputs of the output data selection circuit 14 and the number of inputs of the arithmetic circuit 18. Naturally, the current input data and tH
, 2H delayed signals can be obtained as serial data.

In addition, although this embodiment shows an example in which 1-bit data is configured with two rows of unit memory circuits, the effect of the invention is the same even if the unit storage circuit is configured with three or more rows depending on the amount of delay required. It is.

Effects of the Invention The present invention arranges a plurality of unit memory circuits on one address signal line, further prepares two unit memory circuit rows for one bit, and writes write data signals for each unit memory circuit row. By providing an output data selection circuit that can take out data from the line and read data signal line, it is possible to take out data with multiple delay amounts from one delay circuit, and the wiring to the arithmetic circuit can be saved. The effect can be obtained with little consideration of design area.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device in one embodiment of the present invention, FIG. 2 is a block diagram of another embodiment, and FIG. 3 is a block diagram of a conventional semiconductor memory device. 1...Unit storage circuit, 2...Address control circuit, 3...Input data selection circuit, 4...
...Output data selection circuit, 5...Write address signal line, 6...Read address signal line, 7...Write data selection circuit, 8...
...Arithmetic circuit, 9a, 9b...Read data signal line, 10a, 10b...Write data signal line.

Claims (1)

[Claims] a memory circuit group in which unit memory circuits capable of writing and reading data are arranged in a matrix; a plurality of address signal lines that control writing and reading of data to and from the memory circuit group for each column; an address control circuit that outputs a plurality of address signal lines, a write data signal line for writing data to the memory circuit group for each row, and a read data signal line for reading data;
Furthermore, an input data selection circuit that selects distribution of input data to each row of the memory circuit group, and an output signal line of the input data selection circuit and a read data signal line of each row are input, A semiconductor characterized in that it has a write data selection circuit that outputs the data to a write data signal line, and an output data selection circuit that can arbitrarily select data on the write data signal line and data on the read data signal line of each row. Storage device.