JPH03212901A - Square board type chip resistor - Google Patents
Square board type chip resistorInfo
- Publication number
- JPH03212901A JPH03212901A JP2008628A JP862890A JPH03212901A JP H03212901 A JPH03212901 A JP H03212901A JP 2008628 A JP2008628 A JP 2008628A JP 862890 A JP862890 A JP 862890A JP H03212901 A JPH03212901 A JP H03212901A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- glass
- softening point
- glass layer
- linear expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、主に自動実装機により高密度配線回路(ハイ
ブリッドIC等)に装備される角板型チップ抵抗器に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a square plate type chip resistor that is mainly mounted on a high-density wiring circuit (hybrid IC, etc.) by an automatic mounting machine.
従来の技術
近年、電子機器の軽薄短小化に対する要求がますます増
大していく中、回路基板の配線密度を高めるため、抵抗
素子には非常に小型な角板型チップ抵抗器が多く用いら
れるようになってきた。Conventional technology In recent years, as the demand for lighter, thinner, and smaller electronic devices continues to increase, very small square plate-type chip resistors are increasingly being used as resistance elements in order to increase the wiring density of circuit boards. It has become.
また、この角板型チップ抵抗器は高速度でプリント基板
に実装するために、自動実装機により実装されることが
ほとんどである。このため、角板型チップ抵抗器の実装
品質を高める要望が強くなってきている。Moreover, in order to mount this square plate type chip resistor on a printed circuit board at high speed, it is almost always mounted using an automatic mounting machine. For this reason, there is an increasing demand for improving the mounting quality of square plate type chip resistors.
従来の角板型チップ抵抗器の構造を第2図に示す。The structure of a conventional square plate type chip resistor is shown in FIG.
従来の高電力型の角板型チップ抵抗器は、96アルミナ
基板11と、銀系厚膜電極による上面電極層12と端面
電極層13、ルテニウム系厚膜抵抗による抵抗層14と
、抵抗層14を覆うホウ珪酸鉛系ガラスによる第1ガラ
ス層15と捺印ガラス層16と第2ガラス層17から構
成されている。なお、露出電極面には半田材は性を向上
させるために、Niメツキ層18と5n−Pbメツキ層
19を電解メツキにより施している。A conventional high-power square plate type chip resistor includes a 96 alumina substrate 11, a top electrode layer 12 and an end electrode layer 13 made of a silver-based thick film electrode, a resistance layer 14 made of a ruthenium-based thick film resistor, and a resistance layer 14 made of a ruthenium-based thick film resistor. It is composed of a first glass layer 15 made of lead borosilicate glass, a stamping glass layer 16, and a second glass layer 17 that cover the glass. Incidentally, in order to improve the properties of the solder material, a Ni plating layer 18 and a 5n-Pb plating layer 19 are applied to the exposed electrode surface by electrolytic plating.
発明が解決しようとする課題
しかし、従来の角板型チップ抵抗器の抵抗体の、保護層
は信頼性を確保するため、3層のガラス構造をとってお
り、第1ガラス層・捺印ガラス層・第2ガラス層から構
成されている。このガラスはガラス軟化点が590℃〜
610℃で線膨張係数が64X10−7〜66 X 1
0−7/’Cであり、これを580℃〜600℃の温度
で焼成することにより形成している。この場合、ガラス
表面には、捺印ガラス層の盛り上がり部分が残り、約2
0〜30μの凹凸が発生してしまう。Problems to be Solved by the Invention However, in order to ensure reliability, the protective layer of the resistor of the conventional square plate chip resistor has a three-layer glass structure. - Consists of a second glass layer. This glass has a glass softening point of 590℃~
Linear expansion coefficient at 610℃ is 64X10-7 to 66X1
0-7/'C, and is formed by firing at a temperature of 580°C to 600°C. In this case, a raised part of the stamped glass layer remains on the glass surface, about 2
Unevenness of 0 to 30 μm will occur.
これは、ガラス軟化点付近で保護ガラスを焼成するため
、ガラスが十分に溶融せず、捺印ガラス層の盛り上がり
が残るためと考えられる。This is thought to be because the protective glass is fired near the glass softening point, so the glass is not sufficiently melted and a bulge of the stamped glass layer remains.
この表面に凹凸がある角板型チップ抵抗器を自動実装機
でプリント基板等に実装しようとする場合、自動実装機
の吸着ピンで角板型チップ抵抗器を吸い上げたときに、
ガラス表面の凹凸のために吸着ビンと角板型チップ抵抗
器が点接触しているような形となり、角板型チップ抵抗
器が回転してしまうことが多く、第3図に示すように斜
めに実装され、正確にプリント基板に実装できないとい
った課題があった。なお、20はプリント基板、21は
導体部、22は角板型チップ抵抗器である。When trying to mount a square plate type chip resistor with an uneven surface on a printed circuit board etc. using an automatic mounting machine, when the square plate type chip resistor is picked up with the suction pin of the automatic mounting machine,
Due to the unevenness of the glass surface, the suction bottle and the square plate chip resistor often come into point contact, causing the square plate chip resistor to rotate, causing the square plate chip resistor to rotate diagonally as shown in Figure 3. The problem was that it could not be mounted accurately on a printed circuit board. In addition, 20 is a printed circuit board, 21 is a conductor part, and 22 is a square plate type chip resistor.
この課題を解決するための対策として従来、■ガラスの
焼成温度を640℃以上の高温で焼成し、保護ガラスを
十分に溶融させ、表面の凹凸を小さくする、■保護ガラ
スの軟化点を550℃程度に下げることにより、従来の
焼成温度により十分にガラスを溶融させ、表面の凹凸を
小さくする、等の検討が考えられた。しかし、■のよう
に焼成温度を上げると、抵抗値のばらつきが大きくなり
、■のようにガラスの軟化点を下げると線膨張係数が大
きくなるとともに、ガラスの耐酸性も劣化する。このた
め、ガラスとアルミナ基板との熱膨張係数の差によるガ
ラス内部の応力が残りやすく、更に耐酸性が劣化してい
るので、露出電極面に電気めっきを施すときにガラス表
面が酸に侵食され、内部応力が発散しようとして、ガラ
ス表面にクラックが発生するといった課題があった。Conventional measures to solve this problem include: (1) firing the glass at a high temperature of 640°C or higher to sufficiently melt the protective glass and reducing surface irregularities; (2) raising the softening point of the protective glass to 550°C. Consideration has been given to lowering the firing temperature to a certain degree, thereby sufficiently melting the glass at the conventional firing temperature and reducing surface irregularities. However, when the firing temperature is raised as shown in (2), the variation in resistance increases, and when the softening point of the glass is lowered as shown in (2), the linear expansion coefficient increases and the acid resistance of the glass also deteriorates. For this reason, stress tends to remain inside the glass due to the difference in thermal expansion coefficient between the glass and the alumina substrate, and the acid resistance deteriorates, so when electroplating is applied to the exposed electrode surface, the glass surface is easily attacked by acid. However, there was a problem in that internal stress tried to dissipate, causing cracks to occur on the glass surface.
本発明は、このような課題を一挙に解決するもので、抵
抗値ばらつきを大きくすることなく、ガラスの耐酸性も
劣化させず、更にガラスの表面の凹凸を小さくし高実装
精度を実現した角板型チップ抵抗器を提供するものであ
る。The present invention solves these problems all at once, and is a corner that does not increase the variation in resistance value, does not deteriorate the acid resistance of the glass, and further reduces the unevenness of the glass surface and achieves high mounting accuracy. The present invention provides a plate-type chip resistor.
課題を解決するための手段
本発明の角板型チップ抵抗器は、絶縁性のセラミック基
板と、前記セラミック基板上に形成される銀系厚膜の上
面電極層と、前記上面電極層の一部に重なるルテニウム
系厚膜の抵抗層と、前記抵抗層を完全に覆う軟化点が5
50℃〜570℃でかつ線膨張係数が69X10−7〜
75X10−7層℃の第1ガラス層と、前記第1ガラス
層上に形成される軟化点が550℃〜570℃でかつ線
膨張係数が68X10−7〜74 X 10−7層℃の
捺印ガラス層と、前記第1ガラス層上で前記捺印ガラス
層を完全に覆うように形成される軟化点が580℃〜6
30℃でかつ線膨張係数が62x10−7〜68 X
10−7層℃の第2ガラス層と、前記上面電極層の一部
に重なる銀系厚膜の端面電極層とより構成されている。Means for Solving the Problems The square plate type chip resistor of the present invention includes an insulating ceramic substrate, a top electrode layer made of a thick silver film formed on the ceramic substrate, and a part of the top electrode layer. A thick ruthenium-based resistance layer overlapping the resistance layer and a softening point of 5 that completely covers the resistance layer.
50℃~570℃ and linear expansion coefficient 69X10-7~
A first glass layer having a temperature of 75X10-7 layers and a sealing glass formed on the first glass layer having a softening point of 550C to 570C and a coefficient of linear expansion of 68X10-7 to 74X10-7C. layer formed on the first glass layer to completely cover the imprinting glass layer has a softening point of 580°C to 6.
At 30℃ and linear expansion coefficient of 62x10-7 to 68X
It is composed of a second glass layer having a temperature of 10-7 degrees Celsius, and an end electrode layer made of a silver-based thick film and partially overlapping the upper electrode layer.
作用
この構成にによると、第1ガラス層のガラス軟化点が焼
成温度(590℃)に比べ低いので、捺印ガラスが第1
ガラス層に沈み込み、表面の凹凸を小さくできると共に
、第2ガラス層の耐酸性は劣化していないので、電気メ
ツキの時ガラスが侵食されず、ガラス表面にクラックは
発生しない。Function According to this configuration, since the glass softening point of the first glass layer is lower than the firing temperature (590°C), the marking glass is
It sinks into the glass layer and can reduce surface irregularities, and the acid resistance of the second glass layer is not deteriorated, so the glass is not eroded during electroplating and no cracks are generated on the glass surface.
また、第2ガラス層の線膨張係数が最も小さいので、内
部応力は第2ガラス層を圧縮する方向に発生し、クラッ
クは更に発生しにくい。Furthermore, since the second glass layer has the smallest coefficient of linear expansion, internal stress is generated in a direction that compresses the second glass layer, making cracks less likely to occur.
これにより、抵抗値ばらつきを大きくすることなく、ガ
ラスの耐酸性も劣化させず、更にガラスの表面の凹凸を
小さくし高精度実装を可能にした角板型チップ抵抗器を
提供することができる。As a result, it is possible to provide a square plate type chip resistor that does not increase the variation in resistance value, does not deteriorate the acid resistance of the glass, and further reduces the unevenness of the glass surface and enables high-precision mounting.
実施例
以下、本発明の実施例について、第1図を用いて説明す
る。EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.
第1図は本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
第1図において、本発明の角板型チップ抵抗器は、96
アルミナ基板1と、銀系厚膜電極による上面電極層2と
端面電極層3、ルテニウム系厚膜抵抗による抵抗層4と
、抵抗層4を覆うホウ珪酸鉛系ガラスによる第1ガラス
層5と捺印ガラス層6と第2ガラス層7からなっている
。なお、露出電極面には半田付は性を向上させるために
、Niメツキ層8と5n−Pbメツキ層9を電解メツキ
により施している。In FIG. 1, the square plate type chip resistor of the present invention has 96
An alumina substrate 1, a top electrode layer 2 and an end electrode layer 3 made of silver-based thick film electrodes, a resistance layer 4 made of a ruthenium-based thick film resistor, and a first glass layer 5 made of lead borosilicate glass covering the resistance layer 4 are stamped. It consists of a glass layer 6 and a second glass layer 7. In order to improve solderability, a Ni plating layer 8 and a 5n-Pb plating layer 9 are applied to the exposed electrode surface by electrolytic plating.
第2図を用いて、本発明の実施例の詳細について説明す
る。まず、耐熱性及び絶縁性に優れた大版の96アルミ
ナ基板を受は入れる。このアルミナ基板には短冊状、お
よび個片状に分割するために、分割のための溝(グリー
ンシート時に金型成形)が形成されている。次に、前記
96アルミナ基板上に厚膜銀ペーストをスクリーン印刷
し、ベルト式連続焼成炉によって850℃の温度で、ピ
ーク時間6分、lN−0UT 45分のプロファイル
によって焼成し上面電極層2を形成する。次に、上面電
極層2の一部に重なるように、RuO2を主成分とする
厚膜抵抗ペーストをスクリーン印刷し、ベルト式連続焼
成炉により850℃の温度でピーク時間6分、lN−0
UT時間45分のプロファイルによって焼成し、抵抗層
4を形成する。次に、前記上面電極層2間の前記抵抗層
4の抵抗値を揃えるために、レーザー光によって、前記
抵抗体層4の一部を破壊し抵抗値修正を行う。更に、前
記抵抗層4を完全に覆うように、ガラス軟化点が560
±5℃で焼成後の線膨張係数が72±2X10−7の第
1ガラスペーストをスクリーン印刷し、近赤外線乾燥炉
によって150℃で10分乾燥する。さらに、乾燥済み
の第1ガラスペーストの上に、ガラス軟化点が560±
5℃で焼成後の線膨張係数が71±2X10−7の捺印
ガラスペーストをスクリーン印刷し、近赤外線乾燥炉に
よって110℃で10分乾燥する。さらに、乾燥済みの
第1ガラスペーストの上で乾燥済み捺印ガラスペースト
を完全に覆うように、ガラス軟化点が603±15℃で
焼成後の線膨張係数が65±2X10−7の第2ガラス
ペーストをスクリーン印刷し、近赤外線乾燥炉によって
150℃で10分乾燥する。その後、ベルト式連続焼成
炉によって590℃の温度で、ピーク時間6分、IN=
OUT 5C1の焼成プロファイルによって焼成し、
第1ガラス層5と捺印ガラス層6と第2ガラス層7を形
成する。次に、端面電極を形成するための準備工程とし
て、端面電極を露出させるために、アルミナ基板1を短
冊状に分割し、短冊状アルミナ基板をえる一部基板分割
を行った。前記短冊状アルミナ基板の側面に、前記上面
電極層2の一部に重なるように厚膜銀ペーストをローラ
ーによって塗布し、ベルト式連続焼成炉によって600
℃の温度で、ピーク時間6分、lN−0UT45分の焼
成プロファイルによって焼成し端面電極層3を形成する
ために端面導体ペースト印刷・焼成を行う。次に、電極
メツキ工程Jの準備工程として、前記端面電極層3を形
成済みの短冊状アルミナ基板を個片状に分割する二次基
板分割を行い、個片状アルミナ基板を得る。そして最後
に、露出している上面電極層2と端面電極層3のはんだ
付は時の電極喰われの防止およびはんだ付けの信頼性の
確保のため、電解メツキによってNiメツキ層8,5n
−Pbのメツキ層9を形成する電解メツキを行う。The details of the embodiment of the present invention will be explained with reference to FIG. First, a large 96 alumina substrate with excellent heat resistance and insulation properties is inserted. In order to divide the alumina substrate into strips and individual pieces, grooves for dividing are formed (molded with a mold when forming a green sheet). Next, a thick film silver paste was screen printed on the 96 alumina substrate and fired in a belt type continuous firing furnace at a temperature of 850°C with a peak time of 6 minutes and a profile of lN-0UT of 45 minutes to form the top electrode layer 2. Form. Next, a thick film resistor paste containing RuO2 as a main component was screen printed so as to partially overlap the upper electrode layer 2, and a belt-type continuous firing furnace was used to heat the film at a temperature of 850°C for 6 minutes at a peak time of 1N-0.
The resistive layer 4 is formed by firing according to a profile with a UT time of 45 minutes. Next, in order to equalize the resistance value of the resistance layer 4 between the upper electrode layers 2, a portion of the resistance layer 4 is destroyed by laser light to correct the resistance value. Furthermore, the glass softening point is 560 to completely cover the resistance layer 4.
A first glass paste having a linear expansion coefficient of 72±2×10 −7 after firing at ±5° C. is screen printed and dried at 150° C. for 10 minutes in a near-infrared drying oven. Furthermore, on top of the dried first glass paste, a glass softening point of 560±
A stamped glass paste having a linear expansion coefficient of 71±2×10 −7 after firing at 5° C. is screen printed and dried at 110° C. for 10 minutes in a near-infrared drying oven. Furthermore, a second glass paste having a glass softening point of 603±15°C and a coefficient of linear expansion after firing of 65±2×10-7 is placed on top of the dried first glass paste to completely cover the dried stamping glass paste. was screen printed and dried for 10 minutes at 150°C in a near-infrared drying oven. After that, it was heated in a belt-type continuous firing furnace at a temperature of 590°C for a peak time of 6 minutes, IN=
Fired according to the firing profile of OUT 5C1,
A first glass layer 5, an imprint glass layer 6, and a second glass layer 7 are formed. Next, as a preparatory step for forming the end electrodes, the alumina substrate 1 was divided into strips to expose the end electrodes, and partial substrate division was performed to obtain strip-shaped alumina substrates. A thick film silver paste was applied to the side surface of the rectangular alumina substrate using a roller so as to partially overlap the upper surface electrode layer 2, and then heated for 600 minutes using a belt-type continuous firing furnace.
The end face conductor paste is printed and fired in order to form the end face electrode layer 3 by firing at a temperature of °C with a firing profile of 6 minutes peak time and 1N-0UT 45 minutes. Next, as a preparatory step for the electrode plating step J, a secondary substrate division is performed in which the strip-shaped alumina substrate on which the end face electrode layer 3 has already been formed is divided into individual pieces to obtain individual pieces of alumina substrate. Finally, the exposed top electrode layer 2 and end electrode layer 3 are soldered using electrolytic plating to prevent the electrodes from being eaten away and to ensure soldering reliability.
- Perform electrolytic plating to form a Pb plating layer 9.
以上の工程により、本発明の実施例による角板型薄膜チ
ップ抵抗器を試作した
また、比較例1として第1ガラス層・捺印ガラス層・第
2ガラス層を、ガラス軟化点が600±20℃かつ焼成
後の線膨張係数が65±2×10−7のガラスペースト
を用い、640℃で焼成した角板型チップ抵抗器を試作
し、比較例2として第1ガラス層・捺印ガラス層・第2
ガラス層を、ガラス軟化点が550±20℃かつ焼成後
の線膨張係数が65±2X10−7のガラスを用い、5
90℃で焼成した角板型チップ抵抗器を試作した。Through the above steps, a rectangular plate-type thin film chip resistor according to the embodiment of the present invention was prototyped. Also, as Comparative Example 1, the first glass layer, the stamped glass layer, and the second glass layer had a glass softening point of 600±20°C. Using a glass paste with a linear expansion coefficient of 65±2×10-7 after firing, a square plate type chip resistor was prototyped and fired at 640°C. 2
The glass layer was made of glass with a glass softening point of 550±20°C and a coefficient of linear expansion after firing of 65±2X10-7.
A square plate type chip resistor fired at 90°C was prototyped.
この本発明の実施例と比較例1、比較例2の性能比較を
第1表に示す。Table 1 shows a performance comparison between this embodiment of the present invention, Comparative Example 1, and Comparative Example 2.
第1表に示さなかった特性(抵抗温度特性、電流雑音特
性等)は本発明の実施例、従来例、比較例1.比較例2
は同等の性能を有していることを確認した。Characteristics not shown in Table 1 (resistance temperature characteristics, current noise characteristics, etc.) are those of the embodiment of the present invention, the conventional example, and comparative example 1. Comparative example 2
It was confirmed that the two had equivalent performance.
また更に、本発明の角板型チップ抵抗器は第1ガラス層
・捺印ガラス層のガラス軟化点は焼成温度より約30℃
も低いので、十分に軟化し、角板型チップ抵抗器でしば
しば問題になるガラス表面のピンホールも改善されてい
る。Furthermore, in the square plate type chip resistor of the present invention, the glass softening point of the first glass layer/imprint glass layer is about 30°C higher than the firing temperature.
Since the resistance is low, it is sufficiently softened and pinholes on the glass surface, which are often a problem with square plate type chip resistors, are also improved.
(以 下 余 白)
第
表
第1表より明らかなように、本発明の実施例の角板型チ
ップ抵抗器はガラス表面の凹凸が小さいため実装性能が
優れ(斜゛め実装無し)、耐酸性も良好で、抵抗値バラ
ツキも従来品と比べ同等で優れた性能を有していると言
える。(Left below) As is clear from Table 1, the square plate type chip resistor of the embodiment of the present invention has excellent mounting performance (no oblique mounting) due to small irregularities on the glass surface, and has excellent acid resistance. It can be said that the resistance is good, and the resistance value variation is the same as that of conventional products, indicating excellent performance.
なお、第1ガラス層にガラス軟化点が560±5℃で焼
成後の線膨張係数が72±2X10−7のガラスペース
トを、捺印ガラス層としてガラス軟化点が560±5℃
で焼成後の線膨張係数が71±2×10−7のガラスペ
ーストを、第2ガラス層としてガラス軟化点が603±
15℃で焼成後の線膨張係数が65±2×10 のガラ
スペーストを用いたが、これはガラス層を限定するもの
ではなく、これは軟化点が550℃〜570℃(555
℃〜565℃が最適)でかつ線膨張係数が69X10−
7〜75X10″77℃の第1ガラス層と、軟化点が5
50℃〜570℃(555℃〜565℃が最適)でかつ
線膨張係数が68X10−7〜74 X 10−7/’
Cの捺印ガラス層と、軟化点が580℃〜630℃(5
88℃〜618℃が最適)でかつ線膨張係数が62X1
0−7〜68 X 10−7−/℃の第2ガラス層であ
ればよい。In addition, a glass paste with a glass softening point of 560±5°C and a linear expansion coefficient of 72±2×10−7 after firing was used as the first glass layer, and a glass paste with a glass softening point of 560±5°C was used as the imprinting glass layer.
A glass paste with a linear expansion coefficient of 71±2×10−7 after firing was used as the second glass layer, and a glass softening point of 603±
A glass paste with a linear expansion coefficient of 65 ± 2 × 10 after firing at 15 °C was used, but this does not limit the glass layer; this paste has a softening point of 550 °C to 570 °C (555
℃~565℃) and linear expansion coefficient of 69X10-
7~75X10'' 77℃ first glass layer and softening point 5
50°C to 570°C (optimally 555°C to 565°C) and linear expansion coefficient of 68X10-7 to 74X10-7/'
C imprinted glass layer and a softening point of 580°C to 630°C (5
88℃~618℃) and linear expansion coefficient of 62X1
The second glass layer may have a temperature of 0-7 to 68 x 10-7-/°C.
また実施例においては、抵抗値トリミング前に抵抗値ド
リフトを抑えるためのプリコートガラスを形成しなかっ
たが、プリコートガラスを形成した後にトリミングし、
角板型チップ抵抗器を試作しても同等の性能が得られる
ことを確認している。In addition, in the example, precoat glass was not formed to suppress resistance value drift before resistance value trimming, but trimming was performed after forming precoat glass.
It has been confirmed that equivalent performance can be obtained even if a square plate type chip resistor is prototyped.
発明の効果
以上の説明より明らかなように、本発明の角板型チップ
抵抗器は抵抗値ばらつきを大きくすることなく、ガラス
の耐酸性も劣化させず、更にガラスの表面の凹凸を小さ
くし高精度実装を可能にした角板型チップ抵抗器を提供
することができるといった優れた効果が得られる。Effects of the Invention As is clear from the above explanation, the square plate type chip resistor of the present invention does not increase the variation in resistance value, does not deteriorate the acid resistance of the glass, and also reduces the unevenness of the glass surface and has a high Excellent effects such as being able to provide a square plate type chip resistor that allows precision mounting can be obtained.
第1図は本発明の一実施例による角板型チップ抵抗器の
構造を示す断面図、第2図は従来の角板型チップ抵抗器
の構造の一例を示す断面図、第3図は従来の角板型チッ
プ抵抗器が斜めに実装されたときの状態説明図である。
1・・・・・・96アルミナ基板、2・・・・・・上面
電極層、3・・・・・・端面電極層、4・・・・・・抵
抗層、5・・・・・・第1ガラス層、6・・・・・・捺
印ガラス層、7・・・・・・第2ガラス層、8・・・・
・・Niメツキ層、9・・・・・・5n−Pbメツキ層
。FIG. 1 is a sectional view showing the structure of a square plate chip resistor according to an embodiment of the present invention, FIG. 2 is a sectional view showing an example of the structure of a conventional square plate chip resistor, and FIG. 3 is a conventional one. FIG. 2 is an explanatory diagram of a state in which a rectangular plate type chip resistor is mounted diagonally. 1...96 alumina substrate, 2...Top electrode layer, 3...End electrode layer, 4...Resistance layer, 5... First glass layer, 6... Imprint glass layer, 7... Second glass layer, 8...
...Ni plating layer, 9...5n-Pb plating layer.
Claims (1)
形成される銀系厚膜の上面電極層と、前記上面電極層の
一部に重なるルテニウム系厚膜の抵抗層と、前記抵抗層
を完全に覆う軟化点が550℃〜570℃でかつ線膨張
係数が69×10^−^7〜75×10^−^7/℃の
第1ガラス層と、前記第1ガラス層上に形成される軟化
点が550℃〜570℃でかつ線膨張係数が68×10
^−^7〜74×10^−^7/℃の捺印ガラス層と、
前記第1ガラス層上で前記捺印ガラス層を完全に覆うよ
うに形成される軟化点が580℃〜630℃でかつ線膨
張係数が62×10^−^7〜68×10^−^7/℃
の第2ガラス層と、前記上面電極層の一部に重なる銀系
厚膜の端面電極層とより構成したことを特徴とする角板
型チップ抵抗器。an insulating ceramic substrate, a top electrode layer made of a thick silver film formed on the ceramic substrate, a resistance layer made of a thick ruthenium film that partially overlaps the top electrode layer, and a resistance layer that completely covers the resistance layer. A first glass layer having a softening point of 550°C to 570°C and a linear expansion coefficient of 69 x 10^-^7 to 75 x 10^-^7/°C, and a softening point formed on the first glass layer. is 550℃ to 570℃ and linear expansion coefficient is 68×10
^-^7~74×10^-^7/℃ stamped glass layer,
Formed on the first glass layer so as to completely cover the marking glass layer, the softening point is 580°C to 630°C and the linear expansion coefficient is 62 x 10^-^7 to 68 x 10^-^7/ ℃
A square plate type chip resistor comprising: a second glass layer; and a silver-based thick film end electrode layer overlapping a part of the upper electrode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008628A JP2780408B2 (en) | 1990-01-18 | 1990-01-18 | Square plate type chip resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008628A JP2780408B2 (en) | 1990-01-18 | 1990-01-18 | Square plate type chip resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03212901A true JPH03212901A (en) | 1991-09-18 |
| JP2780408B2 JP2780408B2 (en) | 1998-07-30 |
Family
ID=11698218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008628A Expired - Fee Related JP2780408B2 (en) | 1990-01-18 | 1990-01-18 | Square plate type chip resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2780408B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5379017A (en) * | 1993-10-25 | 1995-01-03 | Rohm Co., Ltd. | Square chip resistor |
| US5955938A (en) * | 1995-03-09 | 1999-09-21 | Sumitomo Metal (Smi) Electronics Devices, Inc. | RuO2 resistor paste, substrate and overcoat system |
| JP2008277628A (en) * | 2007-05-01 | 2008-11-13 | Murata Mfg Co Ltd | Method of manufacturing ceramic substrate, ceramic substrate, and electronic device |
| JP2010238801A (en) * | 2009-03-30 | 2010-10-21 | Tdk Corp | Manufacturing method of electronic parts |
| JP2011014845A (en) * | 2009-07-06 | 2011-01-20 | Tdk Corp | Electronic component |
-
1990
- 1990-01-18 JP JP2008628A patent/JP2780408B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5379017A (en) * | 1993-10-25 | 1995-01-03 | Rohm Co., Ltd. | Square chip resistor |
| US5955938A (en) * | 1995-03-09 | 1999-09-21 | Sumitomo Metal (Smi) Electronics Devices, Inc. | RuO2 resistor paste, substrate and overcoat system |
| JP2008277628A (en) * | 2007-05-01 | 2008-11-13 | Murata Mfg Co Ltd | Method of manufacturing ceramic substrate, ceramic substrate, and electronic device |
| JP2010238801A (en) * | 2009-03-30 | 2010-10-21 | Tdk Corp | Manufacturing method of electronic parts |
| JP2011014845A (en) * | 2009-07-06 | 2011-01-20 | Tdk Corp | Electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2780408B2 (en) | 1998-07-30 |
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