JPH03213007A - Frequency controller for crystal oscillator - Google Patents

Abstract

PURPOSE:To improve the frequency control accuracy by providing a frequency control coefficient correction means to correct the dispersion of the process to an electronic clock provided with the frequency control device so as to always make the relation of frequency - capacitance characteristic constant. CONSTITUTION:A signal generating circuit 2 receives an oscillation signal from an oscillation circuit 1 and outputs clock information or the like. A clock circuit 3 outputs the time information according to the count signal. A frequency control means 4 consists of a frequency control circuit 5 and a control setting circuit 6, and the circuit 5 switches the oscillation capacitor of the oscillation circuit 1 in time division for a prescribed period to control the frequency. A frequency control coefficient correction means 7 consists of a coefficient correction circuit 8, a coefficient correction circuit 8 and a coefficient correction setting circuit 9, and the coefficient correction circuit 8 selects an output resistance of the oscillation circuit 1 according to the coefficient correction setting value from the coefficient correction setting circuit 9 to correct the frequency versus capacitance characteristic. That is, even when the frequency control in time division has an error due to the dispersion by the actual manufacture, the error is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a frequency adjustment device by time division switching of an oscillation capacitor attached to a crystal oscillator.

[Conventional technology]

Conventionally, devices that adjust the frequency by time-divisionally switching the capacitors of a crystal oscillator are already well known (for example, in JP-A No. 5
0-131747) As shown in Figure 5, an oscillation circuit 1 configured to adjust the oscillation frequency by time-divisionally switching the oscillation capacitor connected to the oscillator, and an oscillation signal from the oscillation circuit 1 are input. The signal generation circuit 2 outputs a frequency-divided signal and a frequency adjustment means 4.

The frequency adjustment means 4 inputs an adjustment setting circuit 6 that outputs temperature information outputted from the temperature sensor as an adjustment setting value, an adjustment setting value from the adjustment setting circuit 6, and a frequency division signal from the signal generation circuit 2. The frequency adjustment circuit 5 controls the oscillation capacitor of the oscillation circuit 1 in a time-sharing manner for a certain period of time. Note that 6 is a clock circuit that outputs time information according to the clock signal of the signal generating circuit 2.

[Problem to be solved by the invention]

In the conventional example, the oscillation capacitor of the oscillation circuit 1 is controlled in a time-sharing manner for a certain period of time based on the set value from the adjustment setting circuit 6. Due to variations, the characteristics of the amount of frequency change with respect to the capacitor capacity will change,
Originally, even if the frequency was adjusted by controlling the capacitor in a time-sharing manner as set at the time of design, an adjustment error would occur due to the above-mentioned variations, and because the above-mentioned process variations were not taken into account, it would be difficult to achieve high accuracy. (・There was a problem that it was not possible to adjust the frequency.

In order to solve the above problem, the present invention provides a frequency adjustment coefficient correction means for correcting process variations with respect to the conventional configuration, thereby always keeping the relationship between frequency and capacitance characteristics constant. It is an object of the present invention to provide a frequency adjustment device for a crystal oscillator that can improve frequency adjustment accuracy.

[Means to solve the problem]

In order to achieve the above object, the present invention has the following configuration. That is, it has an oscillation circuit, a signal generation circuit that outputs clock information, etc., and a clock circuit that outputs time information,
In an electronic watch equipped with a frequency adjustment means for adjusting the frequency by time-divisionally switching the capacitor of the oscillation circuit, a frequency adjustment coefficient correction means is provided for correcting the adjustment coefficient of the frequency adjusted by the frequency adjustment means. It is characterized by being configured as follows.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Fig. 2 is a block diagram of an electronic timepiece equipped with a crystal oscillator according to the present invention, Fig. 1 is a circuit block diagram showing a specific configuration, Fig. 3 is a main voltage waveform diagram, and Fig. 4 is a block diagram of an electronic timepiece equipped with a crystal oscillator. It is a frequency-capacitance characteristic diagram of a crystal oscillator.

1 is an oscillation circuit equipped with a crystal oscillator; 2 is a signal generation circuit that receives the oscillation signal from the oscillation circuit 1 and outputs time information, etc.; and 3 generates time information according to the time signal from the signal generation circuit 2. This is a clock circuit that outputs .

Reference numeral 4 denotes a frequency adjustment means, which is composed of a frequency adjustment circuit 5 and an adjustment setting circuit 6, and the frequency adjustment circuit 5 controls the oscillation capacitor of the oscillation circuit 1 for a certain period of time according to the adjustment amount setting value from the adjustment circuit 6. , the frequency is adjusted by switching in a time-division manner. The above configuration is similar to the conventional example shown in FIG.

7 is a frequency adjustment coefficient correction means; a coefficient correction circuit 8;
It consists of a coefficient correction setting circuit 9.

The coefficient correction circuit 8 selectively switches the output resistance value of the oscillation circuit 1 in accordance with the coefficient correction setting from the coefficient correction setting circuit 9 to correct the frequency-capacitance characteristic.

Next, the specific configuration will be explained with reference to FIG.

The oscillation circuit 1 includes an oscillation inverter 10, an oscillation capacitor 11, 16, a crystal resonator 12, an output resistor 14, a feedback resistor 26, and a switching transistor 15 connected between the oscillation capacitor 13 and a power source.

The inverter 10 is connected to a feedback resistor 26 in parallel.
The input terminal is connected to an oscillation capacitor 11 whose one end is connected to a power source, and also connected to one terminal of the crystal resonator 12. Further, the output terminal is connected to the signal generating circuit 2 and the output resistor 1.
It is connected to one terminal of 4. The other terminal of the output resistor 14 is connected to the other terminal of the crystal oscillator 12 and an oscillation capacitor. It is connected to one terminal of 13. Further, the output resistor 14 is connected to the source terminal of an N-channel transistor (hereinafter abbreviated as N-Tr) 16.17 of the frequency adjustment coefficient correction means 7, which will be described later, and each drain terminal of the N-Tr 16.17 is connected to the output resistor. 14 intermediate tap terminals (A), e).

The other terminal of the oscillation capacitor 16 is a switching N-T for capacitor time division, one end of which is connected to the power supply.
It is connected to the other terminal of r15. The gate terminal of the switching N-Tr 15 is connected to the frequency adjusting means 4.
A control signal (PC) from the PC is input.

The signal generation circuit 2 includes a frequency dividing circuit 18 and a waveform shaping circuit 1.
It is composed of 9.

The frequency dividing circuit 18 receives the oscillation signal from the oscillation circuit 1, performs a division operation, and divides the frequency divided signals (Pfl) and (PF
2), outputs (f3). The waveform shaping circuit 19 inputs the division signal (f3) from the frequency dividing circuit 18 and outputs a driving pulse.

The clock circuit 6 includes a drive circuit 20 and a display device 21.

The drive circuit 20 receives the drive pulse from the waveform shaping circuit 19 and outputs time information, and outputs time information to the display device 2.
1 displays the time.

The frequency adjustment means 4 includes a frequency adjustment circuit 5 and an adjustment setting circuit 6.

The frequency adjustment circuit 5 includes a counter 22, a coincidence detection circuit 26, a latch circuit 24. The clock input terminal (CL) of the counter 22, which is composed of an AND gate 25, receives the frequency division signal (Pfl) from the frequency division circuit 18 and performs a counting operation. In addition, the reset terminal (6) is connected to the branch signal (Pf
2) is input, and the branch signal (PF2) is H.
The counter 22 operates only during the level period and counts the frequency divided signal (Pfl).

The coincidence detection circuit 26 receives counter 220 count information (PF) and frequency adjustment information (PL) from the latch circuit 24.
) and outputs the coincidence detection signal (PK) from the output terminal (Q.) The frequency division signal (PF2) is also input to the reset terminal (8) of the coincidence detection circuit 26, The frequency division signal (PF2) operates only during the H level period.

A frequency division signal (
pf2) is input, and the frequency divided signal (PF2) is V
level, the adjustment setting information (
PSW) is latched. At this time, adjustment setting information (PSW
) is not set and is 0, the zero detection signal (pz) is output from the output terminal (Q).

The AND gate 25 receives the frequency divided signal (Pf 1 ),
(PF2), zero detection signal (pz) from the latch circuit
and the coincidence detection signal (PK), and outputs a time division control signal (PC).

The adjustment setting circuit 6 is constituted by a storage element such as a non-volatile memory, and inputs a frequency adjustment setting value by external writing.

Reference numeral 7 denotes frequency adjustment coefficient correction means, which is composed of a coefficient correction circuit 8 and a coefficient correction setting circuit 9.

The coefficient correction circuit 8 consists of an N-Tr 16.17, the source terminal of which is connected to the output terminal of the inverter 10 of the oscillation circuit 1 and one terminal of the output resistor 14, and the source terminal of the N-Tr 16.17 The drain terminal is connected to the intermediate tap terminal of the output resistor 14, and the gate terminal is connected to the switch output terminal of the setting switch (Sl) of the coefficient correction setting circuit 9. Further, the drain terminal of the N-Tr 17 is connected to the intermediate tap terminal (B) of the output resistor 14, and the gate terminal is connected to the switch output terminal of the setting switch (S2) of the coefficient correction setting circuit 9.

Setting switches (Sl) and (S) of the coefficient correction setting circuit 9
When either of 2) is turned on, coefficient correction setting signals (Psi) and (PS2) are output from each switch output terminal. When the coefficient correction setting signal (PS 1 ) outputs an H level signal, the N-Tr 16 of the coefficient correction circuit 8
is turned on, the intermediate tap terminal (5) of the output resistor 14 of the oscillation circuit 1 and the output terminal of the inverter 10 are short-circuited, and the resistance value of the output resistor 14 is reduced to 1/2.

Also, when the coefficient correction setting signal (PS2) outputs an H level signal, the N-Tr 17 is turned on, so the output resistor 14 is connected to the intermediate tap terminal (B and the output terminal of the inverter 10). is shorted and the output resistor 14
The resistance value is 273.

Next, the frequency adjustment operation of the electronic timepiece in the above configuration will be explained.

Before frequency adjustment, the memory of the adjustment setting circuit 6 is not written, so the frequency adjustment setting information (PSW
) is set to 0. Therefore, it is output from the latch circuit 24 connected to the frequency adjustment circuit 5. When the zero detection signal (PZ) is at L level, the time division control signal (PC) from the AND gate 25 is also at L level.

Also, at this time, neither the setting switches (Sl) and (S2) of the coefficient correction setting circuit 9 of the frequency adjustment coefficient correction means 7 are set, and the coefficient correction setting means from each switch (Sl) and (S2) is not set. (Psi) and (PS2) both output L level signals. Therefore, both N-Trs 16 and 17 of the coefficient correction circuit 8 are turned off, and the output resistance 14 of the oscillation circuit 1 has a resistance value of 1/1.

Therefore, the switching Tr15 of the oscillation circuit 1 is OFF.
In other words, the oscillation operation is performed in a state where the oscillation capacitor 13 is not connected and the output resistor 14 has a resistance value of 171. Then, the signal generation circuit 2 operates with the oscillation signal as input, outputs a driving pulse, and the driving circuit 2
A time report is displayed on the display device 21 via 0.

At this point, the oscillation frequency (fs) is measured using a measuring device, and the amount of frequency adjustment is determined.

The frequency adjustment amount (f?) set at this time is the difference between the measured frequency (fs) and the actual frequency to be tuned (T8), and frequency adjustment amount (fy) = measured frequency (f,) - adjustment Including frequency (T2
). In order to adjust and set the frequency adjustment amount (f?), the frequency change amount (fc) when the oscillation capacitor 16 is connected and when it is not connected is assumed in the design, and the capacitor 13 within a specific time. Calculated from the connection time ratio. In other words, the frequency adjustment setting (i1rm)=frequency adjustment amount (f?)/frequency change amount (fc) is obtained, but since the time division control signal (PC) input to the switching Tr15 is a pulse with a duty factor of -50%, it is actually Then, the value of frequency adjustment setting value (fM)/2 is written into the storage element of the adjustment setting circuit 6.

Therefore, the adjustment setting information (psw) is output from the adjustment setting circuit 6, and the zero detection signal (PZ) is output from the output terminal Q.
becomes an H level output.

And the L of the frequency division signal (PF2) from the frequency division circuit 18
When the level signal arrives, the adjustment setting information (psw) from the adjustment setting circuit 6 is latched by the latch circuit 24, and frequency adjustment information (PL) is output.

At this point, the frequency divided signal (PF2
) is at L level during the T1 period, the frequency adjustment circuit 16
The counter 22 and the -number output circuit 23 are in a non-operating state, and the AND gate 25 is also closed, and an L-level time division control signal (PC) is output from the output terminal. The oscillation capacitor 13 is oscillating in a disconnected state.

Next, during the T2 period when the frequency division signal (PF2) is at H level, the counter 22 and the - number generating circuit 26 are in an operating state, and the counter 22 counts the frequency division signal (Pfl) and the As shown in FIG. 3), a time division control signal (PC) is output via an AND gate 25, and the oscillation capacitor 13 is connected in a time division manner to oscillate.

When the count information (PF) of the counter 22 and the frequency adjustment information (PL) from the latch circuit 24 match,
The -number configuration circuit 26 outputs an L level coincidence, and A
The ND gate 25 is closed again and the time division control signal (pc)
is set to L level, the oscillation capacitor 16 is disconnected again, and oscillation continues.

After that, the same operation as above is repeated, but the oscillation circuit 1
The oscillation frequency is −period (TI) of the frequency-divided signal (PF2).
+T2) becomes the frequency after frequency adjustment by the frequency adjustment circuit 4. However, this is just the output resistor 14 and oscillation capacitor 1 according to the design values.
1.160 This is a case in which the built-in value is correct, and if the built-in value does not match the designed value, it is necessary to correct it. The principle of the coefficient correction circuit 8 constituting the frequency adjustment coefficient correction means 7 used in the embodiment of the present invention will now be explained with reference to FIG.

FIG. 4 is a capacitance-frequency characteristic diagram in the oscillation circuit 1, where the horizontal axis shows the capacitance of the oscillation capacitor 16 (from 0 to
10PF), and the amount of frequency change (df) depending on the resistance value of the output resistor 14 is plotted on the vertical axis.

Therefore, the setting switch (Psi) of the coefficient correction setting circuit 9
), (PS2) is not set, the output resistor 1
The resistance value of the oscillation capacitor 16 remains unchanged and exhibits a capacitance-frequency characteristic as shown in C1 shown in FIG.
) becomes the value of (dfl). In addition, the setting switch (P
S2) is set, the resistance value of the output resistor 14 decreases to 2/3, thereby exhibiting the capacitance-frequency characteristic of 02 in Fig. 4, and the amount of frequency change (d) due to capacitance switching.
f) becomes (df2). Furthermore, the setting switch (Ps
When i) is set, the resistance value of the output resistor 14 is reduced to 1/2, resulting in the capacitance-frequency characteristic shown in 03 in Fig. 4, and the amount of frequency change (d
f) becomes (df3). The frequency adjustment coefficient correction means 7 of this embodiment focuses on the fact that the capacitance-frequency characteristic changes by changing the resistance value of the output resistor 14 of the oscillation circuit 1 as described above.

In other words, if the design values are met, the amount of frequency change when the oscillation capacitor 13 is connected or disconnected (
fc) changes by (dfl) and normal adjustment can be made, but
If the oscillation capacitor 11 or 13 is not manufactured according to the designed value, normal frequency adjustment cannot be performed. For example, if the capacitance of the oscillation capacitor 11 or 16 becomes smaller than the design value, the oscillation capacitor 16
The amount of frequency change (fc) when connected or disconnected becomes small, and when the frequency is adjusted according to the value set by the adjustment setting circuit 6, the frequency after frequency adjustment becomes a low frequency.

Therefore, in the present invention, the setting switch (Sl) or (S2 ) is turned on, the value of the output resistor 14 becomes 1/1.1/2. as shown in FIG.
By setting it to 2/3, the capacitance-frequency variation characteristic is changed, and when the resistance value of the output resistor 14 is 171, the frequency variation (df) is dfl, and the output resistor 14 is 27.
When the output resistance value is 3, it changes to df2, and when the output resistance value is 172, it changes to df3. For example, when the current setting switch (S2) is turned on, the coefficient correction circuit 8ON-Tr17 is turned on, and the resistance value of the output resistor 14 is reduced to 2/3. Therefore, as shown in FIG.
fc) increases, and the change value becomes (df2).

To make even larger coefficient corrections, use the setting switch (S).
l) is turned on, the resistance value of the output resistor 14 becomes 1.
/2, and the amount of frequency change (fc) further increases to df3
)become.

As described above, by correcting the young leaves of the oscillation capacitor 13 in the oscillation circuit 1 by switching the resistance of the coefficient correction circuit 8, highly accurate frequency adjustment can be performed.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, in a crystal oscillation circuit that performs time-division oscillation of a capacitor, frequency adjustment by time division is Even if errors occur, it is possible to provide a frequency adjustment device for a crystal oscillator that can perform highly accurate frequency adjustment using the same frequency setting value by providing a frequency adjustment coefficient correction means for correcting these errors.

[Brief explanation of drawings]

Fig. 2 is a block diagram of an electronic timepiece equipped with a frequency adjustment device according to the present invention, Fig. 1 is a circuit block diagram embodying Fig. 2, and Fig. 3 is a block diagram of the main voltages shown in Fig. 1. waveform diagram,
FIG. 4 is a frequency-capacitance characteristic diagram of a crystal oscillator, and FIG. 5 is a block diagram of an electronic timepiece in a conventional embodiment. 1...Oscillation circuit, 11.13...Oscillation capacitor, 14...
...Output resistance, 15...Switching transistor, 4...
... Frequency adjustment means, 5 ... Frequency adjustment circuit, 6 ... Adjustment setting circuit, 7 ... Frequency adjustment coefficient correction means, 8 ...
・Coefficient correction circuit, 9... Coefficient correction setting circuit.

Claims (2)

[Claims] (1) It has an oscillation circuit, a signal generation circuit that receives the oscillation signal from the oscillation circuit and outputs time information, etc., and a clock circuit that outputs time information, and the capacitor of the oscillation circuit is switched in a time-sharing manner to generate What is claimed is: 1. A frequency adjustment device for a crystal oscillator, characterized in that an electronic timepiece is equipped with a frequency adjustment device for adjusting the frequency of a crystal oscillator, comprising a frequency adjustment coefficient correction means for correcting an adjustment coefficient of the frequency adjusted by the frequency adjustment device. (2) The frequency adjustment coefficient correction means includes a coefficient correction circuit for switching the output resistance value of the oscillation circuit, and a coefficient correction setting circuit for outputting a control signal for causing the coefficient correction circuit to select an output resistance value. A crystal oscillator frequency adjustment device comprising: