JPH03214082A - Apparatus and method for inspecting logic circuit - Google Patents

Abstract

PURPOSE:To achieve a higher testing accuracy by providing a semiconductor integrated circuit with a data input/output means or the like equivalent to a data input/output means of a semiconductor integrated circuit apparatus before replaced to supply a test pattern to the circuit apparatus. CONSTITUTION:When inspecting a logic operation test of a peripheral circuit 3a of a substrate 3 and transmission state of an analog signal between the circuit 3a and an LSI socket 3b, first, the socket 3b of the substrate 3 with an Application Specific Integrated Circuit (ASIC) under development removed is connected to an ASIC emulator 10 through a socket 7 connected to a pod 11. Then, an I/O control signal or the like is supplied to an I/O control signal memory 22b through the emulator 10, the pod 11 and the like. The socket 7 has an I/O circuit 22a equivalent to an I/O circuit assembled into the ASIC as repeater and a logic operation test, an analog voltage test and the like are conducted with the side of the substrate 3 being separated from the side of inspection having the pod 11, the emulator 10 and the like.

Description

[Detailed Description of the Invention] [Summary] A logic circuit testing device and method for testing the logic operations of a plurality of semiconductor integrated circuit devices mounted on a substrate using an external test pattern, especially for ASICs, etc. under development. Regarding an interface matching verification device and its verification method for verifying peripheral circuits on boards such as logic circuit printed boards in which semiconductor integrated circuit devices are incorporated, The purpose of this document is to provide a logic circuit testing device and testing method that performs well and does not limit the test cycle due to signal delay time caused by cables, especially when the operating speed of ASIC etc. is high. In a logic circuit testing device that tests the logical operation of a plurality of mounted semiconductor integrated circuit devices using an external test pattern, the device is mounted as a replacement for at least one semiconductor integrated circuit device among the plurality of semiconductor integrated circuit devices. The semiconductor integrated circuit device for testing includes data input/output means equivalent to the data input/output means of the semiconductor integrated circuit device before replacement, and the data input/output means for testing. control means for controlling input/output of the semiconductor integrated circuit device for inspection, configured to supply the test pattern to the plurality of semiconductor integrated circuit devices via the data input/output means; Furthermore, the semiconductor integrated circuit device for testing is configured to include a storage means for storing the test pattern, and further, the testing apparatus for logic circuits having the semiconductor integrated circuit device for testing including the storage means is used. In the method for testing logic circuits, the test pattern generated from the testing means is temporarily stored in the storage means, and then the logic of a plurality of semiconductor integrated circuit devices is tested based on the test pattern stored in the storage means. perform the operation, then temporarily store the results of the logical operations of the plurality of semiconductor integrated circuit devices in the storage means, and then send the results of the logical operations stored in the storage means to the inspection means. , then,
The testing means analyzes and tests the logic operations of the plurality of semiconductor integrated circuit devices based on the results of the logic operations.

(Industrial Application Field) The present invention relates to a logic circuit testing device and testing method for testing the logic operations of a plurality of semiconductor integrated circuit devices mounted on a board using an external test pattern. In other words, the ASIC (App
lication 5pecifjc Integra
This article refers to a so-called interface matching verification device and its verification method for verifying peripheral circuits (boards/systems) on a substrate such as a logic circuit printed board into which a semiconductor integrated circuit device such as ted circuit is incorporated.

In recent years, due to functional requirements depending on users' usage patterns, there has been a tendency for many ASICs such as VLSIs and microcomputers to be incorporated into logic circuit printed boards that perform general logic operations.

Therefore, there is a need for the above-mentioned testing device that can perform an interface matching test (also referred to as ASrC emulation) between an ASIC and its peripheral circuits at a stage before the ASfC under development is manufactured.

[Conventional technology]

FIG. 10 is a block diagram of a conventional logic circuit testing device.

In the figure, the logic circuit inspection device is, for example, an ASIC emulator that inspects a semiconductor integrated circuit device 4 under development as shown in the circle with two-dot chain lines, and a substrate 3 such as a logic circuit printed board in which an ASIC is incorporated. 10 and substrate 3
A socket adapter 2 that is connected (fitted) to the LSI socket 3b of
Both are connected by a cable 5.

Moreover, the figure inside the broken line circle has shown the perspective view based on the socket adapter 2. In the figure, the main structure of the socket adapter 2 is formed by lead-out portions 2a of a plurality of signal lines within the cable 5 and pin connectors 2b connected to these lead-out portions 2a.

In the above inspection apparatus, first, a test signal is supplied via the ASIC emulator 10, the bot 11, and the socket adapter 2 to the board 3 from which the eight SICs under development have been removed, that is, in front of the ASxctiii.

Next, this test signal appears as a signal under test at the LSI socket 3b via the peripheral circuit 3a of a plurality of semiconductor integrated circuit devices already installed, for example, an ASIC under development. Connect this signal under test to socket adapter 2.
, the board 11 and the testing means 1, and the logical operation of the board 3 with the ASIC under development removed is tested.

[Problem to be solved by the invention]

FIG. 11 is an equivalent circuit diagram for explaining the conventional problems, and shows an electrical circuit diagram between the peripheral circuit 3a and the ASIC emulator IO related to one terminal of the LSI socket 3b. However, in this case, Bod 11 (8th
Figure) will be omitted.

In the figure, RI is the wiring resistance, and LSI socket 3
It shows the resistance between b and the peripheral circuit 3a. R@ is the resistance of the signal line in the cable 5, and is the resistance of the signal line in the cable 5,
and the ASIC emulator lO. Zo is the output impedance of the peripheral circuit 3a, and L
When an ^SIC under development is mounted in the SI socket 3b, impedance matching is performed with the input impedance of the ASIC. ZI is the input impedance of the ASIC emulator 10, and is determined by line constants such as the wiring resistance Re and the resistance R1 of the signal line in the cable 5.
It is different from the input impedance of the node 3b.

According to this, when the signal under test S, which is output from the peripheral circuit 3a after supplying the test signal from the ASIC emulator 10, is taken into the ASIC emulator IO via the LSI socket 3b, the logic of the signal under test S1 is "L". "(Low)" or "H" (formerly gh) can be transmitted to the AS4C emulator IO even though it is affected by the impedance mismatch state, that is, by the wiring resistance R1, the signal line resistance R3, or their inductances.

However, noise caused by the wiring between the LSI socket 3b and the peripheral circuit 3a may be included in the overall analog signal noise between the peripheral circuit 3a and the ASIC emulator 10. In other words, when observing the analog waveform with the ASIC emulator IO, the peripheral circuit 3a to A
The voltage waveform transmitted to the SIC emulator IO is based on the output impedance Z0, wiring resistance RI, signal line resistance R,
and input impedance Z, and may be distorted. As a result, the peripheral circuit 3a and the LSI socket 3b
Is the logic amplitude insufficient due to noise caused by the wiring between the LSI socket 3b and the ^SIC emulator IO? Or is the logic amplitude insufficient due to noise caused by the signal line in the cable 5 between the LSI socket 3b and the ^SIC emulator IO? cannot be distinguished.

Therefore, if an ASIC developed and manufactured in a state where analog signal transmission between the peripheral circuit 3a and the Li socket 3b is incomplete is installed, it is determined that the ASIC is malfunctioning even though the ASIC is normal. may be done,
Therefore, a problem arises in that verification of the peripheral circuit 3a on the substrate 3 such as a logic circuit printed board cannot be performed with high accuracy. As a result, it takes time and man-hours to return the normal ASIC to the development process and investigate the cause, which may cause a delay in the entire development process.

Furthermore, in order to feed back the inspection results from the above-mentioned inspection apparatus to the ASIC side as quickly as possible, a series of tests including verification of the peripheral circuit 3a on the board 3 and the like are normally performed in real time. That is, while the above tests are being performed, test signals including various test patterns necessary for these tests must be transmitted one after another from the ASIC emulator IO to the board 3 via the cable 5 etc. Must be. For this reason, as the cable 5 becomes longer, the delay time of the test signal due to the signal line within the cable 5 becomes thicker, which causes the problem that the test cycle is limited by this delay time.Especially during development. When the operating speed of an ASIC is high, the influence of the above-mentioned delay time becomes significant, and it becomes difficult to perform a test in a manner close to the actual operation of the ASIC.

The present invention has been made in view of the above-mentioned problems, and it performs a series of tests with high accuracy such as verification of logic circuit printed boards into which ASICs etc. under development are incorporated.
It is an object of the present invention to provide a logic circuit testing device and a testing method thereof, in which the test period is not limited by the length of a signal transmission cable when the operating speed is high.

[Means to solve the problem]

FIG. 1A is a diagram showing the principle of the logic circuit testing apparatus of the present invention. Note that components similar to those described above are denoted by the same reference numerals.

As shown in FIG. 1, the inspection apparatus of the present invention includes a semiconductor integrated circuit device for inspection mounted in place of at least one semiconductor integrated circuit device 4 among a plurality of semiconductor integrated circuit devices mounted on a substrate 3. The test semiconductor integrated circuit device 6 is equipped with a circuit device 6, and the test semiconductor integrated circuit device 6 has a data input/output means 1 equivalent to the data input/output means 14a of the semiconductor integrated circuit device before replacement.
2a, and a control means 12b for controlling input/output of the data input/output means 12a, and the semiconductor integrated circuit device 6 for inspection is configured to control the plurality of semiconductor integrated circuit devices via the data input/output means 12a. It is configured to supply test patterns from the outside.

Preferably, the logic circuit testing device of FIG. 1A includes a testing means 1 for generating the test pattern, a socket 7 containing the testing semiconductor integrated circuit device 6 for receiving the test pattern, and a socket 7 for receiving the test pattern. A cable 5 for transmitting data to the semiconductor integrated circuit device 6 for inspection is provided.

FIG. 1B is another principle diagram of the logic circuit testing apparatus of the present invention. Here, the semiconductor integrated circuit device 6 for inspection shown in FIG. 1A is further provided with a storage means 12c for storing the test pattern. The other configurations are the same as those shown in FIG. 1A.

More preferably, the logic circuit testing device of FIG. 1B comprises:
A socket 7 which includes an inspection means l for generating the test pattern, a semiconductor integrated circuit device 6 for inspection that receives the test pattern, and a socket 7 that includes the storage means 12c and a semiconductor integrated circuit device 6 for inspection that receives the test pattern; A cable 5 for transmitting data to a circuit device 6 is provided.

Furthermore, by using the inspection device shown in FIG. 1B above,
The test pattern generated from the inspection means l is temporarily stored in the storage means 12c, and then
A plurality of semiconductor integrated circuit devices are caused to perform logical operations based on the test patterns stored in the storage means 12, and the results of the logical operations of the plurality of semiconductor integrated circuit devices are then stored in the storage means 12.
c, and then sends the result of the logical operation stored in the storage means 12c to the checking means l, and then the checking means l performs the plurality of operations based on the result of the logical operation. The present invention provides a logic circuit testing method for analyzing and testing the logic operation of a semiconductor integrated circuit device.

[For production]

According to the principle of the present invention (FIG. 1A), the socket 7 etc. has a data input/output means 12 equivalent to the input/output means 14a incorporated in the semiconductor integrated circuit device 4 such as the ASIC under development.
A semiconductor integrated circuit device 6 for testing is built-in.

Therefore, the output impedance of a plurality of other semiconductor integrated circuit devices (for example, peripheral circuit 3a) already mounted on the board 3 such as a logic circuit printed board and the input impedance of the data input/output means 12a provided in the socket 7 The consistency state with AS developed and manufactured in place of socket 7
[The matching state of both impedances can be made the same as when C etc. are attached.] Therefore, when the logic amplitude is insufficient due to an analog cause such as noise entering the wiring, etc., the data input/output means 12a provided in the socket 7
The control means 12b acts as a repeater, making it possible to inspect the substrate 3 side and the inspection means 1 side in a state where they are separated and differentiated.

Furthermore, according to another principle of the present invention (FIG. 1B), other semiconductor integrated circuit devices r! on the substrate 3! 1 (for example, peripheral circuit 3a), a test pattern is stored in advance in the storage means 12c in the socket 7, and the equivalent input/output means 12a is transferred from the storage means 12c by an external clock signal or the like. A test pattern is supplied to the board 3 via the control means 12b to start the test. Therefore, the peripheral circuit 3 on the board 3
Since the delay time of the test signal due to the cable 5 need not be taken into account when performing the verification of a, etc., the test cycle is not limited by this delay time.

Thus, in the present invention, a series of tests such as verification of the board 3 can be performed with high precision in a state where the board 3 side and the inspection means l side are separated and differentiated. Furthermore, the test cycle is not limited by the length of the signal transmission cable, etc., so AS
Even when the operating speed of an IC or the like is high, it is possible to perform high-quality tests in a manner close to actual operation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2 to 9 are diagrams for explaining a logic circuit testing device according to an embodiment of the present invention, and FIG. 2 shows a logic circuit testing device according to an embodiment based on the principles of the present invention. Such a configuration diagram is shown.

In FIG. 2, the inspection means 1 is connected to a data analysis workstation (not shown) or the like.
IC emulator 10 and this SIC emulator I
A box 11 is connected to a cable 5 via a cable 5. Note that this box 11 is connected to the socket 7 via a cable 5.

The ASIC emulator IO is a logic circuit mounted with at least one semiconductor integrated circuit device 4 under development, such as a semiconductor integrated circuit device 6 for testing in place of an ASIC, as shown in the circle with a dashed-dotted line. This is for inspecting a substrate 3 such as a printed board. The pod 11 transmits test signals and control signals from the ASIC emulator 10 into the LSI socket 3b, and transmits signals under test from the LSI socket 3b to the ASIC emulator IO.

Furthermore, A
An interface circuit (hereinafter simply referred to as 170 circuit) having the same characteristics as the data input/output means 14a, such as an interface circuit for data input/output incorporated in the SIC.
22a, and as a control means 12b, an I10 control signal storage circuit 22b for controlling the 110 circuit 22a is provided.

The socket 7 includes the above-mentioned I10 control signal storage circuit 22b,
It consists of an I10 circuit 22a and a pin connector 2b, and the output signal from the socket 7 reaches other semiconductor integrated circuit devices on the board 3, such as a peripheral circuit 3a, via the pin connector 2b and the LSI socket 3b. Note that this peripheral circuit 3a has a function of performing logical operations of the ASIC and interoperating with other LSIs. Next, the above socket 7
The circuit configuration etc. inside will be explained in more detail.

FIG. 3 is a circuit diagram of a socket according to an embodiment based on the principle of the present invention.

In the figure, the l10811171 signal storage circuit 22b stores a signal from bond I■, for example, the l10IIJ control signal (
Serial data) Sl, emulated signals S2 and 1
10 control signal (clock) S3 is inputted to cause each of the 110 circuits 22a to output a first gate selection signal S and a second gate selection signal S. Also, an output signal S from the I10 circuit 22a. is input and outputted to the box 11. The configuration of the 110 control signal storage circuit 22b will be explained with reference to FIG.

In addition, the I10 circuit 22a is connected to the bin connector 2 of the socket 7.
b, inputs the first and second gate selection signals StS from the I1010 control memory circuit 22b, and imports the terminal information of the bin connector 2b of the socket≠≠4-7, and also inputs the first and second gate selection signals StS from the I1010 control memory circuit 22b. The test signal etc. from the output signal S4m are supplied as the output signal S4m.

As a result, based on the signal from the bot 11, the I10
The I10 control memory circuit 22b can control the input/output of the I10 circuit 22a.

FIG. 4 shows an embodiment based on the principle of the present invention.
FIG. 3 is a configuration diagram related to a III signal storage circuit.

In the figure! The 1010 control memory circuit 22b includes a first latch function circuit 31, a second latch function circuit 33, two-man power NOR circuits 32-1 to 32-n, and a two-man power NOR circuit 32-1 to 32-n.
It consists of AND circuits 34-1 to 34-n. The first latch function circuit 31 is! Based on the 1010 control signal l, S3, the first latch signal S is input to the human-powered NOR circuits 32-1 to 32-1.
32-n. These two-man power NOR
The circuits 32-1 to 32-n are a two-man NOR circuit of the first latch signal S and the emulated signal S8 from the bot 11.
It performs a logical operation and outputs the resultant first gate selection signals S, (P1 to Pn) to the gate transistors T1 to T4 (FIG. 5) of the I10 circuit 22a.

The second latch function circuit 33 is the first latch function circuit 3
1, the second latch signal S6 is input to the two-man NAND circuits 34-1 to 34-3 based on the I1010 control signals 1 and S3.
4-n. These two-person NAND
The circuits 341 to 34-n perform a two-person logical operation on the second latch tt and the emulated signal S2, and produce a second gate selection signal 58 (Nl to Nn) as a result signal.
The gate transistors T7 to T10 of the I10 circuit 22a
(Fig. 5).

This controls the driving ability of the output buffer configuring the I10 circuit 22a.

FIG. 5 is a block diagram of 110 circuits of the embodiment based on the principles of the present invention, and shows a block diagram equivalent to the 10 circuits of the ASIC under development.

In the figure, T connected between the power supply line V and VSS
I-T4 is a p-channel MOSFET, and T7~
T10 is an n-channel MO5FET. This P.

Output buffer circuit 2 using n-channel MOSFET
2A, and a gate selection signal 58=N1-Nn is input to the gate of a p-channel type MOSFET.

Similarly, the power line Vllll and ■5. T5. T6 is a p-channel type MOSFET, and Tl
l.

TI2 is an n-channel type l'1O3 FET. The input buffer circuit 22B is composed of these p and n channel type MOSFETs. As a result, the first and second gate selection signals S, , S via the 1010 control signal 1, Sa, and the emulated signal St from the bond 21b.

Accordingly, input, output, or bidirectional selection of the I10 circuit 22a is performed.

These constitute a logic circuit testing device according to an embodiment of the present invention.

Next, the operation of the inspection device will be explained.

FIG. 6 is an equivalent circuit diagram for explaining the inspection operation according to the embodiment based on the principle of the present invention.
3 shows an electrical circuit diagram between the peripheral circuit 3a and the pod 11 related to one terminal b.

In the figure, the test equipment is used to test the logic operation of the peripheral circuit 3a of the board 3, the peripheral circuit 3a and the LSI socket 3.
When inspecting the transmission status of analog signals between
First, L of board 3 with the SIC under development removed.
The SI socket 3b and the ASIC emulator 10 are connected via the socket 7 connected to the bot II (see FIGS. 1A and 2). At this time, the I10 in the socket 7
The input impedance Zrn of the circuit 22a is impedance matched with the output impedance Z0 of the peripheral circuit 3a. That is, the input impedance Z in is
Wiring resistance R between peripheral circuit 3a and LSI socket 3b
It is determined by circuit constants including 1, etc.

In this case, the I10 circuit 22a is the I10 circuit 22a of the ASIC under development.
0 circuit, the impedance matching state will be the same even when a developed and manufactured ASIC is installed in place of the socket 7.

Then, the I1010 control signal 1, the emulator signal S2 and the 110 control signal S are supplied to the 110 control signal storage device 22b via the SIC emulator 10, Bon'11 and cable 5. At this time, for example, when supplying a test signal to the peripheral circuit 3a etc., the function of the output buffer circuit 22A (FIG. 5) is stopped via the first and second gate selection signals S, , S. . In addition, when taking out a test signal that has passed through another peripheral circuit as a signal under test, the I10 circuit 22a is made to function as an input circuit and the voltage waveform of logical amplitude appearing on the pin connector 2b is sent directly to the bot 11. .

Furthermore, by making the I10 circuit 22a bidirectional, the output information of the output buffer circuit 22A is sent to the pod 11 via the peripheral circuit 3a and the bin connector 2b.

By performing logic operation tests, analog voltage tests, etc. using this output information and test signals, peripheral circuits 3a, etc. on the substrate 3, such as a logic circuit printed board, can be inspected.

Thus, according to an embodiment of the present invention, the socket or ≠science≠7 is provided with 110 times 11t22a, which is equivalent to 110 circuits incorporated in the ASIC.

Therefore, the output impedance Z0 of the peripheral circuit 3a provided on the board 3 and the I10 circuit 2 provided on the socket 7
The matching state of input impedance Z ia of 2a can be made equivalent to the matching state of both impedances when the developed and manufactured ASIC is attached instead of the socket 7. Therefore, even if the logic amplitude is insufficient due to analog causes such as noise entering the wiring between the peripheral circuit 3a and the LSI sockets 1-3b, the 110 circuit 22a provided in the socket 7 acts as a repeater, and side and
It becomes possible to perform logic operation tests, analog voltage tests, etc. in a state where the test system side such as the bot 11, the ASIC emulator IO, and the cable 5 are separated and distinguished.

This makes it possible to inspect the substrate 3 with higher precision than in the conventional method (FIG. 11). Also, normal ASI
Since C is not misjudged to be malfunctioning and is not sent back to the redevelopment process, the development of the SIC can be accelerated.

Note that by selecting the drive capability of the output buffer circuit 22A, it is possible to accurately switch the input level and the output drive capability.

FIG. 7 is a block diagram of a logic circuit testing apparatus according to an embodiment based on another principle of the present invention. Here, the semiconductor integrated circuit device 6 for inspection built into the socket 7 of FIG.
Furthermore, a storage means 12c is provided. As this storage means 12c, a test data storage circuit 22c consisting of a rewritable RAM or the like is used to previously store the test pattern included in the test signal from the SIC emulator 1O and temporarily store the test result included in the signal under test. has been established. Note that the other configurations are the same as those shown in FIG. 2 above.

FIG. 8 is a circuit diagram of a socket according to an embodiment based on another principle of the present invention. The circuit configuration in FIG.
Although it is almost the same as the figure, the difference is that a test data storage circuit 22c is provided between the pod 11 and the l10H control signal storage circuit 22b.

This test data storage circuit 22c stores the emulated signal S! Memorize the test patterns included in the test before the test,
And, after the test, the logic circuit printed board 3 to I10 circuit 2
2a (output signal 54b)
) is used to temporarily store the test results included in the test results. When starting the above test, use the SIC emulator lO
Using the test pattern storage/output clock signal S4 from the test data storage circuit 22c as a trigger, a test signal including the test pattern is output from the test data storage circuit 22c. This output test signal is output to the bin connector 2b of the socket 7 via the I10 control signal storage circuit 22b and the 110 circuit 22a. In this case, the clock signal S4 is sent from the ASIC emulator 10 to the bond 11.
Although it is supplied through the substrate 3, it may be supplied from the substrate 3 side instead. On the other hand, in cases where a large number of ASICs are mounted on one board 3, in order to speed up tests such as interface matching inspection, the next test should be carried out immediately after the test for one ASIC is completed. Testing for SIC must begin. At this time, before sending the test result from the pin connector 2b to the bond 11 via the I10 circuit 22a and the I10 control signal storage circuit 22b, the test result is sent to the test data storage circuit 22c.
It is desirable to temporarily store the information in the internal RAM.

FIG. 9 is a flowchart for explaining test data input/output operations according to an embodiment based on another principle of the present invention.

If you want to perform a series of tests such as logic operation tests and analog voltage tests on the peripheral circuit 3a on the board 3, first edit the predetermined test patterns necessary for these tests using a workstation, etc., and create the test circuit. The whole is set to input cover turn transmission mode (step a). Next, in this input pattern transmission mode, that is, before starting the test, the test pattern is sent in advance to the test data storage circuit 22c in the socket 7 and stored (
Step b). Furthermore, the test pattern storage/output clock signal S4 is used as a trigger to set the entire test circuit to a test mode, and in step c), a test signal including the test pattern is supplied from the test data storage circuit 22c to the peripheral circuit 3a for testing. (step d). Furthermore, the signal output by the peripheral circuit 3a during the test, that is, the signal input to the I10 circuit 22a, is temporarily stored in the test data storage circuit 22c (step e). After all of the above tests are completed, the entire test circuit is set to the output return transmission mode by the I10 control ring (step r). The above storage operation is effective when a large number of ASICs to be tested are mounted on one board 3. In this case, when the tests on all ASICs are completed, the test results stored up to that point can be sent to the ASIC emulator 0 at once, or each ASIC can be tested each time the test on one ASIC is completed. The results are sent to the ASIC emulator 10 (step g), and the sent test results are finally analyzed on a workstation or the like.

According to the flowchart of FIG. 9, there is no need to transmit the test signal through the cable 5 (FIG. 7) while the test is being performed, so even if the cable 5 becomes long, the delay of the test signal will be There is no need to consider. For this reason, the test speed can be made faster than before, so even if the operating speed of the ASIC under development is high, this ^SIC
This makes it possible to conduct rigorous tests that closely resemble the actual operation of the system.

〔Effect of the invention〕

As explained above, according to the present invention, the ASIC under development
By installing a semiconductor integrated circuit device for testing having 110 circuits, etc., equivalent to 110 circuits in the socket, the impedance matching state between the socket and the board such as a logic circuit printed board can be maintained as when installing the above ASIC after development and manufacture. Since the same state can be set, a series of tests such as verification of the logic circuit printed board described above can be performed with high accuracy. As a result, it becomes possible to develop ASICs at an early stage without having to take the trouble of returning normal ^SICs to the development process again.

Furthermore, by providing a memory circuit etc. in the socket,
Since the test cycle is no longer limited by the signal delay time caused by the cable, it becomes possible to perform high-quality tests in a manner similar to the actual operation of the ASIC. Especially A.S.
The present invention is effective when the operating speed of the IC is high.

[Brief explanation of drawings]

FIG. 1A is a principle diagram of the logic circuit testing device of the present invention, FIG. 1B is another principle diagram of the logic circuit testing device of the present invention, and FIG. 2 is a principle diagram of the logic circuit testing device of the present invention. 〈A configuration diagram of a logic circuit inspection device according to an embodiment, Fig. 3 is based on the principle of the present invention.〈A circuit configuration diagram concerning a socket according to an embodiment, Fig. 4 is based on the principle of the present invention〈 FIG. 5 is a block diagram of the 110 control signal storage circuit of the embodiment based on the principle of the present invention. FIG. 6 is a block diagram of the 110 control signal storage circuit of the embodiment based on the principle of the present invention. FIG. 7 is an equivalent circuit diagram for explaining the testing operation according to the example, and FIG. Based on the principle, FIG. 9 is a circuit configuration diagram related to the socket of the embodiment, and FIG. 9 is a flowchart for explaining the test data input/output operation according to the embodiment, based on another principle of the present invention. FIG. 11 is an equivalent circuit diagram for explaining the problems of the conventional logic circuit. In the figure, l... Inspection means, 3... Board, 4... Semiconductor integrated circuit device, 5... Cable, 6... Semiconductor integrated circuit device for inspection, 7... Socket, 12a ...Data input/output means, 12b...
- Control means, 12c... Storage means.

Claims (5)

[Claims] 1. In a logic circuit testing device that tests the logical operation of a plurality of semiconductor integrated circuit devices mounted on a substrate using an external test pattern, the method comprises: replacing the plurality of semiconductor integrated circuit devices with at least one semiconductor integrated circuit device; The semiconductor integrated circuit device for testing is equipped with a data input/output means equivalent to the data input/output means of the semiconductor integrated circuit device before replacement, and the semiconductor integrated circuit device for testing is equipped with a data input/output means equivalent to the data input/output means of the semiconductor integrated circuit device before replacement; and control means for controlling input/output of the output means, wherein the semiconductor integrated circuit device for inspection supplies the test pattern to the plurality of semiconductor integrated circuit devices via the data input/output means. Testing equipment for logic circuits. 2. 2. The logic circuit testing apparatus according to claim 1, wherein said semiconductor integrated circuit device for testing further comprises storage means for storing said test pattern. 3. A logic circuit inspection device for inspecting the logic operations of a plurality of semiconductor integrated circuit devices mounted on a substrate using an external test pattern, the logic circuit inspection device comprising: inspection means for generating the test pattern; Claim 1 receiving a pattern
A logic circuit testing device comprising: a socket incorporating the semiconductor integrated circuit device for testing as described above; and a cable for transmitting the test pattern to the semiconductor integrated circuit device for testing. 4. 4. The logic circuit testing device according to claim 3, wherein the logic circuit testing device includes a testing means for generating the test pattern, and a semiconductor integrated circuit device for testing according to claim 2, which receives the test pattern. What is claimed is: 1. A logic circuit testing device comprising: a socket for testing a test pattern; and a cable for transmitting the test pattern to the semiconductor integrated circuit device for testing. 5. 5. A logic circuit testing method using the logic circuit testing device according to claim 4, comprising: temporarily storing the test pattern generated by the testing means in the storage means; and then storing the test pattern in the storage means. causing a plurality of semiconductor integrated circuit devices to perform logical operations based on the test pattern, then temporarily storing the results of the logical operations of the plurality of semiconductor integrated circuit devices in the storage means; The method is characterized in that the stored results of the logical operations are sent to the testing means, and then the testing means performs an analysis test of the logical operations of the plurality of semiconductor integrated circuit devices based on the results of the logical operations. A method for testing logic circuits.