JPH03214275A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of Industrial Application The present invention relates to a semiconductor integrated circuit having an instruction space and a data space in separate memory spaces.

1. Prior Art] FIG. 6 is a diagram showing an example of the system configuration of a conventional semiconductor integrated circuit of this type. In the figure, 1 is a digital signal processing processor, 2 is an external command memory, and 3 is an external data processor. Memory, 4 is a clock generator, CLK is a clock input terminal, IAD is an instruction address output terminal, IDA is an instruction input terminal, DA[ is a data address output terminal, DDA is a data output terminal, RD is a data read signal output terminal, WF
i is a data write signal output terminal.

In addition, FIG. 7 shows the data other than the digital signal in FIG. 6. 51 is a program counter, 52 is an internal instruction memory, 53 is an instruction register, 54 is an address register, 55 is an internal data memory,
60 is an instruction address bus, 61 is an instruction path, and 62 is a data address bus. 63 is a data bus.

Next, the operation will be explained.

Regarding the instruction space, when accessing the external instruction memory 2, the program counter 5l first outputs the indicated instruction address IA to the instruction address bus 6o. Next, the instruction address output IAD sends the instruction I from the external instruction memory 2 to the instruction manual ID? through the command bus 61 and held in the command register 53. When accessing the internal instruction memory 52, the internal instruction memory 52 indicated by the instruction address IA
The data is held in the instruction register 53.

Regarding the data space, data D indicated by the address A held in the address register 54 is exchanged according to the contents of the command held in the instruction register 53. When accessing the external data memory 3, address A is output to the data address bus 62. The external data memory 3 is accessed by the data address output DAD, and data D is exchanged with the data bus 63 through the input/output DDA. When accessing the internal data memory 55, the data D' of the internal data memory 55 indicated by the address A is output to the data path 63 or input from the data bus 63.

As described above, a microcontroller sensor with a configuration in which the instruction space and data space are different can execute instruction space processing and data space processing in parallel using the buses of each space, so there is no bus contention. It is used in digital signal processing processors that require high-speed, real-time processing.

[Problem to be solved by the invention]

Conventional semiconductor integrated circuits such as those described above enable high-speed operation by having different instruction spaces and data spaces. However, there is a problem in that address pins and data pins for accessing the external command space and data space must be provided for each space, and a large number of pins are required. Further, depending on the user, an external data memory may not be necessary, or an internal instruction memory may be sufficient for the instructions, and in such cases, each bin is unnecessary and the cost increases.

This invention was made in order to solve the above-mentioned problems, and it is possible to create a semiconductor integrated circuit that has a configuration in which the instruction space and data space are different, and can take advantage of its advantages with a small number of external pins. The purpose is to obtain.

[Means to solve the problem]

A semiconductor integrated circuit according to a first aspect of the present invention is provided with a first selection circuit that selects an instruction address path and a data address bus, and a second selection circuit that selects an instruction bus and a data path, and has external pins. The instruction space and data space are shared.

Further, in the second and third aspects of the present invention, whether or not to perform bus switching by the first and second selection circuits is determined by a first method that sets whether or not to use external instruction storage means. It is set by the input value from the second input terminal that sets whether or not to use the input terminal and the external data storage device, or it is set by a command from the present integrated circuit device, and the input terminal and the external data storage device are set by the input value from the second input terminal. This is set by first and second control bits having similar functions.

[Effect]

In the semiconductor integrated circuit according to the first aspect of the present invention, I
The SI selection circuit selects the instruction address bus and the data path address bus, and the second selection circuit selects the instruction bus and data path, so the common bus is time-shared between the instruction space and the data space. It can be used with a small number of external bins, and it is possible to input and output addresses in the instruction space and data space, as well as the instructions and data themselves.

Moreover, in the second and third inventions of this invention, the first
The input terminal or the first control bit sets whether or not to use the external instruction storage device, and the second input terminal or the second control bit sets whether or not to use the external data storage device. 1 input terminal or the first
Whether or not the first and second selection circuits perform the selection operation is controlled by the control bit and the second input terminal or the second control bit. A product that can be used in one product type can be obtained without any further development.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention, and here shows a system configuration when the circuit is applied to a digital signal processing processor. In the figure, 1 is a digital signal processing processor, 2 is an external instruction memory, 3 is an external data memory, 4 is a clock generator, 5.6 is an address register, 7.8 is a data register, and 9 is an inverter. Also, ADDR is an address output terminal, DATA is a data input/output terminal, DAL is a data address latch signal terminal, JAL is an instruction address latch signal terminal, I/U is an instruction data switching signal terminal, and R/W is a data read/write terminal. Control terminal CLK is a clock input terminal, EIM is an external command space use signal terminal, and EDM is an external data space use signal terminal.

FIG. 2 is an internal block diagram of the digital signal processing processor in FIG. 1, in which 51 is a program counter;
2 is an internal instruction memory, 53 is an instruction register, 54 is an address register, 55 is an internal data memory, 56 is an address bus selection circuit, 57 is a data path selection circuit, 58 is a control circuit that generates each control signal, and 60 is a 61 is an instruction bus, 62 is a data address bus, and 63 is a data path. Note that when the address bus selection circuit 56 and the data path selection circuit 57 use external memories for both the instruction memory and the data memory, the paths are switched every half cycle of the operating machine cycle, and only one of the instruction memory and the data memory uses the external memory. Sometimes only the selection circuit on the side using the external memory switches the bus every half cycle of the operating machine cycle,
The output of the other selection circuit is in a tri-state state and no switching is performed.

FIG. 3 is an operation timing diagram of the digital signal processing processor of FIG. 2.

Next, the operation will be explained.

First, a case will be described in which both an external command space and an external data space are used. In this case, both the external command space use signal terminal EIM and the external data space use signal terminal EDM are set to ``H'' to set the mode in which the external command memory and external data memory are used. Next, the instruction address IA indicated by the program counter 51 is output to the instruction address bus 60. The instruction address IA is selected by the address bus selection circuit 56 for the period shown in FIG.
The first half of +1, . . . is output to the address output terminal ADDR. The instruction address IA is temporarily held in the address register 5 by the launch signal output from the instruction address launch signal terminal IAL, and then the external instruction memory 2 is accessed. The instruction I output from the external instruction memory 2 is held in the data register 7 by the instruction data switching signal terminal I/U in the latter half of the operation machine cycle, and then transferred to the data input/output terminal D.
Output to ATA. The fetched instruction I is selected by the data path selection circuit 57, outputted to the instruction bus 61, and held in the instruction register 53.

Regarding the data space, data corresponding to the address A indicated by the address register 54 is exchanged according to the instruction contents held in the instruction register 53. Address A passes through the data address path 62 to the address path selection circuit 5.
6 and output to the address output terminal ADDR during the second half of the operating machine cycle as shown in FIG. Thereafter, the data is temporarily held in the address register 6 by a latch signal output from the data address launch signal terminal DAL, and the external data memory 3 is accessed. When reading the external memory when the data read/write control terminal R/W is "H", the data D output from the external data memory 3 is transferred to the command data switching signal terminal 1/W in the first half of the next operating machine cycle.
After being held in the data register 8, it is output to the data input/output terminal DATA. The captured data D is selected by the data path selection circuit 57 and output to the data bus 63.

When writing data to an external memory when the data read/write control terminal R/W is "L", data is externally transferred from the data bus 63 through the data path selection circuit 57, data input/output terminal DATA, and data register 8 at the same timing as when reading data. Write to data memory 3.

When only the external data space is used, the external command space use signal terminal EIM is set to 'L°, and the external data space use signal terminal EDM is set to "H". FIG. 4 is a system configuration diagram at that time, and FIG. 5 is an operation timing diagram when the system configuration shown in FIG. 4 is configured.

The address A held by the address register 54 is input to the address bus selection circuit 56 through the data address bus 62, and the address output terminal AD is inputted to the address output terminal AD in the second half of the operating machine cycle and the first half of the next operating machine cycle as shown in FIG.
Output to DR. When reading external memory using data read/write control terminal R/W, external data memory 3
The data D outputted from is outputted to the data input/output terminal DATA in the first half of the next operating machine cycle. The captured data D is selected by the data path selection circuit 57 and output to the data bus 63. When writing to the external memory, data is written to the external data memory 3 from the data bus 63 through the data path selection circuit 57 at the same timing as when reading.

Note that even when only the external command space is used, the external command space is accessed with the same system configuration as when only the external data space is used.

In this way, in this embodiment, the address output pin that sets the address of the instruction and data space and the data input/output bin that exchanges the instruction and data are shared, and the operating machine cycle is divided into two for instruction access and data access. By configuring the system to operate in a divided manner, it is possible to share external pins between the instruction space and the data space, while eliminating a drop in external memory access.

Moreover, there is an effect that one product type can be used instead of developing multiple products, such as those compatible with external memory and those compatible only with internal memory.

Furthermore, unlike the above embodiments, the selection of whether or not to switch buses is not made by an external signal, but as shown in FIG. As shown in FIG. 8, the switching may be performed using a bit set by a command of the semiconductor integrated circuit itself, and the same effect as in the above embodiment can be obtained.

This figure 7. The operation and configuration of the embodiment shown in FIG. 8 are almost the same as those shown in FIGS. 1 and 2, and the time chart is also the same as that shown in FIG. 3, so only the differences will be explained below.

In FIG. 7, 100 is an external instruction space control bit;
01 is an external data space control bit.

In the device shown in FIG. 7, when using both an external command space and an external data space, first, after resetting the chip of the digital signal processor 1, an instruction to control the external space is used to control the external command space control bit 7}100. and external digital space control bit 7} 101 are set to "H".Next, the instruction address IA of the program counter 51 is output to the instruction address bus 60.The subsequent operations are exactly the same as in FIG. Thereby, it is possible to control whether or not to select a bus based on its own command, without depending on an external command signal.

Also, in the embodiments shown in FIGS. 7 and 8, the embodiments shown in FIGS. It goes without saying that, like the embodiment shown in FIG. 2, only one of the external data space and the external command space can be used.

C. Effects of the Invention] As described above, according to the semiconductor integrated circuit of the present invention, in a semiconductor integrated circuit having a configuration in which the instruction space and data space are separated for speeding up, the external bin is separated into the instruction space and the data space. The number of bins can be reduced without compromising the speed of having separate instruction spaces and data spaces, with almost no drop in external memory access efficiency. .

Moreover, there is an effect that one product type can be used instead of developing multiple products, such as those compatible with external memory and those compatible only with internal memory.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is an internal block diagram of an embodiment of the present invention shown in FIG. 1, and FIG. 3 is a system configuration diagram of the system configuration of FIG. 1. Operation timing diagram; Figure 4 is a system configuration diagram when no external command space is used in the embodiment shown in Figure 1; Figure 5 is a timing diagram for the system configuration shown in Figure 4; Figure 6 is a conventional semiconductor integrated circuit diagram. A system configuration diagram using a circuit, FIG. 7 is an internal diagram of a conventional semiconductor integrated circuit. FIG. 8 is a system configuration diagram of a semiconductor integrated circuit according to another embodiment of the present invention, and FIG. 9 is an internal block diagram in FIG. 8. In the figure, l is a digital signal processing processor, 2 is an external instruction memory, 3 is an external data memory, 4 is a clock generator, 5.6 is an address register, 7.8 is a data register, 51 is a program counter, and 52 is an internal instruction memory, 53 instruction register, 54 address register, 5
5 is an internal data memory, 56 is an address bus selection circuit,
57 is a data bus selection circuit, 58 is a control circuit,
60 is an instruction address bus, 61 is an instruction bus, 62 is a data address bus, 63 is a data path, 100 is an external instruction space control bit, and 101 is an external data space control binoto. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) A first address bus that has different instruction spaces and data spaces, and that transfers addresses of the instruction space; a second address bus that transfers addresses of the data space; and instructions of the instruction space. a semiconductor integrated circuit having an instruction bus for transferring data, and a data bus for exchanging data in the data space, the semiconductor integrated circuit comprising: first selection means for selecting the first and second address buses; and the instruction bus and the data. A semiconductor integrated circuit comprising: second selection means for selecting a bus. (2) The first step for setting whether or not to use external command storage means.
and a second input terminal for setting whether or not to use an external data storage device, and the first and second selection means select according to the input values of the first and second input terminals. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit determines whether or not to perform the bus selection operation based on the bus selection operation. (3) A first control bit that controls whether or not to use an external instruction storage means by a command of the present semiconductor integrated circuit, and a second control bit that controls whether or not an external data storage device is used by a command of the present semiconductor integrated circuit. control bits, and the first and second selection means determine whether or not to select a bus depending on the values of the first and second control bits. The semiconductor integrated circuit described.