JPH03214346A - Inter-processor communication control method - Google Patents

Abstract

PURPOSE:To quickly execute the conversion of a CPU to off-line by sending back a reception stopping state response to a processor which transmits data without registering the data in a receiving data buffer by an inter-processor communication receiving part in the processor to be converted to off-line. CONSTITUTION:A stop notice of a communication state is executed to all other CPUs that are connected, and also, in the CPU 1 to be converted to off-line, '0' is written in the own processor communication state holding part by the own processor communication state rewriting part. In such a state, when a communication from the other CPU 2 is inputted, an inter-processor communica tion receiving part 130 sends back the receiving stopping state abnormality end to the CPU 2 of a communication destination, based on '0' of the own processor communication state holding part. Accordingly, the CPU 1 becomes a state that it does not receive a new communication from the other CPU 2. In such a way, the stop of an arbitrary CPU, or the detachment from the processing in the system can be executed quickly by a simple procedure.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a parallel processing system, a multiprocessor system, etc., in which a plurality of processors (hereinafter referred to as
Described as CPU; Central Process
It relates to the communication method between each CPU in a system that connects ng Units and performs a series of processing, and in particular,
The present invention relates to an inter-CPU communication control method suitable for dealing with situations such as when a U goes offline.

[Prior Art] There are various system configurations aimed at improving the processing performance and reliability of computer systems.

For example, one of them is a system configuration for parallel processing.

A computer that performs parallel processing has several to several hundred or more CPUs, and uses these many CPUs in parallel to process large amounts of data at the same time. Since the processing is executed without waiting for data that is ready for calculation, processing time can be shortened.

In parallel processing, the SIMD method (Single Tnstr) is used depending on the CPU arrangement and processing method.
ctionSjream Multiple Da
tasstream + single instruction, single data method) and M
TMD method (Multiple Instruct)
ionstrcam Multiple Da
tasstream (multi-instruction, multiple-data system).

In SIMD parallel processing, multiple CPUs synchronously execute multiple pieces of data based on the same command given from a central control device. Each CPU is connected by a connection network.

In MIMD parallel processing, each CPU works independently and asynchronously executes multiple pieces of data according to multiple different instructions. Each CPU has an internal control function to operate independently. Like the SIMD system, each CPU has a communication network for exchanging information.

In this way, in parallel processing, it becomes necessary to exchange information between CPUs while each CPU executes a process.

Regarding parallel processing, please refer to "Monthly Information Processing Examination 1".
PP of “April 989 Issue” (published by Japan SoftBank Publishing Division). 2 to 5.

Furthermore, there is a multiprocessor system as a system that uses a plurality of CPUs to improve processing performance.

Multiprocessor systems include tightly coupled multiprocessor systems in which multiple CPUs share a common main memory and channel, and tightly coupled multiprocessor systems in which multiple CPUs share a common main memory and channel, and
There is a loosely coupled multiprocessor system in which the CPUs are coupled together and the main memory is also independently connected to each CPU.

In a multiprocessor system, one of the CPUs
If the CPU fails, disconnect the failed CPU and
Processing continues using the remaining CPUs.

Connections between CPUs in a tightly coupled multiprocessor system include bus coupling and multi-board coupling, and in a loosely coupled multiprocessor system, communication between CPUs is also performed by channels.

For such multiprocessor systems, [
PP of “Passing Information Processing February 1989 Issue” (published by Gakken Co., Ltd.). 15-17.

A conventional example of an inter-processor communication method in a multiprocessor system will be described below.

FIG. 3 is a block diagram showing the internal configuration of a CPU related to inter-processor communication in a conventional multiprocessor system.

Although this example describes inter-processor communication between two CPUs, the same applies to inter-processor communication between three or more CPUs.

The CPU 31 and the CPU 32 have a communication path (SBUS in the figure) 33 for communicating with each other.

The CPU 3 1 includes a central control unit (MPU in the figure) 3 1 0 1 which performs the main control of the C:PU 3 1 itself, and a main memory (which stores programs that describe the operations of this central control unit 3101 and various data). MM in the figure) 3 1 1 0,
It is comprised of an inter-processor communication transmitter (SBLK in the figure) 3120 that performs a transmission operation for inter-processor communication, and an inter-processor communication receiver (RBLK in the figure) 3130 that performs a receive operation for inter-processor communication.

Although not shown, the CPU 32 also has exactly the same configuration as the CPU 31.

Central control unit 3101 and inter-processor communication transmitting unit 312
As a method for taking over communication data between O and the inter-processor communication receiving unit 3130,
0, or (u) placing registers in the inter-processor communication transmitter 3l20 and the inter-processor communication receiver 3130. This part is outside the scope of the present invention, and in this example, the method (ii) of placing registers in the inter-processor communication transmitter 3120 and the inter-processor communication receiver 3130 will be described.

The inter-processor communication transmission section 3120 is a transmission control section (CPKT in the figure) that assembles and transmits communication packets (CPKT in the figure).
SSCTL in the figure) 3 1 2 1, Transmission data buffer (SBUF in the figure) 3 that holds communication data to be transmitted
1 22, transmission write control unit (SWCTL in the figure) 3 that writes to this transmission data buffer 3122
It is made up of 123 pieces.

The inter-processor communication receiving unit 3130 receives a reception data buffer (RBUF in the figure) 3 1 3 2 that holds communication data in a received communication packet, receives the communication packet, writes it to the reception data buffer 3132, and sends a response. Consists of a reception write control unit (RWCTL in the diagram) 3 1 3 3 that transmits packets (APKT in the diagram) and a reception read control unit (RRCTL in the diagram) 3 1 3 1 that reads from the reception data buffer 3l32. has been done.

In one inter-processor communication from CPU 3 1 to CPU 32, CPU 3 1 sends a communication packet to communication channel 33.
is transferred to CPU32 via
32 ends by forwarding the response packet to CPIJ3l.

The contents of the response packet include normal termination and abnormal termination. If the communication packet is successfully written to the receive data buffer of CPIJ32 (corresponding to 3132 in CPU31), it is considered a normal end, and the write fails due to the receive data buffer of CPU32 being full, etc. If so, it will be terminated abnormally.

The transmission operation is first performed by the central control unit 3101 of the CPU 31.
This is accomplished by checking the status of the receiving side CPU 32, preparing transmission data and instructing the inter-processor communication transmitter 3120 to send it, and further assembling and transmitting a communication packet by the inter-processor communication transmitter 3120.

Confirmation of the communication status of the receiving CPU 32 by the sending CPU 31 is performed by the central control unit 3101 by referring to the processor communication status table (PCSTBL in the figure) 3111 on the main memory 3101. This processor communication status table 311
1 is a processor identification number column (PID in the figure) 3112 that identifies other CPUs connected to CPU 3 1;
A processor communication status column (PST in the figure) that stores the communication status of the corresponding CPU on the processor identification number column 3l12.
3113.

In the processor communication status column 3113, rQJ indicates a reception-stopped state, and "l" indicates a reception-enabled state.

The central control unit 3101 performs the transmission process if the processor communication status field 31l3 corresponding to the CPU of the communication partner is "1", and cancels the transmission process if it is "O". In FIG. 3, the processor communication status column 3l13 corresponding to the CPU 32 is "1", and the central control unit 31o1 performs a transmission process to the CPU 32.

Next, a case where the CPU 31 performs a receiving operation will be described.

In the reception operation, first, the inter-processor communication reception unit 3130 confirms whether reception is possible, and then the reception data buffer 3l
32 and transmission of a response packet, furthermore, the inter-processor communication receiving section 3130 reports the reception of the communication packet to the central control section 3101, and the central control section 3101 reads data from the inter-processor communication receiving section 3130. It is realized by

The reception write control unit 3133 confirms whether reception is possible or not by checking the availability of the reception data buffer 3l32. If there is no free space in the reception data buffer 3132, the reception write control unit 3l33
, for example, transfers an abnormal end response packet to the CPU 32 and ends the receiving operation. If there is space in the reception data buffer 3132 and reception is possible, the reception write control unit 3133 registers the data in the communication packet in the reception data buffer 3132 and continues the reception operation.

Next, for example, when stopping reception of inter-processor communication of the CPU 32, the CPU 32 sends a message to the processor communication status column 31 corresponding to the CPU 32 in the processor identification number column 3112 of the CPU 31.
A request is made to write rQJ to 13.

In the CPtJ31 that received the request, the central control unit 31o1 uses software to create the processor communication status table 3111.
Write to. The CPU 32 needs to perform this operation on all CPUs other than itself in the system.

Similarly, the suspension of reception is canceled by writing rlJ in the processor communication status column 3l13 corresponding to the CPU in question.

[Problems to be Solved by the Invention] In recent years, there has been an increasing demand for improvements in the processing power of computers, and systems that use a large number of CPUs to perform a series of processes have been realized. In these systems,
The technology for separating units due to failures of connected CPUs, etc. has become a problem. That is, in order not to degrade the processing performance of the entire system, it is necessary to quickly take the failed CPU offline.

For example, in a multiprocessor system, any C
There are cases where the PU is stopped or separated from the processing within the system and taken offline.

In this case, CP
Before taking U offline, all communications in this CPU's receive buffer must be processed.

If new communication is performed from another CPU during this processing period, the number of communications in the CPU's reception buffer increases, making it impossible to quickly stop the CPU and take it offline. Therefore, other C
It is necessary to immediately stop communication from the PU.

However, in the conventional inter-processor communication control method, there is a high possibility that communication with this CPU will occur during the period from when the reception stop notification is given until all the other CPIJs recognize the reception stop notification.

As a result, there is a problem in that the time it takes to stop the CPU is extended, making it impossible to quickly stop the CPU and take it offline.

An object of the present invention is to solve the problems of the prior art, and to easily stop any CPU or disconnect it from processing within the system in a computer system in which a plurality of CPUs are connected to perform a series of processing. It is an object of the present invention to provide an inter-processor communication method that can be implemented quickly without depending on the number of CPUs in the system or the state of the system bus, and improves the processing capacity of the system.

[Means for Solving the Problems] In order to achieve the above object, the inter-processor communication control method of the present invention provides a communication state maintenance function for each processor to maintain the state of whether or not to stop receiving data. and a self-processor communication state rewriting section that rewrites the contents of the own processor communication state holding section, and when an arbitrary processor of the computer system is taken offline, the own processor communication state rewriting section in the processor to be taken offline The processor rewrites the state held by its own processor communication state holding unit in the processor to a reception-stopped state that does not accept data reception, and causes the processor to go offline when receiving data transmitted from other processors in the computer system. The inter-processor communication receiving unit is characterized in that it does not register the data in the reception data buffer and returns a reception-stopping response to the processor that sent the data based on the reception-stopping state of its own processor communication state holding unit. .

[Operation] In the present invention, when a certain CPU is taken offline, in order to stop reception of inter-processor communication, the inter-processor communication receiving unit transfers the CPU to be taken offline to new communication from other CPUs. will not be accepted.

That is, according to the prior art, all other connected CPUs are notified of the termination of the communication state, and in the CPtJ to be taken offline, the own processor communication state rewriting unit writes rOJ to the own processor communication state holding unit.
Write.

In this state, when communication from another CPU is input, the inter-processor communication receiving unit returns a reception-stopping status abnormal end to the communication destination CPU based on rQJ of its own processor communication status holding unit.

In this way, this CPU'U enters a state in which it does not accept new communications from other CPUs.

In addition, it is possible to quickly stop any CPU or disconnect it from processing within the system using a simple procedure.

〔Example} Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows 6 CPUs related to the inter-processor communication method of the present invention.
3 is a flowchart showing an example of processing operation of FIG.

In this embodiment, a self-processor communication state flag (CSFLG) is used to hold the state of whether or not to stop the data reception operation, and this inter-processor communication state flag (CSFLG) is registered. In order to rewrite the contents, the flag control section (CSFCTL) is described as being provided within the inter-processor communication receiving section (RBLK).

C. When the PU stops reception of inter-processor communication (step 1o1), first, the central control unit (MPIJ) inside the CPU itself stops reception.
) instructs the flag control unit (CSFCTL) in the inter-processor communication reception unit (RBLK) to change to the reception stop state (step +02). Upon receiving this instruction, the flag control unit (CSFCTL) writes "O" to its own CPU communication status flag (CSFLG) (step 1
03). Furthermore, it notifies all CPUs other than itself, such as CPU 2, that the communication status has stopped (step 104).
, ends the process.

In this way, multiple CPUs that perform interprocessor communication
In a system consisting of
By providing the PU itself with a status display indicating that communication is stopped, there is no need to accept new communications from other CPUs. Therefore, the CPU is promptly taken offline.

FIG. 2 is a block diagram showing one embodiment of the internal configuration of a CPU that performs the processing operations shown in FIG. 1.

In this embodiment, the case where there are two CPUs will be described, but the same applies to the case where there are three or more CPUs.

Its configuration is almost the same as the conventional example shown in FIG.

The difference is that the inter-processor communication status table 31 in FIG.
11 is placed in the inter-processor communication transmitter 3120 instead of the main memory 311o, and the status flag according to the present invention is provided in the inter-processor communication receiver.

The purpose of moving the inter-processor communication status table 111 from the main memory 110 to the inter-processor communication transmitter 120 is to change its management from software to hardware and improve performance such as processing speed.

Further, in this embodiment, the status flag according to the present invention is used as a self-processor communication state holding unit that holds the state of whether or not to stop receiving data, and as a flag that changes the self-processor communication state flag. Control unit (CSFC in the figure)
TL) is provided in the inter-processor communication receiving section as a self-processor communication state rewriting section.

However, the configuration is not limited to this embodiment. For example, a method may be used in which the status flag according to the present invention is stored in the main memory and managed by software. In short, a self-processor communication state holding section that holds the state of whether or not to stop receiving data, and a self-processor communication state rewriting section that changes the holding state of this self-processor communication state holding section.
It is sufficient if it is controlled by the same PU.

Hereinafter, the internal configuration and operation of the CPU according to the present invention will be explained in detail based on FIG.

The CPU I and the CPU 2 have a communication path (SBUS in the figure) 3 for communicating with each other.

The CPUI includes a central control unit (MPU in the figure) 101 that performs main control in the CPU itself;
The main memory (MM in the figure) 110 stores programs that describe the operations of the processors and various data, and the interprocessor communication transmitting unit (SB in the figure
LK) 120, and an inter-processor communication receiving section (RBLK in the figure) 130 that performs a receiving operation for inter-processor communication.

Methods for passing communication data between the central control unit 101, the inter-processor communication transmitting unit +20, and the inter-processor communication receiving unit 130 include (i) a method of securing a buffer area on the main memory 110; and (ij) a method of securing a buffer area on the main memory 110; Possible methods include placing resistors in the inter-processor communication transmitter 120 and the inter-processor communication receiver 130. Since this part is not related to the present invention, in this embodiment, a method will be described assuming that a resistor is placed in the inter-processor communication transmitter 120 and the inter-processor communication receiver 130 (l1).

The inter-processor communication transmitting section +20 is a transmission control section (SS in the figure) that assembles and transmits a communication bucket (CPKT in the figure).
CTL) 1 2 1, a transmission data buffer (SBUF in the diagram) 122 that holds communication data to be transmitted, a transmission data write control unit (SWCTL in the diagram) 123 that writes to this transmission data buffer 122, are connected. It consists of a processor communication state management table (PCSTBL in the figure) l11 that holds the communication states of other CPUs, and a communication state control unit (SPCTL in the figure) 10 that changes this processor communication state management table 111.

The inter-processor communication receiving unit 130 has a receive data buffer (RBIJF in the figure) 1 3 2 that holds the communication data in the received communication packet, receives the communication packet, writes it to this receive data buffer 132, and writes the response packet. A reception write control unit (RWCTL in the diagram) 133 that transmits the data (APKT in the diagram), a reception data read control unit (RRCTL in the diagram) that reads data from the reception data buffer 132, and further, C
The own CPU communication state flag (CSFLG in the figure) 20 that maintains the communication state of the PUI itself, and the flag control unit (CSFLG in the figure) that changes the own CPLI communication state flag 20
TL) It is composed of 30.

For example, one inter-processor communication from CPUI to CPU2 ends when the CPUI transfers a communication packet to CPU2 via communication path 3, and in response, CPU2 transfers a response packet to CPUUI. .

The contents of the response packet include normal termination, abnormal termination with reception buffer full, and abnormal termination while reception is stopped. The communication packet is correctly stored in the reception data buffer (C
If the data can be written to the PUI reception data buffer 132 (corresponding to the PUI reception data buffer 132), it is considered to be a normal end. If the CPU 2 is in the process of stopping reception, it is determined that the process is abnormally terminated while the reception is stopped, and if writing fails due to the reception data buffer of the CPU 2 being full, etc., the process is determined to be abnormally terminated with the reception buffer full.

The transmission operation in the CPUI is performed by (i) the central control unit 101;
(ii) confirmation of the status of the receiving side CPU by the inter-processor communication transmitter 120, and (■) assembly of communication packets by the inter-processor communication transmitter 120. This is accomplished by sending.

In order to confirm the communication state of the receiving side CPU, the communication state control unit 10 refers to the processor communication state management table 111 based on a transmission instruction from the central control unit 101 to the inter-processor communication transmission unit l20. If the communication state of the receiving side CPU is confirmed to be capable of receiving, the inter-processor communication transmitting unit 120 continues the transmitting operation. Also, the receiving side CP
If the communication state of tJ is reception stopped, the inter-processor communication transmitting unit 120 ends the transmitting operation and notifies the central control unit 101 to that effect.

This processor communication state management table 111 has a processor identification number column (PI in the figure) that identifies each connected CPU.
D) 112 and a processor communication status column (PST in the figure) 113 that stores the communication status of the CPU corresponding to this processor identification number column 112.

In the processor communication status column 113, rQJ indicates a reception stopped state, and "1" indicates a reception enabled state.

The central control unit 101 performs the transmission process if the processor communication status field 213 corresponding to the CPU of the communication partner is r5, and cancels the transmission process if it is rOJ. In FIG. 2, processor communication status column 1 corresponding to CPU2
13 is "rl", and the central control unit 101 performs a transmission process to the CPU 2.

The reception operation in the CPUI is first to confirm whether reception is possible by the inter-processor communication receiving unit +30, then to register in the received data buffer 132 by the inter-processor communication receiving unit 130, and then to register the response packet by the inter-processor communication receiving unit 130. transmission, and reporting of reception of the communication packet from the inter-processor communication receiving unit 130 to the central control unit;
The reception by the central control unit (lot) is realized by reading data from the data bus sofa.

The reception capability is confirmed by (1) checking the free space in the reception data buffer +32 by the reception write control unit 133, and (1l) checking the own CPU communication status flag 20 by the reception write control unit 133 according to the present invention. It will be done.

In the confirmation operation of (1), if there is no free space in the reception data buffer [32], the reception write control unit 133 transfers a reception buffer full abnormal end response packet to the other party's CPU, for example, CPU2. .

In the confirmation operation (ij), if the own CPU communication status flag 20 is "0", the own CPU, here cpU1, is in the receiving stopped state, and the reception write control unit 133 detects the other CPU, e.g. A response packet indicating abnormal termination while reception is stopped is transferred to the CPU 2.

Upon checking whether reception is possible, if reception is possible, the reception write control unit 133 registers the data in the communication packet in the reception data buffer 132, and continues the reception operation.

When the CPU] performs a reception stop of inter-processor communication, the central control unit 101 instructs the flag control unit 30 in the inter-processor communication reception unit 130 to change to the reception stop state. Upon receiving this instruction, the flag control unit 30 writes rQJ to its own CPU communication state flag 20, and further notifies all CPUs other than itself, such as the CPU 2, of stopping the communication state. Then, in each CPU that has received this stop notification, the communication state control unit (communication state control unit 10 of the CPUI) in the interprocessor communication transmission unit (corresponding to the interprocessor communication transmission unit I20 of the CPUI) of each CPU
) receives the second notification, and CPU1 in the processor identification number field (corresponds to the processor identification number field 112 of the CPUI) in the processor communication state management table (corresponds to the communication state management table 111 of the CPUI) of each CPU. Write rOJ in the processor communication status field (corresponding to CPUI processor communication status 119113) corresponding to .

When the CPUI cancels reception of inter-processor communication, the central control unit 1. 0 1 to flag control unit 3
0 is instructed to change to a state in which reception is not possible. Upon receiving this instruction, the flag control section 30 writes "N" in the own CPU communication state flag 20, and further,
A communication state stop cancellation notification is sent to all CPUs other than CPLI1.

Then, in each CPU that receives this stop notification, the communication state control unit (corresponding to the communication state control unit IO of the CPUI) of each interprocessor communication transmission unit (corresponding to the interprocessor communication transmission unit 120 of the CPUI) sends this notification. is received, and the processor identification number column (CP
CPUI (corresponding to the processor identification number field 112 of the UI)
Write "1" in the processor communication status column (corresponding to the processor communication status column 113 of the CPUI) corresponding to the CPU.

As mentioned above, in this embodiment, the transmitting side, for example,
Although we have shown a method for managing the processor communication status management table 111 of the CPUI using hardware, if you do not need very high performance in terms of processing speed, etc., you can use the processor as in the conventional example shown in FIG. It is also possible to place the communication status management table 111 in the main memory 110 and use software.

As explained above, in this embodiment, when the CPUI is taken offline, in order to stop reception of inter-processor communication, the CPUI updates the communication status to all CPUs other than itself, such as CPU2. Along with giving a notice of suspension,
The CPU itself is placed in a state where it does not accept new communications from other CPUs.

That is, in CPtJl, from the central control unit 101 to the flag control unit 3 in the inter-processor communication reception unit +30.
An instruction is given to o to change to the receiving stopped state. Then, upon receiving this instruction, the flag control unit 30 controls the own CPU.
Write “O” to the communication status flag 20. As a result, CPMI enters a state in which it does not accept new communications from other CPBI, and can quickly go offline by terminating the communications it has been holding up to that point.

In this way, according to this embodiment, in a multiprocessor system, any CPU can be stopped or separated from the processing within the system using a simple procedure. Furthermore, it can be quickly implemented without depending on the number of processors in the system or the state of the system bus.

[Effect 1 of the invention According to the present invention, a plurality of C
In a system consisting of a PU, it is possible to quickly take the CPU offline, and the processing capacity of the system can be improved.

[Brief explanation of drawings]

FIG. 1 shows a CPIJ related to the inter-processor communication method of the present invention.
FIG. 2 is a block diagram showing an example of the internal configuration of a CPU that implements the processing operations shown in FIG. CP related to communication
FIG. 2 is a block diagram showing the internal configuration of U. l, 2: CPU, 3/Communication path (SBUS), I O:
Communication status control unit (SPCTL), 20: Own CPU communication status flag (CSFLG), 30 Flag control unit (CSF
CTL), 31, 32: CPU, 33: Communication path (SBU
S), 1 0 1: Central control unit (MPU), 1 10
: Main memory (MM), 1 1 1 : Processor communication status management table (PCSTBL), 1 1 2 Processor identification number [(PID), 1 1 3 : Processor communication status column (PST), 1 20 : Inter-processor communication transmission part (SBLK), l 2 1: Transmission control part (S
SCTL), l22. Sending data buffer (SBUF)
，! 2 3: Transmission data write control unit (SWCT
L), 130 inter-processor communication receiving unit (RBL
K), 1 3 1: Received data reading control unit (
RRCTL), l3 2 receive data buffer (RB
UF), 133 Reception write control unit (RWCTL)
, 3 1 0 1: Central control unit (~IPU), 3 1
1 0 Main memory (MM), 3 1 1 1 Processor communication status management table (PCSTBL), . 3 l12 Processor identification number column (PID), 3113 Processor communication status column (PST), 31 20 Inter-processor communication transmitter (SBLK), 3 1 2 1: Transmission control unit (
SSCTL), 31 fa (SBUF), 3 1 2 3 control unit (SWC
TL), 3 1 signal receiving unit (RBLK), 31 output control unit (RRCTL), buffer (RBL7F), 3 1 control unit (RWCTL). 22: Transmission data x: Transmission data writing 30: Processor communication 31: Reception data reading 3132: Reception data 33. Reception writing system

Claims (1)

[Claims] (1) Inter-processor communication transmitting means for transmitting data to any processor connected via a common transmission medium; and receiving data transmitted from any processor connected via the common transmission medium; Two or more processors each having an inter-processor communication receiving means that returns a data reception completion response to the processor that sent the data, and a reception data buffer that holds the received data are connected via the common transmission medium, and In an inter-processor communication control method for a computer system in which data is transmitted and received between processors via the common transmission medium and a series of processes are executed, each of the processors is provided with a state of whether or not to stop receiving data. It has own processor communication state holding means for holding it, and own processor communication state rewriting means for rewriting the contents of the own processor communication state holding means,
When taking any processor of the computer system offline, the self-processor communication state rewriting means in the processor to be taken offline accepts data reception to update the state held by the self-processor communication state holding means within the processor. When data transmitted from another processor of the computer system is received, the inter-processor communication receiving means in the processor to be taken offline changes to the receiving stopped state of the own processor communication state holding means. Based on the condition
An inter-processor communication control method, characterized in that the data is not registered in the received data buffer, and a reception stop response is returned to the processor that transmitted the data.