JPH03214492A - Multi-port memory - Google Patents

Abstract

PURPOSE:To delete a signal line for bypass at the outside of a memory cell array by transferring data from a port on one side to the port on the other side by selecting the same memory cell with two ports. CONSTITUTION:A both port same cell selection circuit 40 connected to word lines 21-24, 31-34 at port A and B sides and bit line selection signals 27, 28, 37, and 38 at port A and B sides of the memory cell array 10 is provided. In such configuration, both ports A and B select a memory cell 14 when a both port same cell selection signal is set at a high level, and the bit line 27 at the port A is connected to the bit line 37 at the port B. In such a way, it is possible to delete the signal line for bypass at the outside of the dual-port memory cell array 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to multi-port memories, and more particularly to multi-port memories that transfer data directly from one port to another.

[Conventional technology]

Conventionally, a bypass circuit has been used for this type of direct data transfer between multiple ports.

FIG. 3 is a block diagram showing an example of this dual port memory. This dual port 1 memory connects the A port side data line 6 to the dual port memory cell array 10.
A port side bit lines 27, 28 or bypass line 74
and a changeover switch 72 that connects the B port side data line 62 to the B port side bit line 37, 38 or bypass line 74 of the dual port memory cell array 10.

In this configuration, when the switching signal 73 is set to high level, the A port side data line 6] is connected to the B port side data line 62 through the pie bus line 74.

[Problem to be solved by the invention]

The above-described conventional multi-port memory has a horizontal structure that requires a bypass signal line 74 outside the memory cell array 10, and therefore has the disadvantage that an area for this bypass signal line is required.

An object of the present invention is to provide a multiport memory that can transfer data between both ports through memory cells in a memory cell array without requiring a bypass signal line.

[Means to solve the problem]

Alternatively, in a multi-port memory having a plurality of input/output ports 1 to 1 and having a function of directly outputting data from one port of these input/output ports to another port, the plurality of input/output ports A same memory cell selection circuit is provided for selecting the same memory cell for a port, the same memory cell is selected by a cell selection signal, and data is transferred from the one port to another port via this memory cell. It is characterized by the following.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention.

The memory array is simplified to a dual port memory cell array with a 4×2 configuration. The dual-board 1-memory cell array 10 includes memory cells 11 to 18 that are common to both ports A and B, and an A port that controls the gate of each memory cell.
Port side word lines 21 to 24, B port side word lines 31 to 34, A port side bit lines 27 and 28 that perform data input/output with the A port, and B port side bit line 37 that performs data input/output with the B port. .38, A port side bit selection signals 25 and 26 for selecting the bit line of the A port, and B port side bit line selection signals 35 and 36 for selecting the B port bit line.

In this embodiment, A and B baud 1 and 1 of the memory cell array 10 are
Both port same cell selection circuits 40 are connected to side word lines 21 to 24, 31 to 34 and A and B port side bit line selection signals 27, 28, 37, 38, and both port same cell selection signals 41 are set to high. When the level is set, memory cell 14 is selected for both ports A and B, and bit line 2 on the A port side is selected.
7 is connected to the B port side bit line 37.

FIG. 2 is a block diagram of a second embodiment of the invention. Word lines 21 to 2 of dual port memory cell array 10
4.31-34 and bit line selection signals 25.26, 35
．． A both-port same cell selection circuit 40a is connected to 36.

In this embodiment, one cell selection circuit 40a for both ports has one
Since it is equipped with a bit register 50 and can change the memory cell selected by the same cell selection signal 41 for both ports, it selects a memory cell whose data can be changed by 8 and selects it as a memory cell for data transfer. It has the advantage of being able to

For example, when the 1-bit register 50 is "1", the word line 24.34 becomes the word line for data transfer, and vice versa.
If bit register 50 is “O”, 23.3 before word
3 is a word line for data transfer.

〔Effect of the invention〕

As explained above, in the present invention, by selecting the same memory cell from both ports, data can be transferred from one port to the other port using the memory cell. This has the effect of eliminating bypass signal lines outside the cell array.

[Brief explanation of drawings]

1 and 2 are block diagrams of dual port memories showing first and second embodiments of the present invention, and FIG. 3 is a block diagram of an example of a conventional dual port memory having a data bypass function. . 10...Dual port memory cell array, 11-1
8...Memory cell, 21-24...A port side word line, 25.26...A port side bit line selection signal,
27.28...A port side bit line, 31-34...
・B port side word line, 35.36...B port side bit line selection signal, 37.38...B port side bit line, 40.40a...Both ports same cell selection circuit, 41
...Same cell selection signal for both ports, 50...1-bit register, 61...A port side data line, 62...
B port side theta wire, 71.72... changeover switch,
73...Switching signal, 74...Bypass line.

Claims (1)

[Claims] In a multi-port memory that has multiple input/output ports and has a function of directly outputting data from one of these input/output ports to another port, selecting the same memory cell for the multiple input/output ports. The multi-port is characterized in that the same memory cell is selected by a cell selection signal, and data is transferred from the one port to another port via the memory cell. memory.