JPH03214493A - Sense amplifier circuit and method for forming its source resistance - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Icheon Field of A'Xl) The present invention relates to a sense amplifier circuit for a memory device, particularly for a conductor dynamic RAM device.

[Successful technology]

A conventional sense amplifier circuit will be explained using FIG. 16. In FIG. 16, (1) is a sense amplification section,
arranged so as to be sandwiched between a pair of memory array sections (2),
It is composed of a plurality of NMOS type flip-flop and bus type sense amplifier circuits (5) connected to a focus line (4) having a coupling to each memory cell (3) of the memory array section (2). (6) is an NMO that constitutes the sense amplifier circuit (5)
The wiring resistance (7) of the voltage supply line connected to the common area of the S-type transistor pair is the power supply line (8) connected to the voltage supply line.
(9) is a sense amplifier circuit (
5) and the wiring resistance (8) directly connected to the common source node of the sense amplifier circuit (5) and the outer ii1 electric gap. The distance (t)'L from the supply waveguide to the sense amplifier circuit drive switch (7) is reduced by (9).

Normally, in a dynamic RAM circuit of C M O S J"!, not only the sense amplifier circuit of NMOS I'l'l but also the sense amplifier circuit of P M O S I';'l is connected to the bit line pair (4). These bit lines (4
) is affected by the amplification operation. However, in order to make the explanation clearer, the PMOS type sense amplifier circuit is intentionally omitted here.

Next, 1. The operation of the sense amplifier circuit described above will be explained with reference to the operating waveform diagram shown in FIG. 17 which also serves as a timing chart.

In I t”to, row address strobe, 1
When 5 words are manually input, the word lj (10) selected by the row address is 1'/. Chi1-garu. Then, the electric power f and the electric current f and ij (4) stored in the memory cell (3)
The focus line (4) produces a potential X of only 8 V due to the ++r distribution with the telegraph that was multiplied by ii.

II At t=to, the switch (7) connecting the voltage supply line connected to the common north region of the sense amplifier circuit (5) and the power supply line (8) is turned on.

Then, the difference in voltage {1'I of Bi7} wire pair (4) is equal to one Bi2
, becomes larger as the T line is amplified to the lower level side. The reason why the bit line is amplified to the high level side as indicated by the small dotted line in FIG.
This is because the sense amplifier circuit of O S rt> also operates. As shown in FIG. 16, when only the MOS type sense amplification circuit is operated, amplification toward the mm level side of the focus line is not performed, as shown by the solid line. The operation of the PMOS type sense amplifier circuit will not be explained here for the sake of space, but since it is the same as the NMOS type except that it amplifies the bit line to the high level side, which is the opposite of the NMOS type, the explanation will be omitted. .

[Problem to be solved by the invention]

By the way, with the increase in the degree of integration and density of Dynaminoku RAM, the chip area also increases, the wiring length of the 1U source line inside the chip also becomes longer, and the voltage drop due to wiring resistance tends to increase. Historically, each device's 1. There is a trend to lower the power supply voltage for reliability and lower power consumption.

For this reason, 1゛. The conventional configuration is like this power line (8)
When applied to a long circuit device with a long wiring J<, the effect of the voltage drop due to the wiring resistance (19) described above becomes even greater. In particular, when the sense amplifier circuit (5) is operating, which must not supply the most current, the supply voltage drops due to this voltage drop, and the amplification operating voltage of the sense amplifier circuit (5) decreases. Look at Chikanobu.

Next, the wiring resistance (6) of the power supply line 11 and the city fA:I line (
8) The process of inducing the amplification delay of the wiring resistance (9) and the sense amplifier circuit (5) is shown in Figure 18. ! (I will explain while IL.

In FIG. 18, the word line (10) is selected at t"to, and when the line γ is 1", the bit line to which the memory cell (3) connected to the word line (10) is connected is selected. (
-1i which had IQ written into memory sensor (3) in 4)
Also, corresponding to 't', there is a minute electric current {t/', and X is 7+'. Uru.

Basically, if OV or F is written into the memory cell (3), ΔVL will be /l, and the memory cell will have V,...,■
If 8 is entered, ΔVl+ (=V2−
■, ) occurs. Therefore, in reality, some of the F&1 bit lines (4) have a minute potential difference of -ΔVL, while others have a minute potential difference of ΔVl1.

In FIG. 18, among the bit lines (4) connected to the memory cell (3), (n
-I) The wooden bit line (4) has a minute potential difference of ΔV++, and only one bit line (4) has a minuscule potential of -ΔVL
The case where 1 occurs is minimized.

In this case, in order to drive the sense amplifier circuit (5), t
” When you turn on the switch (7) with L l, the first
As shown in Figure 6, the NMOS type sense amplifier circuit (5)
From that point on, the waveform of the source node of the pair of transistors curves toward 0 while sweeping out the current 4X:r stored in the floating capacitor iJ of the common source node.

At the 115 point of t=t2, the transistor of the sense amplifier circuit (5) is turned on, and the transistor connected to the common source node and the turned-on transistor is Bi,1.11l (4).
Since a plurality of are connected through the transistors,
The potential of the common source node a) "I" is the potential of multiple bits with large capacitance 111, l(4), that is, V1,.
For a moment, you will be drawn to it. At the time of 1=12, the transistor of the sense amplifier circuit (5) is turned on, and the
The bit line (4) connected to the sense amplifier circuit (5) that started the amplification starts amplification, but the bit line (4) connected to the sense amplifier circuit (5) whose transistor did not turn on at time 1=t2 , 1. Line (4) will not be amplified.

As shown in FIG. 18, the sense amplifier circuit (5) can start operating at time t=t+ only if the connected bit line (4) has a small voltage difference of ΔVll. , (n-1) sense amplification circuits (5) start amplification and amplify the connected bit lines (4) as shown in the figure. However, only one -Δ■16 microelectronic current (1'/
'． t'+ is /l. In the instant, the potential of the common source node attracted to the IS1 level side becomes Nr and V2.
Until it goes up, that is, t = t:+, there is no movement at all.
1 cannot be started.

Here, the common source node voltage (+'lV+) where (n-l) sense amplifier circuits (5) start operating, and the common source node v where one sense amplifier circuit starts operating
2 is a minute potential difference ΔVl+.

This phenomenon is the amplification J! of the sense amplifier circuit (5). J! Female cause. This delay time t=ta and 1 = 1 :+
The dynamic R can be shortened by -l engineering.
This is essential for the construction of an AM sense amplifier circuit.

1- The delay time τ mentioned above is determined by the wiring resistance (6) (9) mentioned earlier.
It is known that the wiring resistance (G) (9) becomes larger due to the increase in chip area in the future, and this problem will become even more serious.

The problem with 1.
Due to single integration and high density, the power supply current supplied to the sense amplifier circuit has increased due to the increase in chip size, and the wiring resistance has also tended to become thicker, making this problem even more serious.

The invention was made in view of the problems mentioned in item 1, and its eleventh object is to provide a sense amplifier circuit that can reduce the amplification delay of the bit line.

[R Stage for Solving the Problems] In order to achieve the 11th objective, the first configuration of the present invention is to provide a first configuration of the present invention, in which each of the plurality of bit lines connected to the memory cell is In the type sense amplifier circuit,
Each of the transistor pairs of the sense amplifier circuit is composed of a plurality of transistors connected in parallel, and each of the plurality of transistors connected in 16 columns is formed by a transistor having a different current driving ability. That is.

In the second structure of the invention, each of the transistor pairs of the sense amplifier circuit is composed of a plurality of parallel-connected MOS type transistors, and the parallel-connected MOSM:I
Each of the transistors has a different source voltage Cb"L.
1,'I is composed of transistors.

A third configuration of the present invention is characterized in that an additional capacitor 11 is connected to the power supply line 11 connected to the common source region of the transistor χ·1 of the sense amplifier circuit.

In a fourth configuration of the invention, the threshold voltage of the transistor pair of each sense amplifier circuit is set at the threshold voltage of the transistor pair on the side far from the location where the switch connecting the power supply line to the voltage supply line connected to the common source region is provided. The threshold voltage. It is characterized by being smaller than the one on the closer side.

In a fifth configuration of the present invention, the current driving capability of the transistor pair of each sense amplifier circuit is determined by the voltage supply line connected to the common source region on the side far from the location where the switch connecting the power supply line is provided. This device is characterized in that the driving capacity of the electric gate is made larger than that of the one on the nearby side.

A sixth configuration of the present invention is to oxidize each of the transistors constituting the transistor pairs of the plurality of sense amplifier circuits connected to each of the plurality of bit line pairs having a connection to the memory cell with a common source region. The transistor is formed in an activation region completely separated from the I1 conductive substrate by a film, and the substrate potential of each of the transistors is set to be different at a grounding point of the activation region. .

In a seventh configuration of the present invention, each of the transistors constituting the transistor pairs of the plurality of sense amplifier circuits connected with a common source region to each of the plurality of bit line pairs having a connection to the memory cell is formed using an oxide film. J. is formed in an activation region completely separated from the conductor substrate, and determines the substrate potential of the transistor. (It is characterized in that the plate potential supply section and the supply section for the electric potential of the common source region are shared.

In the eighth structure of the invention, a plurality of sense amplifier circuits, each of which has a common source region connected to each of a plurality of V7 line pairs that couple to a memory cell, are composed of CMOS II 7-lip float transistors. , one end of a plurality of sense amplifier circuits connected in the column direction with the source regions in common. Alternatively, the switch which connects the power line to the power line II supply line connected to the common source region of the J and P type MOS transistor pairs is connected to the N type MOS transistor pair. It is characterized by being provided at the end opposite to the switch.

A third configuration of the present invention is to reduce the threshold voltage of MOS transistors constituting a plurality of sense amplifier circuits whose source regions are connected in common to each of a plurality of bit line pairs having coupling to a memory cell. , 11-conductor memory chip I-
It is characterized in that the threshold voltage is set lower than the threshold voltage of MOS type transistors forming circuits other than the sense amplifier circuit formed in the circuit.

The method for forming a source resistor of the present invention is to connect the sources 6 and 6 of the MOS transistors connected in parallel in a Frison flop type sense amplifier circuit connected to each of a plurality of bit lines having connections to a memory cell to a 11 conductor. provided between two adjacent gate electrodes in the active region 1- of the substrate,
Perform a low-intensity injection on that area, then:
Add a sidewall oxide film to the above two gate electrodes to a very small extent? 't, then 1 culm source/drain height c
This is a method for forming a source resistor of a sense amplifier circuit, which is characterized by using a mask containing a J.

[For production]

According to the first configuration of the present invention, at the time of initial amplification, the common source node and the bit line are The coupling between the common source node and the bit line becomes weaker, and the common source node is no longer attracted to the precharge potential of the bit line. The amplified delay τ described above becomes smaller. 'ii After a period of time τ has elapsed, when the sense amplifier circuits connected to all the bit lines start initial amplification, the current drive capability of the transistor pairs connected in series is determined. ” can also be driven, so the amplification J! mentioned above can also be driven. Ll and τ can be made small, and the overall bit line amplification can also be made as low as I,L.

According to the second configuration of the present invention, in the initial amplification, one of the plurality of sense amplifier circuits that starts to move earlier than the others has its transistor pair itself
(The voltage drop is increased by l1 due to the resistor, and the voltage drop is increased by f1 in the +11. period.)
This acts as a force that suppresses the current driving ability of the transnostar pair that has started. This prevents the potential of the common source node from being greatly attracted to the potential of multiple bit lines, and prevents the sense amplifier circuit that starts operating the latest from being left behind and causing a large amplification delay. 11. can.

According to the third configuration of the present invention, by optimizing the capacitance value, the degree of attraction to the bit line potential can be reduced.
Since the amplification delay is reduced, the delay time required for all sense amplifier circuits using a common source node to reach a source node potential at which they can start amplification can be suppressed.

According to the fourth configuration of the present invention, the effect of voltage drop due to the wiring resistance of the voltage supply line connected to the common source node can be absorbed by the difference in threshold voltage. Compared to the amplification operation of the sense amplifier circuit, it is possible to prevent the amplification of the sense amplifier circuit arranged on the far side from being extremely delayed.

According to the fifth configuration of the invention, due to the influence of voltage drop due to the wiring resistance of the voltage supply line connected to the common source node, the amplifier driver or the sense amplifier driver, which is lagging behind, or the sense amplifier driver located on the far side. By increasing the current drive capability of the amplifier circuit by 1- and decreasing the current drive capability of the sense amplifier circuit on the nearer side, we can create the sense amplifier circuit with the fastest amplification operation f'+ and the sense amplification circuit with the slowest amplification operation. It is possible to reduce the difference in the amplification time of the circuit, and to suppress the effect of interference noise caused by the phenomenon in which the bit line with faster amplification is transferred to the bit line with slower amplification, as well as the problem of the above-mentioned dependent example. I can do it.

According to the sixth configuration of the present invention, each transistor pair of the sense amplifier circuit can be formed by not sharing a substrate with other transistor pairs, and the substrate potential can be changed to I.
It is one skill to set 4rL to 'llll+ depending on the placement location, and 1. than the well-based method described above;
Integration is IIJ's ability.

According to the seventh configuration of the present invention, when it is desired to set a substrate potential of 1 to the transistor pair h1, there is no need to separately provide a region for forming the substrate potential supply 11, and the layout curvature can be reduced. In addition, since the source electrode and substrate electrode of the transistor pair are common, even if the voltage drop due to the wiring resistance of the voltage supply line mentioned above is only 1%, it is in the area far from the sense amplifier driver. The potential difference between the plate and the source electrode of the pair of transistors arranged at becomes large, and the amplification J! ! ! A high-speed sense amplifier circuit with less fd can be realized.

According to the eighth configuration of the present invention, due to the voltage drop due to wiring resistance of the voltage supply line, the gate-source voltage 1 of the N-type sense amplifier circuit disposed on the side far from the switch.
1. If it is made so that the value does not become small, the amplification delay of the N-type sense amplifier circuit can be compensated for by the P-type sense amplifier circuit.

According to the ninth configuration of the invention, the threshold voltage of the transistor pair of the sense amplifier section can be set to be lower than the threshold voltage of the transistors used in the peripheral circuit and the memory cell section.

According to the method for forming a source resistor of the present invention, the layout area can be kept small, and the +Mi column connection with a transistor pair having a small current drive capacity can be made 1I.

〔Example〕

1 to 15 are circuit diagrams and operational waveform diagrams of a sense amplifier circuit according to an embodiment of the present invention. In addition, in the circuits of the respective embodiments shown in these figures, the parts that basically have the same configuration and moving numbers as the circuits of the conventional examples shown in FIGS. 16 and 17 are given common numbers. In order to avoid Ir1N, detailed explanation thereof will be omitted.

Example 1 FIG. 1 shows a sense amplifier circuit according to a first embodiment of the present invention.
1 (A) shows a "t. value" circuit, and FIG. 1 (B) shows a small shell-like layout.

In these figures, (I1) is a transistor pair with a large current drivability, and (+21) is a transistor pair with a small current drivability compared to transistor pair (11).

In this example, C is realized by changing the gate length of the MOS transistor/transistor to compensate for the difference in current drive capability of both 7(m(+2)).(13) is the common source of the large capacity transistor pair (11) The voltage supply line (+4) connected to the node is a voltage supply line connected to the common source node of the transistor pair (12) with the smaller current drive capability.

(15) is the gate electrode of the transistor pair and the bit line (
4), (IG)(+7)4;t
The common source node and the voltage supply line (+3Hl)
4), and (+8) is the contact connecting the drain electrode of the transistor pair and the above-mentioned V. This is a contact that connects to the 7-t wire (4).

According to the above configuration, first, in the initial amplification, if the transistor pair (+2)L with the smaller current drive capacity is not driven, as described in the conventional example, the common source node is connected to multiple transistors. Since there is no strong coupling between the focus line (4) and the transistor pair (12) with the smaller current drive capacity, the common source node is not attracted to the bit line potential to a large extent, and compared with the conventional example. The amplification delay time τ can be made small.

In addition, the amplification delay due to the small current drive ability of the transistor pair (12) performs initial amplification, and all bit lines (4) start amplification without being left behind, and the current drive ability is large. This problem can be solved by starting driving the other transistor pair (II) as well.

Historically, in this embodiment, since a MOS transistor with a small gate length is used in the initial amplification, it can be expected to have the effect of suppressing process variation in threshold voltage, which is the L cause of sensitivity deterioration.

■λ允子图2 and 3 show a sense amplifier circuit according to a second embodiment of the present invention. In the circuits shown in these figures, parts common to those of the circuit of the first embodiment are denoted by the same reference numerals, and detailed explanation thereof will be omitted to avoid duplication.

FIG. 2(A) shows an equivalent circuit, and FIG. 2(B) shows its detailed layout. In these figures, (2
1) is the source resistance of the MOSI-run star pair (12). This source resistance is formed in the activation region sandwiched between the gate electrodes of the transistor pair (I2), as shown in the layout diagram of FIG. 2(B). At this time, the source resistance (21) can be freely set depending on the interval between the gate electrodes.

Figure 3 (A) is an enlarged view of the group 81 in Figure 2 (B), and Figure 3 (B) is a cutaway view taken along cutting line ■1■ in Figure 3 (A). In these figures, especially when a large source resistance (2l) is required, a low resistance is applied to the active region sandwiched between the gate electrodes, which is the source region, as shown in FIG. 3(B). A sidewall oxide film (24) is formed on the gate electrode so that the source/drain height/rotation (23) is not performed even if the filtration (22) is performed.
), the high-intensity implantation (23) is masked in the source region, resulting in a relatively large source resistance (21).
can be obtained.

If the configuration of this embodiment is adopted, first, in the initial amplification, one of the plurality of sense amplifier circuits (5) connected to the plurality of bit lines (4), which starts the operation f1 earlier than the others. , that is, the common source node and the bit line (4
) through the transistor pair (12), the source resistance (
21) makes the electricity 11 fall l1 shi, its +,! In the period f
It acts in the direction of suppressing the current driving ability of the transnostar pair (!2) that started '+. For this reason, as explained in the first embodiment, the potential of the i1rl source node is not attracted to the potential of the plurality of bit lines (4), and is moved most slowly. The sense amplification circuit (5) that starts f'+ is left behind, resulting in a large amplification j! I!
You can prevent 11 points from inducing a spread.

Further, as a method for forming the source resistor (21), a second
When using the method shown in Figure (El) and Figures 3 (A) and (B), the layout area can also be kept small, and L
A large transistor pair (l l) with current drive capability (85 rows of connections becomes one transistor pair).

FIG. 4 shows a small sense amplifier circuit (5
) is a dynamic zero waveform diagram that also serves as a timing chart when driving.

Of the cascade-connected transistor pairs (II) (12) described in the first and second embodiments, the transistor pair (12) or the source resistor (2l) with the smaller current drive capability is connected. 1=1 for the other transistor pair. is driven by the I-th sense amplifier activation signal to perform initial amplification.
At t”t+, a pair of transistors (I
1) or the transistor pair to which the source resistor (21) is not connected is driven by the second sense amplifier activation signal.

According to such a driving method, high-speed bit line amplification can be achieved as described above in the sense amplifier circuit (5) of the eleventh second embodiment.

FIG. 5 is a circuit diagram of a sense amplification H path according to a third embodiment of the present invention. In this figure, (25) is a capacitor κ formed by a MOS transistor. This capacitor +,} (25) is connected to a voltage supply line connected to the common source node of the sense amplifier circuit (5) (5°). Here, the additive value of additive capacitance 1+t(25) is multiple bit lines (4)
It is a value of 1 ship that cannot be ignored compared to the 1 power capacity f + j (2G), that is, a value of approximately the number 1 to number + 'l' pF.

FIG. 6 is an operational waveform diagram of a common source node of a sense amplifier circuit in which capacitors 1 and t formed by MOS transistors are connected.

According to the configuration of this embodiment, as shown in FIG. 6, the capacity:
By optimizing the 1F value, the 4' induced by the focus line potential at time L=tr can be made smaller, and the amplification delay as described above becomes smaller. For example, if the capacitor IIC+, which has a larger old directivity, is connected to the voltage supply line, then the time t=to and 1+
Since the capacity of the voltage supply line is large between 1 and 1. The falling speed of the electric current is slower than when the capacitor 1sE C 2 with the smaller t value is connected, but when 1=1, the electric potential attracted to the potential of the bit line (4) is Therefore, the source node potential V= at which all the sense amplifier circuits (5H5') with a common source node can start operating.
The delay time to reach V2 is τ1 in the case of 1ij C + , and the delay time until reaching V2 is τ1, and the delay time is τ1 in the case of 1ij C + , and the delay time until V2 is reached is τ1, and the delay time is τ1 in the case of 1ij C + . In the case of , τ2 becomes τ2, and the difference Δτ can suppress the delay.

Next, the configuration of the additional capacitor 11k connected to the voltage supply line mentioned above will be described.

Figure 7 (A) shows the common source node at U and the gate, U.
The timing chart of the control voltage low potential of the pole (29 H30) and the difference between the common source node voltage and the gate electrode potential and the capacitance κ value of the capacitor fIt(25) are shown in FIG. 7(B). This is a graph that reduces the relationship.

The part surrounded by the broken line in FIG. 5 is the NMOS'? !
, P M Q are additional capacitors κ connected to the voltage supply lines (27) (2B) connected to the common source node of the S type transistor pair, respectively. In the illustrated example, the source and drain electrodes of the NMOS S-type transistor are connected to the electrode 1 in common.
The potential of each gate electrode (29H30) is shown in Fig. 7 (A).
At the start of the initial amplification, t=tll~1= so that /1<
1, and then change it after t: L +, [.

(If 1<1+, MOS as shown in Figure 7 (B))
The transistor capacity fat (25) is the maximum capacity jjt value C w
At t)tl, the MOS} transistor is turned off so as to have the minimum capacitance iI1 value Csin.

- On the other hand, FIG. 8(A) shows the portion surrounded by the broken line shown in FIG. 5, that is, the additional capacitors l, 1. Figure 8 (B) is a circuit diagram showing the horizontal construction of 1.
A timing chart in which the potential of the 1 supply line is set to tJ<, Fig. 8 (C) shows the relationship between the difference between the 1 supply line potential and the 6; is a small graph.

In FIG. 5, unlike the configuration in which 1<
P! The source and drain electrodes of the s P M O S type transistor pair are made common, and the ground line (power line) (8) and internal vt. . line (3!) and connect the respective gate electrodes to the voltage I1 supply line (27) (28).
Connect to each.

According to this configuration, by turning on the drive switch (7H7') of the sense amplifier circuit +]i+, the potentials of the power supply lines (27) and (28) change to 1 as shown in FIG. 8(B). ＜So, ・ノj is I. From G5V to 0.0■,
The other one is 1. It changes from G5V to 3.3V. As a result, as shown in FIG. 8(C), 1 {as shown in FIG. ,I:
(25°) is naturally the maximum human size i+1- 1nl Cm
This is to convert a x to the minimum value Cain.

1, M O S '. shown in FIGS. 5 and 8. Additional feature: With feature 1, the potential of the common source node is not greatly attracted to the potential of the plurality of bit lines (4) at the stage of the initial amplification described above, and the delay caused by this is suppressed. In addition, the capacity 1 of the additionally provided common source node
11 is also configured to become smaller after the initial amplification, as described above, so it is possible to suppress the influence of the delay due to the additional capacity I1 of the common source node to a small level.

FIG. 9 is a block diagram of a sense amplifier circuit according to a fourth embodiment of the present invention. Note that the circuit diagram of the transistor level of the sense amplifier circuit in FIG. 9 is the same as the conventional example shown in FIG. 16 and the embodiment shown in FIG. 5. The phase 11' of the memory array section (2), sense amplifier section (1), and sense amplifier driver (32) in the semiconductor memory chip 1- is omitted. Only the positional relationship is small.

In FIG. 9, yth, is the threshold voltage of the sense amplifier transistor pair in the sense amplifier array l as a sense amplifier circuit, and vth2 is the threshold voltage of the sense amplifier transistor pair in the sense amplifier array 2 as a sense amplifier circuit. Voltage, Vth: + is the threshold voltage of the sense amplifier transistor pair in the sense amplifier array 3 as a sense amplifier circuit, Vth4 is the threshold voltage 1h of the sense amplifier transistor pair in the sense amplifier array 4 as a sense amplifier circuit l1 Teatte, l Vth41 > l V
th:+l>lvth2+>lVthl
It is 1.

Approximately 1000 to 2000 sense amplifier circuits (5H5') each connected to a plurality of bit lines (4) are connected with a common source node, and are simultaneously activated by a sense amplifier driver (32).

The fourth embodiment of the present invention has a plurality of sense amplifier circuits (5).
The threshold voltage of the MOS type transistor pair constituting (5') is set to be high for those placed in the area close to the sense amplifier driver <<32>>, and set to be low for those placed in the far area. be.

According to the configuration of this embodiment, the common source node l'
Since the effect of voltage drop due to the wiring resistance (6) of the supply line connected to the power supply line 11, that is, the effect of a decrease in the voltage between the gate and source nodes of the transistor pair, can be absorbed by the difference in threshold voltage. Near the sense amplifier driver (32)
It is possible to prevent the amplification of the sense amplifier circuit placed on the far side from being extremely delayed compared to the amplification operation of the sense amplifier circuit placed on the far side. In addition, the threshold voltage setting is 1. It can be easily set by controlling .

ffi Example 1 FIG. 10 is a block diagram showing a sense amplifier circuit according to a fifth embodiment of the present invention. Note that FIG. 10 is similar to FIG. 9, and the transistor level circuit diagram of the sense amplifier circuit is the same as that shown in the conventional example shown in FIG. 16 and the embodiment shown in FIG. Therefore, the phase I of the memory array section (2), sense amplifier section (I), and sense amplifier driver (32) in the 11-conductor memory chip-1 will be omitted.
l: Only about positional relationships.

In FIG. 1O, L+ is the gate length of the sense amplifier transistor pair in sense amplifier array l, L2 is the gate length of the sense amplifier transistor pair in sense amplifier array 2, and L:I is the sense amplifier transistor in sense amplifier array 3. The gate length of the pair, L4, is the gate IQ of the sense amplifier transnoster pair in the sense amplifier array 4, and L4>L:+>L2>L+.

In this embodiment, the gate lengths of the MOS transistor pairs constituting the plurality of sense amplifier circuits (5) (5°) are set to 1<> for those arranged nearer to the sense amplifier driver (32), By setting shorter distances for those located in farthest areas, the current driving ability can be increased for those located far away, and the current driving ability can be decreased for those located close to each other.

According to the configuration of this embodiment, the effect of the voltage drop due to the wiring resistance (6) of the voltage supply line connected to the source node, that is, the effect of the decrease in the distance between the gate and source nodes of the transistor pair, is , the Senos amplifier driver (32) with an excellent amplification frequency increases the current drive capacity of the sense amplifier circuit placed on the far side by 1, and conversely increases the current drive capacity of the sense amplifier circuit on the near side by 16C. In addition, it is possible to reduce the difference in amplification time between the sense amplifier circuit with the fastest amplification speed and the sense amplifier circuit with the slowest amplification speed r+.

Therefore, it is possible to suppress the influence of interference noise caused by this phenomenon that is applied to the bit line where the amplification is fast or the bit line where the amplification is slow, and the problems of the conventional example described above.

FIG. 3 is a block diagram of a sense amplifier circuit according to a sixth embodiment of the present invention. Note that Figure 11 is similar to Figures 9 and 10.
Similarly to the figure, the transistor level circuit diagram of the sense amplifier circuit is omitted because it is the same as the conventional example shown in Fig. 16 and the small embodiment shown in Fig. 5. , phase I+' of the memory array section (2), sense amplifier section (1), and sense amplifier driver (32) in block 1-. Only for the 4r't positional relationship, 1<.

In FIG. 11, VBB+ is the sense amplifier array l
The board voltage inside ゜f. s VBB2 is the board voltage 1:t in the sense amplifier array 2, V RB :l is the substrate potential in the senos amplifier array 3, and VBB4 is the j+l voltage (i'rtea'c) in the sense amplifier array 4. ,IVBB4
1 > l VBD: l l > l VBsz
l > l Vae+ l.

In this embodiment, MOS type transistor pairs forming the plurality of sense amplification H paths (5) (5') are formed. 1
lv: The substrate potential of the switching region is set by the sense amplifier driver (3
2) It is set so that the absolute value of the potential difference between the substrate and the source becomes thicker as the area is closer to 2), and the absolute value of the potential difference between the substrate and the source becomes smaller as the area is further away.

According to the configuration of this embodiment, as clarified in the fourth embodiment, the threshold voltage of the transistor pair is higher when the transistor pair is disposed closer to the sense amplifier driver (32), and In this case, the threshold voltage I1 becomes smaller, so it can be expected that the same drop as in the fourth embodiment will occur.

In order to separately estimate the substrate voltage {1゜l for each sense amplifier array part as in this embodiment, it is possible to realize this by configuring the sense amplifier circuits in separate wells. An invention that achieves this in a different way will be described.

FIG. 12 shows a reduced size of the wedge portion when forming the sense amplifier circuit of the sixth embodiment, and FIG. 12(A) is an enlarged cross-sectional view.
FIG. 12(B) is a 1' side view of the same.

I love these pictures! ! ({ L, To describe an example of the method of forming the sense amplifier circuit of the sixth embodiment, {1
1 conductor substrate 1.. The plate 1 is selectively etched by ion etching. A trench is formed in the trench, and then the inside of the trench is oxidized particularly strongly in the deep part of the substrate, and the oxide film is oxidized to the extent that it comes into contact with the oxidized part in the adjacent trench. Using a process technique in which the oxide film (33) completely separates the region from the conductive substrate by the oxide film (33), each pair of transistors of the sense amplifier circuit is prevented from sharing a substrate with another pair of transistors. It can be formed by
1- than the well-based method described above.
+'+i integration is one manpower.

Next, another example of a method for forming a sense amplifier circuit using the above-mentioned complete isolation technique will be described.

In FIG. 12, (34) (F5) is a power supply line 11 connected to the common source node of the sense amplifier circuit. (34H35) and the different number -3 are used to reduce the fact that the sense amplifier circuit is arranged using a voltage supply line with a high voltage as described above.

(36) is a contact between the common source node and the power supply line 11. (37) connects the common source node to the voltage supply line (34H), which is the key point of this embodiment.
35), and in history, the conductor substrate is an oxide film (33)
This contact connects the region (38) completely separated by the substrate potential supply II. This Pj/min is the contact part mentioned above, and at the same time, the same area (37)
The mask 1) also serves as the former 1 part for carrying out 71 ions of the same conductivity Q+l as the area (38).

According to the configuration of this embodiment, as in the example of the above-mentioned formation method, when it is desired to set the plate electrode 41'I of W for each transistor pair, a separate area for forming the substrate potential supply 11 is provided. There is no need for it, and the layout area is small.

Also, as a big advantage in history, since the source electrode part and the substrate electrode part of the transistor pair are common, even if a voltage drop occurs due to the wiring resistance (6) of the power supply line 11 mentioned above, As a result, the sense amplifier driver (3
2) The potential difference between the substrate and source electrodes of a transistor pair placed in a region far from the region becomes large. In other words, it is possible to avoid the problem that the threshold voltage becomes undesirable due to the influence of the substrate bias effect. Therefore, amplify j! It is possible to realize a high-frequency sense amplifier circuit with less tM.

111J Example 1 FIG. 13 is a small circuit diagram of a sense amplifier circuit according to a seventh embodiment of the invention. In addition, since FIG. 13 is basically the same as the smaller conventional example shown in FIG. 16 and the embodiment shown in FIG. Further explanation will be omitted.

The key point of this embodiment is the sense amplifier driver (32) as shown in FIGS. 9 to 11. Rather than placing it only at one end or the other end of the sense amplifier section (1) consisting of SJ number of sense amplifier circuits,
The sense amplifier drive switch (7) that activates the N-type sense amplifier circuit (5) to V1 is connected to the sense amplifier drive switch (7) that activates the P-type sense amplifier circuit (5).
The holes (7') are arranged at one end of each.

According to the configuration of this embodiment, for example, N
If the gate-source voltage of the sense amplifier circuit of N Ifll, which is located on the fast side from the sense amplifier drive switch (7) of 71, becomes small, NJ'i'! The amplification delay of the sense amplifier circuit can be compensated for by the P-type sense amplifier circuit.

If such a configuration is adopted and the current drive capability of the N-type sense amplifier circuit and the current drive capability of the P-type sense amplifier circuit are made equal, the sense amplifier circuit placed at one end of the first section will also be placed at the other end. The sense amplification circuits that have been activated can also amplify the bit line at the same speed, so the variation between the sense amplification of 1000 to 2000 sense amplification circuits that are activated at the same time will be small, and the amplification will be as fast as the previous one. 1 crosstalk from the bit line being amplified to the bit line being amplified with a delay
The only thing that can be done is to keep the impact of noise to a minimum.

FIG. 14 is a block diagram of a sense amplifier circuit according to an eighth embodiment of the invention. What is shown in Fig. 14 is a memory chip including a sense amplifier section (1), a memory cell section (2), a part of a row decoder (39), and other peripheral circuits (40). The transistor level circuit diagram is basically the same as the conventional example shown in FIG. 16 and the embodiment shown in FIG. Detailed explanation will be omitted.

The key point of the present invention is that, as shown in FIG. (40) and the threshold voltage II of the transistor used in the memory cell section (2) VtPH, V
It is to be set smaller than tM.

FIG. 15 is an operational waveform diagram of the bit line (4) in this embodiment. As shown in this figure, as the power supply voltage of the sense amplifier circuit decreases, the operation of the transistors in the sense amplifier circuit becomes more and more affected by the threshold voltage ++vth (!!) in the invisible region. .

In addition, in FIG. 15, the current driving power of the sense amplifier circuit is W ISA father 11n COX (VBL-S -vth)
2L (Ill,, VBL-S: Common source potential vth:
Threshold voltage W of the sense amplifier circuit: Channel width L of the sense amplifier circuit: Channel length μ, l of the sense amplifier circuit: Movement 1 floor Cox of the sense amplifier circuit: Gate oxide film volume III of the sense amplifier circuit
SA: Drive current of the sense amplifier circuit.

Further, l Vth:4+ < l Vth, l, yth,, is a threshold voltage j1 lower than that of the peripheral circuit (40), and Vth+ is a threshold voltage l1 that is the same as that of the peripheral circuit (40).

IBM bit l) R A M or 64M bit l) R
At AM, the power supply voltage 11 also becomes 3.3V, and l/
When using the 2 Vn/sense h formula, the sense amplifier circuit changes the gate-source voltage to I. G5
It can be seen that when the threshold voltage is set to 0.7 V or 0.8 V, the current drive capability of the sense amplifier circuit during operation is greatly influenced by the threshold value U. In order to improve the current drive ability, the threshold voltage should be set to 0.
It is preferable to reduce the voltage to around 0V.

・Since the transistor in the Noha cell part affects the retention characteristics of the memory cell, it is impossible to lower the threshold voltage, and it is preferable to significantly lower the threshold voltage of the peripheral circuits in order to reduce the standby current. do not have.

However, the transistor pair (5
) (5°), the source potential can be freely varied by 1■
Therefore, the threshold voltage I1- can be set to ~0. By controlling the source potential even if it is set near OV, transistor 2
Canting off J(5)(5') is one function. 1. From the above, it can be seen that only the threshold voltage V tSA of the transistor pair (5) (5') in the sense amplifier circuit section, and the threshold voltage V tSA of the other peripheral circuits II: V tP}l and Memo J
u can be made smaller than the cell threshold 4ni voltage VtM
In J-Noh, the effect is great.

〔Effect of the invention〕

1 - As explained above, according to the first configuration of the present invention,
During initial amplification, since the transistor pair with the smaller current drive capability is used among the transistor pairs connected in parallel, the coupling between the eight source node and the bit line becomes weak, and the common source node 1. The bit line is not attracted to the precharge potential. With the amplification ha mentioned above, it becomes small. After the delay time τ has elapsed, when the sense amplifier circuits connected to all the bit lines start initial amplification, the transistor pair with the larger current drive capacity among the parallel-connected transistor pairs also Since the bit line can be driven, the amplification delay τ mentioned in 1. can be made small, and the overall bit line amplification can be made faster.

According to the second configuration of the present invention, in the initial amplification, one of the plurality of sense amplifier circuits that starts operating more slowly than the others reduces the voltage drop due to the source resistance of the transistor pair itself. It acts in the direction of suppressing the current driving ability of the transistor pair that started operating in the first period. Therefore, the potential of the common source node is not greatly attracted to the potential of multiple Bino wires, and the sense amplifier circuit that starts operating the latest is left behind, inducing a large amplification MM. You can prevent +1-.

According to the third configuration of the present invention, by optimizing the capacitance IIt value, the degree of attraction to the bit line potential can be reduced, and the amplification delay can be reduced, so that all sense amplifiers with a common source node The delay time required for the circuit to reach the source node potential at which it can start operating can be suppressed.

According to the fourth configuration of the present invention, the effect of voltage drop due to the wiring resistance of the voltage supply line connected to the common source node can be absorbed by the difference in threshold voltage. It is possible to prevent the amplification of the sense amplifier circuit disposed on the far side from being extremely delayed compared to the amplification delay of the sense amplifier circuit located on the far side.

According to the fifth configuration of the present invention, due to the influence of voltage drop due to wiring resistance of the voltage supply line connected to the common source/single node,
The current drive capacity of the sense amplifier circuit, in which the sense amplifier driver whose amplification operation tends to be delayed, is placed on the far side is 1. Ge,
On the other hand, by increasing the current drive capability of the sense amplifier circuit on the near side by 1, the difference in amplification time between the sense amplifier circuit with the fastest amplification frequency f1 and the sense amplifier circuit with the slowest amplification frequency f1 described above can be reduced. This makes it possible to suppress the effects of interference noise caused by the phenomenon in which a bit line with faster amplification crosses a bit line with slower amplification, and the problems described above in the prior art.

According to the sixth configuration of the present invention, each transistor pair of the sense amplifier circuit is connected to another transistor pair. ! : J. (
It can be formed by not using a common plate, and it is possible to set the substrate potential at a ratio of 1:1 depending on the placement location. or 1 ability.

According to the seventh structure of the invention, when it is desired to set different substrate potentials for the transistor pair i, there is no need to separately remove a region for forming the substrate potential supply 11, and the layout area is small. It's over. In addition, since the source electrode and plate electrode of the transistor pair are common, even if the voltage drop due to the wiring resistance of the voltage supply line mentioned above occurs, it is far away from the sense amplifier driver. The potential difference between the substrate and source electrodes of the transistor pairs arranged in the region becomes large, and a high-speed sense amplification H path with little amplification delay can be realized.

According to the eighth configuration of the present invention, N'? is placed on the side far from the switch because of the voltage drop due to the wiring resistance of the voltage supply line. If the gate-source voltage of the sense amplifier circuit PI is prevented from becoming small, the amplification delay of the sense amplifier circuit N'F can be captured by the sense amplifier circuit PIfl.

According to the ninth configuration of the present invention, the threshold voltage of the transistor pair of the sense amplifier section can be set lower than the threshold voltage of the transistors used in the peripheral circuit and the memory cell section.

According to the method for forming a source resistor of the present invention, the layout area can be kept small, and the IC column connection with a transistor pair with a small current drive capacity can be made 1f.

1 In summary, when using the sense amplifier circuit according to the invention, the fastest amplification operation is achieved in the amplification operation f1 of the transistor pairs of 1000 to 2000 sense amplifier circuits whose source electrodes are commonly connected. The time difference between the pair of transistors that performs the amplification operation and the pair of transistors that perform the amplification operation at the latest time can be reduced, so that high-speed readout as a memory is possible. It is possible to reduce the influence of interference noise on the transistor pair in which a slow amplification operation is performed from the transistor pair, and this has a great practical effect.

[Brief explanation of drawings]

FIG. 1 shows a small scale sense amplifier circuit according to the first embodiment of the present invention, FIG. 1(A) is an equivalent circuit diagram, FIG. 1(B) is a shell layout diagram thereof, FIG. Figure 3 is the second wooden invention.
The sense amplifier circuit according to the embodiment is made smaller, and FIG. 2 (^) is an equivalent circuit diagram, and FIG. 2 (B) is a shell-shaped layout diagram thereof.
Figure 3 (^) is an enlarged view of Figure 2 (B), Figure 3 (
B) is a diagram along the υ cut line III-III in FIG. 3(A), and FIG. 4 is an operating waveform that also serves as a timing chart when driving the sense amplifier circuit, which is smaller than the first and second embodiments. 5 is a circuit diagram of a sense amplifier circuit according to a third embodiment of the invention, FIG. 6 is an operation waveform diagram of a common source node of a sense amplifier circuit connected to a capacitor formed by a MOS transistor, and FIG. Figure 7 (A) is a timing chart of the voltage of the common source node and the potential of the control voltage of the gate electrode, and Figure 7 (B) is the difference between the common source node potential and the gate electrode potential, and the timing chart of the voltage of the control voltage of the gate electrode. Figure 8 (A) is a circuit diagram showing the structure of the part surrounded by the broken line shown in Figure 5. Figure 8 (B) shows the relationship between the voltage supply line potential and The timing chart shown in FIG. 8 (C) is 1! Difference between supply line potential and power supply potential and capacity +,} (25) capacity: l
(The relationship with the value is shown in a small graph. Figure 9 is a block diagram of a sense amplifier circuit according to the fourth embodiment of the present invention. Figure 1θ is a diagram of the sense amplifier circuit according to a fifth embodiment of the present invention. A horizontal drawing,
FIG. 11 is a block diagram of a sense amplifier circuit according to a sixth embodiment of the present invention, and FIG. 12 is a diagram of the structure of a sense amplifier circuit according to a sixth embodiment, and FIG. 12(B) is an enlarged sectional view, FIG. 13 is a small circuit diagram of the sense amplifier circuit according to the seventh embodiment of the present invention, and FIG.
FIG. 4 is a schematic diagram of a sense amplifier circuit according to an eighth embodiment of the present invention, and FIG. 15 is a diagram of operating waveforms of the bit line in the same embodiment. Figure 16 shows a conventional sense amplifier circuit. Figure 16 is a circuit diagram of a smaller version of the sense amplifier circuit as a follow-up example. Figure 17 is an operating waveform diagram that also serves as a timing chart for the same circuit. Figure 18 shows bit lines, word lines, and transistors. This is a diagram showing a timing chart of a pair of common source nodes. (3)...Memory cell, (4)...Bit line, (5
)(5')...Sense amplifier circuit, (7)(7')...
・Power 6 to power 11 supply line; (switch to connect line, (I)
1) (+2)...Transistor pairs connected in 11 columns, (13HI4)...Power j1 supply line, (16) (17
)... common source region, (21)... source resistance,
(25)...Additional capacity: l1. Figure 3 (A) ■ m Figure 3 (B) I/L ion implantation (J: 7lg people Figure 4 Figure 6 Figure 8 (C) Absolute value of (Electricity l! supply! II127.28 electric power) (Electric IQ city (1 冫) Figure 9 Figure 10〆Memory cell array Figure 11 Figure 13 Figure 9 Figure 15

Claims (1)

[Claims] 1. In a sense amplifier circuit such as a flip-flop or the like connected to each of a plurality of bit lines having coupling to a memory cell, each transistor pair of the sense amplifier circuit is formed by a plurality of parallel-connected transistors. 1. A sense amplifier circuit comprising: a plurality of transistors connected in parallel, each comprising transistors having different current driving capabilities. 2. The sense amplifier circuit according to claim 1, wherein the plurality of parallel-connected transistors are each composed of MOS type transistors having different gate lengths. 3. For each pair of transistors in a sense amplifier circuit configured by parallel connection of MOS transistors having different gate lengths, a common source region is provided independently for each pair of MOS transistors having the same gate length, and the transistor pair with the larger gate length is 3. A sense amplifier circuit according to claim 2, wherein a voltage supply source is connected to the common source regions of the transistor pair before the smaller common source region. 4. In a flip-flop type sense amplifier circuit connected to each of a plurality of bit lines having a connection to a memory cell, each transistor pair of the sense amplifier circuit is configured with a plurality of parallel-connected MOS type transistors, A sense amplifier circuit characterized in that each of the MOS transistors connected in parallel is composed of MOS transistors having different source resistances. 5. Connect the source regions of the parallel-connected MOS transistors in the flip-flop sense amplifier circuit connected to each of the plurality of bit lines coupled to the memory cell to two adjacent gate electrodes on the active region of the semiconductor substrate. A sidewall oxide film is deposited on the two gate electrodes to the extent that they overlap with each other, and is used as a mask for the high concentration source/drain implantation in the next step. A method for forming the source resistor of a sense amplifier circuit. 6. Each pair of transistors in a sense amplifier circuit configured by parallel connection of MOS transistors having different source resistances is provided with a common source region independently like a pair of MOS transistors having the same source resistance, and the one with the larger source resistance is 6. The method of forming a source resistor of a sense amplifier circuit according to claim 5, wherein a voltage supply line is connected to the common source region of the transistor pair before the common source region of the smaller transistor pair. 7. In a flip-flop type sense amplifier circuit connected to each of a plurality of bit lines having a connection to a memory cell, an additional capacitor is connected to a voltage supply line connected to a common source region of a transistor pair of the sense amplifier circuit. A sense amplification circuit characterized by: 8 Connect the source electrode and drain electrode of the MOS transistor in common, connect the common connection part to the voltage supply line connected to the common source region of the transistor pair of the sense amplifier circuit, and connect the gate electrode of the MOS transistor During the initial operation of the sense amplifier circuit, the potential is
8. The sense amplifier circuit according to claim 7, wherein the potential of the gate electrode is set to such a potential that the S-type transistor is turned on, and then the potential of the gate electrode is changed to a potential that causes the MOS-type transistor to be cut off. 9 The source electrode and drain electrode of the NMOS transistor are commonly connected to a first power supply, and the gate electrode of the NMOS transistor is connected to a voltage supply line connected to a common source region of the NMOS transistor pair of the sense amplifier circuit. Similarly, the source electrode and drain electrode of the PMOS transistor are commonly connected to the second electric wire, and the PMOS transistor
Connect the gate electrode of the S-type transistor to the P terminal of the sense amplifier circuit.
9. The sense amplifier circuit according to claim 8, wherein the sense amplifier circuit is connected to a voltage supply line connected to a common source region of the MOS type transistor pair. 10 In a plurality of sense amplifier circuits having a common source region connected to each of a plurality of bit lines having a connection to a memory cell, the threshold voltage of the transistor pair of each sense amplifier circuit is connected to the common source region. The sense amplifier circuit is characterized in that the threshold voltage on the side far from the place where the switch connecting the power supply line to the voltage supply line is provided is smaller than that on the side close to the place where the switch is provided. 11 In a plurality of sense amplifier circuits connected to each of a plurality of bit line pairs having a connection to a memory cell with a common source region, the current driving capability of the transistor pair of each sense amplifier circuit is The sense amplifier circuit is characterized in that the current drive capacity of the voltage supply line on the side far from the place where the switch for connecting the power supply line is provided is greater than that on the side closer to the voltage supply line. 12 Each of the transistors constituting the transistor pairs of the plurality of sense amplifier circuits connected to each of the plurality of bit line pairs having a connection to the memory cell with a common source region is completely separated from the semiconductor substrate by an oxide film. 1. A sense amplifier circuit, characterized in that the sense amplifier circuit is formed in a plurality of activated regions, and the substrate potential of each of the transistors is set to be different depending on the location of the activation region. 13 Each of the transistors constituting a transistor pair of a plurality of sense amplifier circuits connected with a common source region to each of a plurality of bit line pairs having a connection to a memory cell is completely separated from the semiconductor substrate by an oxide film. A sense amplifier circuit is formed in an activated region of the transistor, and a supply section for supplying a substrate potential of the activation region that determines a substrate potential of the transistor and a supply section for supplying a potential of the common source region are shared. . 14 A plurality of sense amplifier circuits connected to each of a plurality of bit line pairs having a connection to a memory cell with a common source region are configured with CMOS type flip-flops, and the common source region of the N-type MOS transistor pair A switch for connecting a power supply line to a voltage supply line connected to a switch is provided at the upper end or lower end of a plurality of sense amplifier circuit groups arranged in a column direction with the source region in common, while a P-type MOS
The switch connecting the power supply line to the voltage supply line connected to the common source region of the transistor pair is the N-type MOS.
A sense amplifier circuit characterized in that it is provided at an end opposite to a switch for a transistor pair. 15 The threshold voltage of MOS type transistors forming a plurality of sense amplifier circuits connected to each of a plurality of bit line pairs having a connection to a memory cell with a common source region, which are formed on the same semiconductor memory chip. A sense amplifier circuit characterized in that the threshold voltage is set to be lower than the threshold voltage of a MOS transistor constituting a circuit other than the sense amplifier circuit.