JPH03214615A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03214615A
JPH03214615A JP1018990A JP1018990A JPH03214615A JP H03214615 A JPH03214615 A JP H03214615A JP 1018990 A JP1018990 A JP 1018990A JP 1018990 A JP1018990 A JP 1018990A JP H03214615 A JPH03214615 A JP H03214615A
Authority
JP
Japan
Prior art keywords
substrates
semiconductor substrates
metal
semiconductor
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1018990A
Other languages
Japanese (ja)
Other versions
JP2566657B2 (en
Inventor
Tadaharu Minato
忠玄 湊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2010189A priority Critical patent/JP2566657B2/en
Publication of JPH03214615A publication Critical patent/JPH03214615A/en
Application granted granted Critical
Publication of JP2566657B2 publication Critical patent/JP2566657B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To execute a highly accurate pasting operation by a method wherein a metal whose melting point is lower than that of semiconductor substrates is used as a pasting medium and the medium metal itself is diffused into the semiconductor substrates. CONSTITUTION:A metal thin film 2 whose melting point is lower than that of both semiconductor substrates 1, 3 to be pasted is sandwiched between the semiconductor substrates 1, 3 to be pasted; an alloying process with the metal is executed; after that, nearly all of metal atoms of it are diffused into at least one of the semiconductor substrates. That is to say, when the low-melting metal 2 is used as a pasting medium, the semiconductor substrates 1, 3 are pasted, and the medium metal 2 itself is diffused and absorbed as part of the semiconductor substrates 1, 3. Thereby, the substrates can be pasted with good accuracy irrespective of the material, crystal plane orientation and flatness of the substrates to be pasted; a crystal defect is hard to produce in the pasted substrates and a highly accurate bonding operation can be realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法において、同種又は異
種の半導体基板を貼り合わせる技術を有する半導体装置
の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, which includes a technique for bonding semiconductor substrates of the same type or different types.

〔従来の技術〕[Conventional technology]

第2図は日経マイクロデハイス1988年3月号に掲載
された従来技術のSiウェハの直接接合の例である。又
、第3図は電子情報通信学会誌Vo1.70, No.
6, pp.593 〜595. ’87. 6月号に
掲載された同技術の細部機構を示す図である。
FIG. 2 is an example of the prior art direct bonding of Si wafers published in the March 1988 issue of Nikkei MicroDehys. Also, Figure 3 is from the Journal of the Institute of Electronics, Information and Communication Engineers Vol. 1.70, No.
6, pp. 593-595. '87. It is a diagram showing the detailed mechanism of the same technology published in the June issue.

以下、この2つの図を使って従来技術を説明する。まず
、第2図において、1.3は貼り付けようとする2種の
Siウエハ、6は貼り付けに先立ちウエハ表面を洗浄す
ると同時に表面をシラノール( 一Si−OH)化する
ための過酸化水素(H202)と硫酸(H2 S 04
 )の混合液、7は重ね合わせたウエハのポイド等の欠
陥を観察するための赤外線透過光源(Siを初めとする
ほとんどの半導体は赤外線を透過させる)で、8はその
赤外線透過光を観察するためのテレビカメラであり、9
は貼り合わせたウェハを加熱する熱処理炉であ?。
The conventional technology will be explained below using these two figures. First, in Figure 2, 1.3 is the two types of Si wafers to be bonded, and 6 is hydrogen peroxide to clean the wafer surface prior to bonding and at the same time convert the surface into silanol (-Si-OH). (H202) and sulfuric acid (H2 S 04
), 7 is an infrared light transmitting light source (most semiconductors, including Si, transmit infrared light) to observe defects such as poids on stacked wafers, and 8 is a light source for observing the infrared transmitted light. It is a TV camera for 9
Is this a heat treatment furnace that heats the bonded wafers? .

次に、第2図の工程について説明する。まず、第2図(
alで上述の如く、貼り合わせようとするウエハ1.3
の表面を洗浄すると同時に、該ウエハ1,3をシラノー
ル化する。その後、乾燥したウエハ同士を空気中、室温
で重ね合わせる(第2図(b))。この時、貼り合わせ
かうまくいっているかどうか、赤外線透過光によりボイ
ド検査を行う(第2図(C))。この検査に合格したも
のを通常の熱処理炉9に入れ、熱処理を行う(第2図(
d))。例えば、1)00゜Cで酸素0■と窒素N2混
合比が1対5の雰囲気中で約2時間熱処理を行う。その
後、熱処理によって貼り合わせが完了したウエハの片方
の面、あるいは両方の面を研磨し、所望の厚さに仕上げ
る(第2図{e})。
Next, the process shown in FIG. 2 will be explained. First, Figure 2 (
As mentioned above in al., the wafer 1.3 to be bonded
At the same time as cleaning the surfaces of the wafers 1 and 3, the wafers 1 and 3 are converted into silanol. Thereafter, the dried wafers are stacked together in the air at room temperature (FIG. 2(b)). At this time, a void inspection is performed using infrared transmitted light to check whether the bonding is successful (Fig. 2 (C)). Items that have passed this inspection are placed in a normal heat treatment furnace 9 and heat treated (see Figure 2).
d)). For example, 1) Heat treatment is performed at 00° C. for about 2 hours in an atmosphere with a mixing ratio of 0:0 and nitrogen (N2) of 1:5. Thereafter, one or both surfaces of the wafers, which have been bonded through heat treatment, are polished to a desired thickness (FIG. 2 {e}).

上記第2図Fdlの熱処理工程中に起こっている詳細な
反応を記述したのが第3図である。図中、13′は貼り
合わせようとするSi基板1と3の最表面にあるSt原
子であり、第2図(a)の工程でシラノール化した際の
酸素原子10と水素原子1)がSi−OHO形で結合し
ている。さらに、第2図(blで貼り合わされた時には
Si基板1と3の双方に結合している2つの水酸基(−
OH)は化学的には等価の状態にあるので、第3図(a
lのように、H /   \ Si−00−Si H の形で水素結合を生じて最表面のSi原子1′と3′が
2個の水酸基を介して結合する。この状態から1000
゜C近くまで徐々に加熱していく過程で、第3図(bl
のように水素結合している2つの水酸基、 \  / H から水分子H2012が離脱し、−Si−0−Si−の
結合へと脱水縮合を起こし、1′と3′のSi原子は酸
素原子10′のみを介在者として結合している状態にな
る。さらに第3図(Clでは10o o ’c以上の加
熱工程中に前述の10′の酸素原?さえも1または3の
Si基板中に格子間酸素10″として、あるいは炉の雰
囲気中へと拡散離脱していき、最終的には1′と3′の
Si最表面原子同士が自身の結合手13によって直接接
合した状態を形成する。
FIG. 3 shows detailed reactions occurring during the heat treatment process shown in FIG. 2 Fdl. In the figure, 13' is the St atom on the outermost surface of the Si substrates 1 and 3 to be bonded, and the oxygen atom 10 and hydrogen atom 1) when silanolized in the step of FIG. 2(a) are -Bonded in OHO form. Furthermore, when bonded together in Figure 2 (bl), two hydroxyl groups (-
OH) are in a chemically equivalent state, so Figure 3 (a
1, a hydrogen bond is formed in the form H/\Si-00-SiH, and the outermost Si atoms 1' and 3' are bonded via two hydroxyl groups. 1000 from this state
In the process of gradually heating up to near °C, the temperature in Figure 3 (bl
Water molecule H2012 separates from the two hydroxyl groups \ / H that are hydrogen bonded as shown in the figure, dehydration condensation occurs to the bond -Si-0-Si-, and the 1' and 3' Si atoms become oxygen atoms. A state is reached in which only 10' is used as an intermediary. Furthermore, as shown in Fig. 3 (for Cl, during the heating step of 10 o'c or more, the aforementioned 10' oxygen source? even diffuses into the 1 or 3 Si substrate as interstitial oxygen 10' or into the atmosphere of the furnace). Eventually, the atoms 1' and 3' on the outermost Si surface are directly bonded to each other by their own bonds 13.

このようにして貼り合わせられた2枚のウエハは最初は
物理的に別々のものであったが、最終的には機械的にも
電気物性的には1枚のウエハとして取り扱えるものにな
ると報告されており、電流経路がSiウエハの裏から表
へという形で形成される、即ち接合面を貫通する形にな
る電力用素子に対して有効であるとされている。
Although the two wafers bonded together in this way were initially physically separate, it was reported that they could eventually be handled as one wafer both mechanically and electrically. This method is said to be effective for power devices in which the current path is formed from the back to the front of the Si wafer, that is, it passes through the bonding surface.

一方、単に機械的なSiウエハの貼り付けはSiO■膜
を介して行う方法や静電圧着法があり、前述の日経マイ
クロデバイス1988年3月号他、ピーイ〜エスーシー
、1988年、4月、1325〜1327頁「ハイボル
ティジ,ニュードライバ IC  テクニソク ウエハ
 ダイレクトポンディングJ  (P E S C ’
88 RECOl?D (.^pri1 198B)p
p.1325〜pp.1327 u旧gh Volta
ge, Neu DriverIC Techniqu
e on Silicon Wafer Direct
−Bor++1ing(SDB)”)や、アイ・−イー
・イー・イー エレクトロン デハイス レターズ E
 D L 8巻 10号 1987年10月 454〜
456頁[アダイエレクトリカリイ アイソレート フ
ォトダイオード アレイ バイ シリコンウェハ ダイ
レクト ポンディングJ  (IE’ Electro
n Device Letters. Vol EDL
−8+ No.10, Oct. ’8L pp.45
4−456  ”A Dielectrically 
Isolated PhotodiodeArray 
by Silicon−Wafer Direct B
onding″)等、他多数に報告されている。しかし
、これらの方法は上述のように貼り付けたウエハ間の電
気物性面での特徴はむしろ絶縁にあり、この発明におけ
る目的とは全く異なるものなので、ここでは詳細につい
ては触れないことにする。
On the other hand, simple mechanical bonding of Si wafers includes a method using a SiO film and an electrostatic bonding method. Pages 1325-1327 "High Voltage, New Driver IC Technisoku Wafer Direct Ponding J (PESC')
88 RECOl? D (.^pri1 198B)p
p. 1325~pp. 1327 u old gh Volta
ge, Neu DriverIC Technique
e on Silicon Wafer Direct
-Bor++1ing (SDB)”) and I-E-E Electron Deheys Letters E
D L Volume 8 No. 10 October 1987 454~
Page 456 [Electrical Isolate Photodiode Array by Silicon Wafer Direct Bonding
n Device Letters. Vol EDL
-8+ No. 10, Oct. '8L pp. 45
4-456 “A Dielectrically
Isolated Photodiode Array
by Silicon-Wafer Direct B
However, as mentioned above, the feature of these methods in terms of electrical properties between the bonded wafers is rather insulation, which is completely different from the purpose of this invention. Therefore, I will not go into details here.

また、公知の技術としてサイリスク等大電力用素子の陽
極金属板(Mo,W等)とSiウェハのA42合金法に
より貼り合わせ技術があるが、これも金属と半導体の貼
り合わせであるという点で本発明と全く異なるものなの
で説明は除外する。
In addition, there is a known technology for bonding anode metal plates (Mo, W, etc.) of high power devices such as Cyrisk and Si wafers using the A42 alloy method, but this is also a bonding process of metal and semiconductor. Since this is completely different from the present invention, explanation thereof will be omitted.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体基板の直接接合法は以上のように構成され
ていたので、以下のような問題点があった。
Since the conventional direct bonding method for semiconductor substrates is configured as described above, it has the following problems.

第1に微視的には第3図に示すような機構で接合が進む
ので、2枚のうエハを重ね合わせる瞬間(第2図(b)
)に、両者の結晶軸面方位が十分正確に一致していない
と接合後接合界面に結晶欠陥や歪みが多く発生ずるだけ
でなく、接合自体がうまく行えないという問題があった
。
First, microscopically, bonding progresses by the mechanism shown in Figure 3, so the moment the two wafers are superimposed (Figure 2 (b)
), there was a problem that if the orientations of the crystal axes of both materials did not match accurately enough, not only would many crystal defects and distortions occur at the bonding interface after bonding, but also the bonding itself would not be successful.

第2にウエハ鏡面同士を重ね合わせる場合に、ウエハ界
面に気泡が残らないように注意を要ずること、又ウエハ
自身の平坦度が十分でないと貼り合わせの機構上、“′
ならう”という過程がないので、簡単に″懸”が発生し
てしまうという問題があった。
Second, when overlapping mirror surfaces of wafers, care must be taken to ensure that no air bubbles remain at the wafer interface, and if the wafers themselves are not sufficiently flat, the bonding mechanism may cause
Since there is no process of "training", there was a problem that "hang" could easily occur.

第3にこの接合機構は“半導体基板表面に親水性を持た
せる処理”によるものと報告されているが、実効的には
Siのシラノール( 一Si −OH)化とその脱水縮
合反応特有の現象と解釈されるので、この機構を用いた
接合はSi基板のみに限られる。
Thirdly, although it has been reported that this bonding mechanism is based on "a treatment that imparts hydrophilicity to the surface of the semiconductor substrate," it is actually a phenomenon unique to the conversion of Si to silanol (-Si-OH) and its dehydration condensation reaction. Therefore, bonding using this mechanism is limited to Si substrates only.

第4にウエハ径が大きくなればなるほど、ウエハ中心部
では第3図(b)のように簡単に氷分子の脱離は起こり
にくくなり、Si,O,H原子のさまざまな化合物が結
晶欠陥発生を誘発するという問題があった。
Fourth, as the wafer diameter increases, it becomes difficult for ice molecules to easily detach from the center of the wafer as shown in Figure 3(b), and various compounds of Si, O, and H atoms cause crystal defects. There was a problem of inducing

第5に接合界面で酸素原子濃度が高くなるために、kV
級高耐圧電力用素子に適しているとされる酸素濃度の低
いFZ法によるS1ウエハを用いた場合でも局部的に酸
素濃度の高いCZ法によって得られるSi基板と同様な
性質(例えば酸素析出等)を持ってしまうという問題が
あった。
Fifth, because the oxygen atom concentration increases at the bonding interface, kV
Even when using an S1 wafer manufactured by the FZ method with a low oxygen concentration, which is suitable for high-voltage power devices, the same properties as Si substrates obtained by the CZ method with a locally high oxygen concentration (for example, oxygen precipitation, etc.) ).

この発明は上記のような問題点を解消するためになされ
たもので、貼り合わせの基板の材質や結晶面方位や平坦
性に鈍感な半導体基板の貼り合わせ方法であると同時に
、貼り合わせた基板中に結晶欠陥の発生しにくい接合技
術を有する半導体装置の製造方法を提供することを目的
とする。
This invention was made to solve the above-mentioned problems, and is a method for bonding semiconductor substrates that is insensitive to the material, crystal plane orientation, and flatness of the bonded substrates. An object of the present invention is to provide a method for manufacturing a semiconductor device using a bonding technique in which crystal defects are less likely to occur.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造方法は、半導体基板の
貼り合わせ方法として、貼り合わせる双方の半導体基根
より低融点の金属薄膜を貼り合わせる半導体基板の間に
挟むとともに、その金属との合金化プロセスを経るよう
にし、その後にその金属原子を少なくとも一方の半導体
基板中にほぼ全原子を拡散する工程を含むようにしたも
のである。
A method for manufacturing a semiconductor device according to the present invention includes, as a method for bonding semiconductor substrates, a metal thin film having a lower melting point than the semiconductor bases of both substrates to be bonded is sandwiched between the semiconductor substrates to be bonded, and an alloying process with the metal is performed. After that, the method includes a step of diffusing substantially all of the metal atoms into at least one of the semiconductor substrates.

〔作用〕[Effect]

この発明における半導体基板の貼り合わせ方法は、貼り
合わせ媒体として低融点金属を用いることにより、半導
体基板同士が貼り合わされ、その媒体金属自身も拡散に
よりこれら半導体基板の一部として吸収される。
In the method of bonding semiconductor substrates according to the present invention, semiconductor substrates are bonded together by using a low melting point metal as a bonding medium, and the medium metal itself is absorbed as a part of these semiconductor substrates by diffusion.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例による半導体装置の製造方
法を示しており、同図(alにおいて、1はP型のSi
ウエハ、2はP型Siウエハ上に形成9 されたAffi膜、3はN型のStウエハで、1と同様
にAll薄膜2を表面に有している。同図(b)はA4
とSiの合金化を行う加熱プロセスを示す。
FIG. 1 shows a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Wafer 2 is an Affi film formed on a P-type Si wafer, and 3 is an N-type St wafer, which, like 1, has an All thin film 2 on its surface. The figure (b) is A4
This shows a heating process for alloying Si and Si.

同図(Clで4ばS i−Aj2の合金層である。同図
(diは再びSi−AAの合金層よりAβ原子をSi基
板中に十分拡散させる加熱プロセスを示す。同図tel
では5はAI!.の拡散によって生じたP型の高濃度不
純物領域を示している。
The same figure (4 in Cl is the Si-Aj2 alloy layer. The same figure (di again shows the heating process to sufficiently diffuse Aβ atoms into the Si substrate from the Si-AA alloy layer.
Then 5 is AI! .. It shows a P-type high concentration impurity region generated by diffusion of .

次に手順について説明する。Next, the procedure will be explained.

まず、重金属や有機物等を十分に取り除いた清浄で、か
つ平坦なP型とN型のSi基板1.3をそれぞれ用意し
、各々の片側の表面にAl薄膜2を形成する(第1図(
a))。
First, clean and flat P-type and N-type Si substrates 1.3 from which heavy metals, organic substances, etc. have been sufficiently removed are prepared, and an Al thin film 2 is formed on one surface of each (see Fig. 1).
a)).

次に、この2枚の基板のAp薄膜のついた面を合わせ、
600゜C以上の不活性又は還元雰囲気の中に入れ加熱
する(第IIFFb))。
Next, align the sides of the two substrates with the Ap thin film attached,
Heat in an inert or reducing atmosphere at 600°C or higher (No. IIFFb)).

この温度で数十分から数時間程度おくごとによって、S
t−Aρの合金層4が形成され、2枚のウエハが接着さ
れる(第1図(C))。
By leaving it at this temperature for several tens of minutes to several hours, the S
An alloy layer 4 of t-Aρ is formed, and the two wafers are bonded together (FIG. 1(C)).

しかし、この時点では機械的には2枚のウエハ10 が接着されているが、電気物性的には半導体/金属/半
導体の構造になっており、1枚の半導体基板とはみなせ
ない。そこで、さらに例えばN2.Ar等の不活性雰囲
気の中で1200゜C程度に加熱し、数時間放置すれば
(第1図(d))、第1図(e)に示すようにAl原子
が、P型1,N型3の各々のSt基板中に十分に拡散し
、元来A!2はSi基板に対してP型不純物ドーパント
であるので、P”不純物領域を形成した形となり、電気
物性的にも1枚の半導体基板とみなせるようになる。
However, at this point, although the two wafers 10 are mechanically bonded, they have a semiconductor/metal/semiconductor structure electrically and cannot be considered as one semiconductor substrate. Therefore, for example, N2. When heated to about 1200°C in an inert atmosphere such as Ar and left for several hours (Fig. 1(d)), Al atoms change to P-type 1, N-type, as shown in Fig. 1(e). fully diffused into each St substrate of type 3, originally A! Since 2 is a P-type impurity dopant for the Si substrate, a P'' impurity region is formed, and electrically and physically it can be regarded as one semiconductor substrate.

より具体的な例として、A−ρ2を300人蒸着する場
合を考える。Aj!−SiO共沸混合物は577℃で1
2.2 atXin  Siであるので、実用的な合金
温度660゜C程度でAρ−Si合金化を行えば、AN
膜300人の約10倍の3000人程度のAβ−Si合
金層4が形成される。高濃度P゛拡敗層1とみなされる
表面不純物濃度は10′9〜1020ケ/cm2であり
、一方、この3000人(0.3,c+m)のAl2−
S i合金層中には八β原子が原子濃度で約1022ケ
/cm’存在するの1) で、拡散後の表面濃度が3X10”〜3X].020ヶ
/cm2 となるには、このAl2−Si層の幅が03
μm×1022/3×1019〜1020−100〜1
0μmになるまで拡敗する必要がある。一方、1200
℃におけるA!の拡散係数D,,は1.6X 1 0−
1)cm2/sec.でB原子の拡散係数Dl](一1
 .  3 X 1 0−”’ cm”/sec.)と
比較すればDA.−/DB’M12.3より儒6χ3.
5となり、/lが約3.5倍、B原子より速く拡散する
ことがわかる。実験データよりB原子は1200゜C約
24hrで約35μm拡散するので、Anの場合も12
00℃,24.hrでは35μmx3.5−122μm
拡散する。従って、An膜300人の場合には1200
℃,数時間〜数十時間の熱処理を第1図(d)の工程で
行えばよいことになる。
As a more specific example, consider the case where 300 people deposit A-ρ2. Aj! -SiO azeotrope is 1 at 577℃
2.2 Since it is atXin Si, if Aρ-Si alloying is performed at a practical alloying temperature of about 660°C, AN
Approximately 3,000 Aβ-Si alloy layers 4 are formed, which is approximately 10 times as many as the 300-layer film. The surface impurity concentration considered to be a high-concentration P゛spreading layer 1 is 10'9 to 1020 particles/cm2, and on the other hand, the Al2-
There are 8β atoms in the Si alloy layer at an atomic concentration of approximately 1022 atoms/cm2, and in order for the surface concentration after diffusion to be 3X10'' to 3X].020 atoms/cm2, this Al2-Si Layer width is 03
μm×1022/3×1019~1020-100~1
It is necessary to spread the damage until it reaches 0 μm. On the other hand, 1200
A at °C! The diffusion coefficient D,, is 1.6X 1 0-
1) cm2/sec. and the diffusion coefficient Dl of the B atom] (-1
.. 3 X 1 0-"'cm"/sec. ) compared to DA. -/DB'M12.3 Confucian 6χ3.
5, indicating that /l diffuses approximately 3.5 times faster than B atoms. According to experimental data, B atoms diffuse by about 35 μm in about 24 hours at 1200°C, so in the case of An, the diffusion rate is also 12
00℃, 24. 35μm x 3.5-122μm for hr
Spread. Therefore, in the case of 300 people in the An film, 1200
C. for several hours to several tens of hours in the process shown in FIG. 1(d).

ここで、実際にはMBE (分子線エビタキシャル)法
.MOCVD (有機金属CVD)法,  rcB(イ
オンクラスタービーム)法等の技術を用いれば、An薄
膜の厚みを数人(−原子レベル)〜数十人で形成するこ
ともできるので、第1図(d)の12 熱処理工程は数百度,数十分という低温.短時間にする
ことも可能である。
Here, the MBE (molecular beam epitaxial) method is actually used. By using techniques such as MOCVD (metal organic CVD) and rcB (ion cluster beam), it is possible to form an An thin film with a thickness of several (-atomic level) to several tens of people, as shown in Figure 1 ( d)-12 The heat treatment process is performed at a low temperature of several hundred degrees or several tens of minutes. It is also possible to shorten the time.

また、上記実施例では第1,第2の半導体基板1.3と
してP型高不純物濃度Si基板及びN型低不純物濃度S
t基板を例にとり、これらの仲介層としての低融点金属
として、Si基仮に対してP型不純物ドーパンI・とな
るAlを選んだが、材料等はこれらのものに限定するも
のではない。即ち、第1.第2の基板1,3はP型でも
N型でも真性(中性)でもよく、また不純物濃度も高濃
度・低濃度のどの組合せでもよく、さらに基板の結晶軸
の面方位を一致させる必要もなく、材質もS3に限らず
、GaAs.InP,CdTe,SiC等のいかなる化
合物半導体及びSi等の単一材料の半導体のいかなる組
合せでも良い。
In the above embodiment, the first and second semiconductor substrates 1.3 are a P-type high impurity concentration Si substrate and an N-type low impurity concentration S substrate.
Taking the t-substrate as an example, Al, which serves as a P-type impurity dopant I for the Si base, was selected as the low melting point metal for these intermediate layers, but the materials are not limited to these. That is, 1st. The second substrates 1 and 3 may be P type, N type, or intrinsic (neutral), and the impurity concentration may be any combination of high concentration and low concentration, and it is also necessary that the plane orientations of the crystal axes of the substrates match. The material is not limited to S3, but also GaAs. Any combination of any compound semiconductor such as InP, CdTe, or SiC, or a single material semiconductor such as Si may be used.

また、仲介となる低融点金属薄膜もSiに対してP型の
ドーパントとなるAβ,Ga..N型ドーパントとなる
As,Sb等はもちろん、中性であるSn,Ti等の金
属でもあるいはこれらの化合物でもよく、又Si以外の
基板の種類に合わせて13 Se,Te等いかなる種類の金属単体及びそれらの化合
物でも良い。
In addition, the low melting point metal thin film that acts as an intermediary also serves as a P-type dopant for Si, such as Aβ, Ga. .. In addition to As and Sb, which serve as N-type dopants, neutral metals such as Sn and Ti or their compounds may also be used, and any type of elemental metal such as 13 Se, Te, etc. may be used depending on the type of substrate other than Si. and compounds thereof may also be used.

また、上記実施例の第1図ではSi−AIの合金化の工
程(第1図(b))と、高温熱処理によるAlの拡散工
程第1図(d)をわけて説明したが、雰囲気ガスの種類
や加熱装置及びその治工具類を工夫することにより、合
金(第1図(b))〜加熱拡敗(第1図(e))のプロ
セスを一度に行うこともできる。
In addition, in FIG. 1 of the above embodiment, the process of alloying Si-AI (FIG. 1(b)) and the process of diffusing Al by high-temperature heat treatment (FIG. 1(d)) were explained separately, but the atmospheric gas By devising the type, heating device, and its jigs and tools, the processes from alloying (FIG. 1(b)) to heating expansion (FIG. 1(e)) can be performed at the same time.

さらに、半導体基板1と3の間に挟む金属2は厚みや種
類に合わせて半導体基板1,3のどちらか一方に形成し
てもよく、また、本実施例のように両方に設けてもよい
。
Further, the metal 2 sandwiched between the semiconductor substrates 1 and 3 may be formed on either one of the semiconductor substrates 1 and 3 depending on the thickness and type, or may be formed on both as in this embodiment. .

このような本実施例によれば、貼り合わせ媒体として低
融点金属を用いることにより半導体基板同志が貼り合わ
され、貼り合わせ媒体金属自身も拡散により半導体基板
の一部として吸収されるので、貼り合わせ基板の材質や
結晶面方位や平坦性に関係なく精度良く貼り合わせでき
るとともに、貼り合わせた基板中に結晶欠陥が発生しに
くく、高精度の接合が実現できる。
According to this embodiment, the semiconductor substrates are bonded together by using a low melting point metal as the bonding medium, and the bonding medium metal itself is absorbed as part of the semiconductor substrate by diffusion, so that the bonded substrates are bonded together. They can be bonded together with high precision regardless of the material, crystal plane orientation, or flatness of the substrates, and crystal defects are less likely to occur in the bonded substrates, making it possible to achieve high-precision bonding.

14 〔発明の効果〕 以上のようにこの発明によれば、半導体基板同士の貼り
合わせ方法をこれら半導体基板より低融点金属を貼り合
わせ媒体として用い、又その媒体金属自体をほとんどこ
れら半導体基板中に拡散するように構成したので、従来
技術に比べて簡便にかつ歩留り良く形成することができ
、また応用範囲の広いものが得られる効果がある。
14 [Effects of the Invention] As described above, according to the present invention, the method for bonding semiconductor substrates to each other uses a metal with a lower melting point than these semiconductor substrates as a bonding medium, and most of the medium metal itself is contained in these semiconductor substrates. Since it is configured to diffuse, it can be formed more easily and with a higher yield than conventional techniques, and has the effect of providing a wide range of applications.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による半導体装置の製造方
法の半導体基板の貼り合わせ方法を示す断面模式図、第
2図は従来の半導体基板の貼り合わせ方法を示す断面模
式図、第3図は第2図の一部の機構を詳細に示した断面
模式図である。 図中、1.3は半導体基板、2は低融点金属薄膜、4は
半導体基板材料と低融点金属薄膜との合金層、5は低融
点金属薄膜原子の拡散領域、6は硫酸,過酸化水素混合
液、7は赤外線透過光源、8は赤外線観察用テレビカメ
ラ、9は熱処理炉、10はSi原子とH原子の間で結合
している酸素15 原子、10′はSi原子同士を結びつけている酸素原子
、10″は半導体基板界面から抜けていく酸素原子、1
)は酸素原子と結合している水素原子、12は半導体基
板界面から抜けていく氷分子、13は半導体基板界面で
のSi原子同士の結合手16 第 3 (G) ≦200°C −102一 手続補正書 (自発) ■. 事件の表示 特願平2−10189号 2. 発明の名称 半導体装置の製造方法 34 4. 補正をずる者 事件との関係   特許出願人 住 所  東京都千代田区丸の内二丁目2番3号名 称
  (601)三菱電機株式会社代表者 志岐守哉
FIG. 1 is a schematic cross-sectional view showing a method for bonding semiconductor substrates in a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view showing a conventional method for bonding semiconductor substrates, and FIG. 2 is a schematic cross-sectional view showing in detail a part of the mechanism shown in FIG. 2. FIG. In the figure, 1.3 is a semiconductor substrate, 2 is a low melting point metal thin film, 4 is an alloy layer of the semiconductor substrate material and the low melting point metal thin film, 5 is a diffusion region of low melting point metal thin film atoms, and 6 is sulfuric acid, hydrogen peroxide. Mixed liquid, 7 is an infrared transmission light source, 8 is a television camera for infrared observation, 9 is a heat treatment furnace, 10 is 15 oxygen atoms bonded between Si atoms and H atoms, and 10' is bonded between Si atoms. Oxygen atoms, 10″ are oxygen atoms that escape from the semiconductor substrate interface, 1
) is a hydrogen atom bonded to an oxygen atom, 12 is an ice molecule that escapes from the semiconductor substrate interface, and 13 is a bond between Si atoms at the semiconductor substrate interface. Procedural amendment (voluntary) ■. Incident display patent application No. 10189/1992 2. Title of invention: Method for manufacturing semiconductor devices 34 4. Relationship to the case of a person who cheats on amendments Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki

Claims (1)

【特許請求の範囲】[Claims] (1)第1の半導体基板と第2の半導体基板とを貼り合
わせる基板貼り合わせ工程を有する半導体装置の製造方
法において、 前記基板貼り合わせ工程は、 前記第1、第2の半導体基板のうち、少なくとも一方の
半導体基板の表面に、該第1、第2両方の半導体基板よ
り低融点の金属薄膜を形成する工程と、 該金属薄膜を仲介として、前記第1、第2の半導体基板
同士を貼り合わせる工程と、 加熱により、前記金属薄膜中の原子の全数近くを、前記
第1、第2の半導体基板の少なくとも一方の基板中に拡
散する工程とを含むことを特徴とする半導体装置の製造
方法。
(1) In a method for manufacturing a semiconductor device including a substrate bonding step of bonding a first semiconductor substrate and a second semiconductor substrate, in the substrate bonding step, out of the first and second semiconductor substrates, forming a metal thin film having a lower melting point than both the first and second semiconductor substrates on the surface of at least one semiconductor substrate; bonding the first and second semiconductor substrates together using the metal thin film as an intermediary; A method for manufacturing a semiconductor device, comprising: a step of combining; and a step of diffusing nearly all of the atoms in the metal thin film into at least one of the first and second semiconductor substrates by heating. .
JP2010189A 1990-01-18 1990-01-18 Method for manufacturing semiconductor device Expired - Fee Related JP2566657B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010189A JP2566657B2 (en) 1990-01-18 1990-01-18 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010189A JP2566657B2 (en) 1990-01-18 1990-01-18 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH03214615A true JPH03214615A (en) 1991-09-19
JP2566657B2 JP2566657B2 (en) 1996-12-25

Family

ID=11743340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010189A Expired - Fee Related JP2566657B2 (en) 1990-01-18 1990-01-18 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2566657B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000286174A (en) * 1999-03-30 2000-10-13 Mitsubishi Materials Silicon Corp Laminated substrate and method of manufacturing the same
JP2000315634A (en) * 1999-04-30 2000-11-14 Mitsubishi Materials Silicon Corp Method for manufacturing bonded silicon wafer and bonded substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000286174A (en) * 1999-03-30 2000-10-13 Mitsubishi Materials Silicon Corp Laminated substrate and method of manufacturing the same
JP2000315634A (en) * 1999-04-30 2000-11-14 Mitsubishi Materials Silicon Corp Method for manufacturing bonded silicon wafer and bonded substrate

Also Published As

Publication number Publication date
JP2566657B2 (en) 1996-12-25

Similar Documents

Publication Publication Date Title
JP3265493B2 (en) Method for manufacturing SOI substrate
KR900003830B1 (en) Bonding Method of Silicon Plate or Silicon Dioxide Plate
US3909332A (en) Bonding process for dielectric isolation of single crystal semiconductor structures
US5650639A (en) Integrated circuit with diamond insulator
JP3513592B2 (en) Manufacturing method of solar cell
KR101362688B1 (en) Photovoltaic device and method for manufacturing the same
EP0371862A2 (en) Method of forming a nonsilicon semiconductor on insulator structure
AU745315B2 (en) Method for manufacturing semiconductor article
US20040169225A1 (en) Isotopically pure silicon-on-insulator wafers and method of making same
CN101652867A (en) Photovoltaic device and method for manufacturing the same
US20080217651A1 (en) Photodetector
TW201003961A (en) Solar cell spin-on based process for simultaneous diffusion and passivation
JPH06244389A (en) Manufacture of semiconductor substrate and semiconductor substrate manufactured by this method
TWI437644B (en) Semiconductor substrate manufacturing method
JP3033655B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP5009124B2 (en) Manufacturing method of semiconductor substrate
JPH05226620A (en) Semiconductor substrate and manufacturing method thereof
CN1033907A (en) The process of directly bonding semiconductor
JPH08316443A (en) SOI substrate and manufacturing method thereof
JPH10256263A (en) SOI substrate and manufacturing method thereof
JP2566657B2 (en) Method for manufacturing semiconductor device
CN101341577B (en) Method for manufacturing soi substrate, and soi substrate
JPH0636407B2 (en) Semiconductor wafer bonding method
JP2022067962A (en) Manufacturing method for soi wafer, and soi wafer
JP2002118242A (en) Semiconductor member manufacturing method

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees