JPH03214636A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH03214636A JPH03214636A JP2009407A JP940790A JPH03214636A JP H03214636 A JPH03214636 A JP H03214636A JP 2009407 A JP2009407 A JP 2009407A JP 940790 A JP940790 A JP 940790A JP H03214636 A JPH03214636 A JP H03214636A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- semiconductor
- end parts
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体を搭載するのに用いられるプリント
配線板に係る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a printed wiring board used to mount a semiconductor.
(従来の技術〕
プリント配線板による半導体チップキャリアとして、プ
リント配線板にピンを挿入したピングリッドアレイ(P
GA)やプリント配線板の端面に外部端子を直接配設し
たプラスチックリードレスチッフ゜キャリア(PLCC
)が日経エレクトロニクス別冊マイクロデバイセズ、1
984.6.LL no.2の160〜16日真に記載
され知られ、またプリント配線板に直接半導体チップを
搭載するチップオンポーt’ (COB)なども特開昭
61−349895号公報で知られている。これらの場
合において、プリント配線板に搭載された半導体チップ
とプリント配線板の導体回路の導体回路端部とは、極細
の金線やアルミニウム線よるワイヤーリングによって相
互接続が一殻に行われている。(Prior art) As a semiconductor chip carrier using a printed wiring board, a pin grid array (P
GA) and plastic leadless chip carriers (PLCC) with external terminals directly arranged on the edge of the printed wiring board.
) is Nikkei Electronics Special Issue Micro Devices, 1
984.6. LL no. A chip-on-port (COB) in which a semiconductor chip is directly mounted on a printed wiring board is also known from Japanese Patent Laid-Open No. 61-349895. In these cases, the semiconductor chip mounted on the printed wiring board and the end of the conductive circuit on the printed wiring board are interconnected in one shell by a wire ring made of ultra-fine gold wire or aluminum wire. .
近年、半導体チップの高機能化、高集積化により、半導
体チップのI/O数が増加し、前記のワイヤーリングの
数も増加する結果、半導体チップを取り囲むプリント配
線板の導体回路端部の数も増加する。従来、60〜15
0本程度であったものが、近年は300本程度が必要と
され、今後さらに400〜500本も用いられるものと
推測されている。この様に、導体回路端部が増加した場
合において、第6図には、そのモデル化したもので示す
が、導体回路2の幅や形状が同じ導体回路端部5を有す
るプリント配線板1では導体回路端部5の順番を認識す
るのが困難で、半導体チンプ3と間違った位置の導体回
路端部5とを金線4でワイヤーリングする問題が生じる
。In recent years, as semiconductor chips have become more sophisticated and highly integrated, the number of I/Os on semiconductor chips has increased, and the number of wire rings has also increased, resulting in an increase in the number of conductor circuit ends on printed wiring boards surrounding semiconductor chips. will also increase. Conventionally, 60-15
In recent years, about 300 pieces of paper have been required, whereas it used to be about 0 pieces, and it is estimated that 400 to 500 pieces will be used in the future. In this way, when the number of conductor circuit ends increases, as shown in a model in FIG. It is difficult to recognize the order of the conductor circuit ends 5, and a problem arises in which the gold wire 4 is wired between the semiconductor chimp 3 and the conductor circuit end 5 in the wrong position.
半導体との接続の順序が、容易に認識できる導体回路端
部を有するプリント配線板を提供することにある。The object of the present invention is to provide a printed wiring board having conductor circuit ends whose order of connection to the semiconductor is easily recognizable.
本発明に係るプリント配線板は、前記の課題を解決する
ため、半導体と接続されるプリント配線板の導体回路に
おいて、異なる形状の導体回路の端部を一定の間隅ごと
に配設された導体回路を有することを特徴とするプリン
ト配線板を提供することにある。In order to solve the above-mentioned problem, the printed wiring board according to the present invention has a conductor circuit of a printed wiring board connected to a semiconductor, in which the ends of the conductor circuits of different shapes are arranged at every corner for a certain distance. An object of the present invention is to provide a printed wiring board characterized by having a circuit.
〔実施例] 以下に、本発明を図面に基づいて説明する。〔Example] The present invention will be explained below based on the drawings.
第1図は本発明の一実施例で、プリント配線板に半導体
が搭載され実装された部分を拡大した平面図であり、第
2図〜第5図はそれぞれ他の実施例を示した平面図であ
る。なお、いずれも実際の場合の導体回路端部の数60
本以上のものを、導体回路端部の数の少ないモデル化し
たもので示した。FIG. 1 is an enlarged plan view of an embodiment of the present invention in which a semiconductor is mounted and mounted on a printed wiring board, and FIGS. 2 to 5 are plan views showing other embodiments. It is. In both cases, the number of conductor circuit ends in actual cases is 60.
This is a model with a small number of conductor circuit ends.
プリント配線板1の導体回路2の導体回路端部5が半導
体3を取り囲むように回路形成されたものにおいて、第
1図では4木目ごとに導体回路端部5が、他のものに比
べ短い形状を有し、半導体3の所定位置と金線4により
それぞれの導体回路端部5と接続されている。In a printed wiring board 1 in which the conductor circuit ends 5 of the conductor circuit 2 surround the semiconductor 3, in FIG. , and are connected to respective conductor circuit ends 5 at predetermined positions of the semiconductor 3 and through gold wires 4 .
第2図では5本目ごとに導体回路端部5の先端形状が斜
めに切断された形状を有し、第3図では5本目ごとに導
体回路端部5の先端形状が突出してT字型の形状を有し
、第4図では4本目ごとに導体回路端部5の先端形状が
L字型の形状を有し、第5図では4本目ごとに回路幅が
やや太い形状の導体回路端部5を有する。なお、以上は
いずれも、一例であり、これらを組み合わせて用いるこ
ともでき、これらの形状に限定されるものではない。ま
た、一定間隔ごとの特殊な形状の導体回路端部が、一本
でなく複数本、例えば10本、20本連続で配設された
ものでもよい。In FIG. 2, the tip shape of the conductor circuit end 5 is cut diagonally for every fifth conductor circuit, and in FIG. In FIG. 4, every fourth conductor circuit end 5 has an L-shaped tip, and in FIG. 5, every fourth conductor circuit end has a slightly thicker circuit width. 5. Note that all of the above are examples, and they can be used in combination, and the shapes are not limited to these. Further, the end portions of the conductor circuit having a special shape at regular intervals may be arranged not only one but in a plurality, for example, 10 or 20 in a row.
以上のように、一定間隔ごとに特殊な形状の導3 一
体回路端部が、半導体の周囲に配設されるために、半導
体と導体回路端部の接続順序の確認が行いやすく、接続
誤認の阻止に有用な作用をし、実装製品の歩留り向上を
もたらすものであり、導体回路端部の数が60本以上の
ものにおいてその効果が認められ、特に150本以上の
ものにおいては、顕著である。As described above, since the conductor 3 integral circuit ends are arranged at regular intervals around the semiconductor, it is easy to confirm the connection order of the semiconductor and the conductor circuit ends, and there is no possibility of misidentification of connection. It has a useful effect in blocking and improves the yield of mounted products, and its effect is recognized in products with 60 or more conductor circuit ends, and is especially noticeable in products with 150 or more conductor circuit ends. .
次に、使用材料について述べる。前記のプリント配線板
1には、基材に樹脂を含浸乾燥して得られたプリプレグ
の樹脂を硬化した絶縁材料が用いられる。この絶縁材料
の樹脂としては耐熱性、耐湿性に優れかつ樹脂純度、特
にイオン性不純物の少ないものが好ましい。具体的には
エボキシ樹脂、ポリイミド樹脂、不飽和ポリエステル樹
脂、フッソ樹脂、フェノール樹脂、PPO樹脂などの樹
脂が適し、絶縁材料の基材としては、紙布、有機合成繊
維、ガラス繊維、ガラス不織布など用途に応じて適宜選
択して用いることができる。特にガラス繊維、ガラス不
織布などの無機材料の方が耐熱性、耐湿性などに優れ好
ましい。Next, we will discuss the materials used. The printed wiring board 1 is made of an insulating material obtained by curing a prepreg resin obtained by impregnating a base material with a resin and drying it. The resin for this insulating material is preferably one that has excellent heat resistance and moisture resistance, and has high resin purity, particularly low ionic impurities. Specifically, resins such as epoxy resin, polyimide resin, unsaturated polyester resin, fluorocarbon resin, phenol resin, and PPO resin are suitable, and as base materials for insulating materials, paper cloth, organic synthetic fiber, glass fiber, glass nonwoven fabric, etc. It can be appropriately selected and used depending on the purpose. In particular, inorganic materials such as glass fiber and glass nonwoven fabric are preferable because of their excellent heat resistance and moisture resistance.
4
プリント配線板lに配設された導体回路2と導体回路端
部5としては銅、真鍮、アルミニウム、鉄、ステンレス
などから適宜選択して用いることができる。中でも銅が
導電性に優れ特に好ましい。4 The conductor circuit 2 and the conductor circuit end portion 5 disposed on the printed wiring board 1 can be appropriately selected from copper, brass, aluminum, iron, stainless steel, etc. and used. Among them, copper is particularly preferred because of its excellent conductivity.
次に、この導体回路と導体回路端部の形成には、アディ
ティブ法、サブトラクティブ法などの通常用いられる種
々の回路形成方法を用いることかでぎる。Next, the conductor circuit and the ends of the conductor circuit can be formed by using various commonly used circuit forming methods such as an additive method and a subtractive method.
(発明の効果〕
本発明のプリント配線板では叙述の如く、半導体と接続
されるプリント配線板の導体回路において、一定の間隔
ごとに配設された異なる形状の導体回路端部を有するプ
リント配線板によって、半導体との接続の順序が、容易
に認識でき、ワイヤリングミスの防止ができ、実装の歩
留り向上が可能になるのである。(Effects of the Invention) As described above, in the printed wiring board of the present invention, in the conductor circuit of the printed wiring board connected to the semiconductor, the printed wiring board has conductor circuit ends of different shapes arranged at regular intervals. This makes it possible to easily recognize the order of connections with semiconductors, prevent wiring mistakes, and improve packaging yield.
第1図は本発明の一実施例の平面図、 第2図〜第5図他の実施例の平面図 第6図一従来例の平面図をそれぞれ示す。 ・・・プリント配線板 ・・導体回路 ・・・半導体 ・・・金線 ・・・導体回路端部 FIG. 1 is a plan view of an embodiment of the present invention; Figures 2 to 5 are plan views of other embodiments. FIG. 6 shows a plan view of a conventional example. ・・・Printed wiring board ・Conductor circuit ···semiconductor ...gold wire ...Conductor circuit end
Claims (1)
おいて、一定の間隔ごとに配設された異なる形状の導体
回路端部を有することを特徴とするプリント配線板。(1) A printed wiring board characterized in that a conductor circuit of the printed wiring board connected to a semiconductor has conductor circuit ends of different shapes arranged at regular intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009407A JPH03214636A (en) | 1990-01-18 | 1990-01-18 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009407A JPH03214636A (en) | 1990-01-18 | 1990-01-18 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03214636A true JPH03214636A (en) | 1991-09-19 |
Family
ID=11719558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009407A Pending JPH03214636A (en) | 1990-01-18 | 1990-01-18 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03214636A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006140535A (en) * | 1999-01-08 | 2006-06-01 | Aisin Aw Co Ltd | Electronic components |
-
1990
- 1990-01-18 JP JP2009407A patent/JPH03214636A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006140535A (en) * | 1999-01-08 | 2006-06-01 | Aisin Aw Co Ltd | Electronic components |
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