JPH03214651A - Verification of layout pattern - Google Patents

Abstract

PURPOSE:To display the place of an error and the content of an error so as to be recognized at a glance and to easily correct the place of the error by providing an error feedback display processing module to a circuit diagram in order to display, in the circuit diagram, an error state regarding a layout pattern data error in a stored verification result. CONSTITUTION:A verification result which has been generated and stored by executing a comparison and verification operation at a layout verification module 4 is controlled by using an error feedback display processing module 7 to a circuit diagram. A data for display use is generated from information for verification use; the data is displayed. Thereby, a connection mistake of a layout pattern data and a mistake regarding the number of devices can be judged at a glance; the place of an error and the content of an error can be corrected easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a design verification method for layout pattern data of a semiconductor integrated circuit.

[Conventional technology]

FIG. 4 is an explanatory diagram of a conventional layout pattern verification method. In the same figure, 1 is layout pattern data, 2 is circuit diagram data, and 3 is layout pattern data 1.
Verification rule 4 performs comparative verification of device information, circuit explanation information, etc. of circuit diagram data 1 and circuit diagram data 2, and 4 extracts device information, circuit explanation information, etc. from layout pattern data 1 and circuit diagram data 2 according to verification rule 3, and performs comparative verification. do the
A layout verification module 5 generates and stores verification results, 5 designates verification results generated and stored by the layout verification module 4, and 6 an error display module for displaying verification results.

Next, the operation will be explained using FIG. 5. Using the verification rule 3 for extracting and comparing the device information, circuit connection information, etc. of the layout pattern data 1 and the circuit diagram data 2, the layout verification module 4 extracts the device information of the layout pattern data 1 and the circuit diagram data 2, Extract circuit connection information, etc., and perform comparative verification (step 11~
14), generate and store verification result 5 (stenop 15)
).

If there is an error, the error display module 6 displays the generated and recorded verification result 5, including different device information between the layout pattern data 1 and the circuit diagram data 2 (steps 16 and 17).

FIG. 6 shows an example where an error is displayed on the circuit diagram data. In the figure, thick lines indicate different parts of the layout pattern data and circuit diagram data.

[Problem to be solved by the invention]

The conventional layout pattern verification method is configured as described above, so the verification results (match and unmatch information)
It is necessary to refer to the layout pattern data and circuit diagram data to determine the error content by displaying the error location in each, but there are problems such as it is difficult to understand the error content at a glance, and it takes time to correct the error. Ta.

The present invention has been made in view of these points, and its purpose is to provide a layout pattern verification method that displays error locations and error details at a glance and allows for easy correction of error locations. There is a particular thing.

Means for Solving Problem C] In order to achieve such an object, the present invention provides a method for verifying information such as device information and circuit connection information between layout pattern data and circuit diagram data. A layout verification module that performs comparative verification using this verification rule and stores the verification results, and a circuit diagram that displays error states regarding layout pattern data errors in the stored verification results. The circuit diagram includes an error feedbank display processing module for displaying error data on the circuit diagram data, and an error display module for displaying error details on the circuit diagram data.

[Effect]

In the layout pattern verification method according to the present invention,
Perform comparative verification using the layout verification module to generate and
The stored verification results are controlled by an error feedback display processing module for the circuit diagram, data to be displayed is generated from the verification information, and this data is displayed. This allows you to determine the location of the error and the details of the error at a glance just by looking at the circuit diagram data.

〔Example〕

An embodiment of the layout pattern verification method according to the present invention will be described below with reference to FIGS. 1 to 3.

In FIG. 1, 1 is layout pattern data, 2 is circuit diagram data, and 3 is a verification rule for extracting verification information such as de-heiss information and circuit connection information of layout pattern data 1 and circuit diagram data 2, and performing comparative verification. , 4 is a layout verification module that extracts verification information such as device information and circuit connection information from layout pattern data 1 and circuit diagram data 2 according to verification rule 3, performs comparative verification, and generates and stores verification results. Verification results generated and stored by the layout verification module 4; 7 is an error feed box display processing module that controls the display of error locations and error contents from the verification results 5;
This is an error display module that displays the data controlled by the error feed display processing module 7 to the circuit diagram.

Next, the operation will be explained using FIG. 2. The layout verification module 4 uses verification rules to extract and compare verification information such as device information and circuit description information between the layout pattern data 1 and the circuit diagram data 2, and between the layout pattern data 1 and the circuit diagram data 2. Deheis information of pattern data 1 and circuit diagram data 2,
Verification information such as circuit connection information is extracted, comparative verification is performed (steps 21 to 24), and verification results are generated (step 25) and stored. If there is an error, the generated and stored verification result 5 is used to feed the error to the circuit diagram.The display processing module 6 displays different device information, circuit connection information, etc. between the layout pattern data 1 and the circuit diagram data 2. Recognize and generate data for display (
step 2627). From the generated data, the error display module 7 displays different device information, circuit connection information, etc. of the layout Bakun data 1 and the circuit diagram data 2 (step 28).

FIG. 3 shows an example in which an error is displayed on circuit diagram data. In the figure, dotted lines indicate different parts of the layout pattern data and circuit diagram data.

〔Effect of the invention〕

As explained above, the present invention compares and verifies verification information between layout pattern data and circuit diagram data, records the verification results, and uses the verification results to compare and verify verification information that is output as an error in layout pattern data. By returning the circuit diagram to the circuit diagram data and displaying an error message indicating the difference, it is possible to determine at a glance any mistakes in the layout pattern data, such as connection errors, number of dehyces, etc.
It becomes easier to correct the error location and error content. It also makes it easier to modify and debug verification rules.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the layout pattern verification method according to the present invention, FIG. 2 is a flowchart showing the operation in the embodiment explained in FIG. 1, and FIG. 3 is according to the embodiment explained in FIG. 1. A data diagram showing an example of error display on circuit diagram data, Fig. 4 is an explanatory diagram of a conventional layout pattern verification method, Fig. 5 is a flowchart showing the operation of the conventional method explained in Fig. 4, and Fig. 6 is a 5 is a data diagram showing an example of error display on circuit diagram data according to the conventional method described in FIG. 4. FIG.

Claims (1)

[Claims] A verification rule for comparing and verifying verification information such as device information and circuit connection information between the layout pattern data and circuit diagram data between the layout pattern data and the circuit diagram data, and this verification rule. a layout verification module that performs the comparative verification using the above and stores the verification results; and an error feedback display on the circuit diagram for displaying an error state regarding a layout pattern data error in the stored verification results in the circuit diagram. A layout pattern verification method comprising: a processing module; and an error display module that displays error details on circuit diagram data.