JPH03214663A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to obtain BiCMOS LSI of high performance by a relatively simple process, by forming all of a bipolar base electrode and gate electrodes of nMOS and pMOS only of p-type polycrystalline silicon of a first layer. CONSTITUTION:An n<+> type buried layer 2 and a p-type diffusion layer 3 are provided in a part of a p-type silicon substrate 1, an epitaxial layer is made to grow and a silicon dioxide 4 is formed by using an ordinary oxide film isolation method. Thereafter a p-type diffusion layer 5 is provided, a base region is formed, a gate oxide film is formed, an opening is provided in a part on the base region and, in succession, p-type polycrystalline silicon 6 and a silicon dioxide 7 are deposited. Thereafter gate electrodes of nMOS and pMOS and a bipolar base electrode are formed simultaneously by using ordinary techniques of photolithography and dry etching. Since the bipolar base electrode and the gate electrodes of nMOS and pMOS are formed of the same p-type polycrystalline silicon by this method, the number of processes can be lessened considerably.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor memory device, and more particularly to a BiCMOS LSI that can obtain high performance characteristics through relatively simple steps. [Prior Art] Conventional semiconductor devices are described in I.E.D.
EDM (1988), pp. 748-751), first, a bipolar p-type heath lead electrode is formed using a first layer of polycrystalline silicon, and then a second layer of polycrystalline silicon is used to form a bipolar p-type heath lead electrode. N-channel MOS transistor (nMOS) and p-channel MOS+ using silicon
An n-type gate electrode of a helangistor (pMOS) was formed. [Problems to be Solved by the Invention] When attempting to realize a high-performance BjCMOS LSI using the above-mentioned conventional technology, it is necessary to use a first layer of p-type polycrystalline silicon and a second layer of n-type polycrystalline silicon. First, there was a problem in that the manufacturing method was complicated. It is also possible to make a part of the first layer of polycrystalline silicon p-type and n-type, but in this case, p-type polycrystalline silicon and n-type
Since the dry etching speeds of the polycrystalline silicon types are different, the p-type and n-type polycrystalline silicon must be processed separately, complicating the manufacturing method. (2) The purpose of the present invention is to produce high-performance BiCM with a relatively simple process.
The object of the present invention is to provide a semiconductor device that can realize OS LS technology. [Means for Solving the Problems] In order to achieve the second object, in the present invention, the bipolar base electrode and the nMOS and pMOS gate electrodes are all made of the first layer of P-type polycrystalline silicon. Formed with chisel. Conventionally, n-type polycrystalline silicon has been used for the gate 1 to electrodes of nMOS and PROS.
The OS was operated as a surface channel type device, and the pMOS was operated as a buried channel type device. This time, n
P-type polycrystalline silicon is used for the gate 1 electrode of MOS and pMOS, but since the work function of P-type polycrystalline silicon is different from that of conventional n-type polycrystalline silicon, nMOS
The device was operated as a buried channel type device, and pMOs was operated as a surface channel type device. [Operation] According to the present invention, a bipolar base electrode and nMOs,
Since the gate electrode of the pMOs is formed of the same p-type poly(3) crystalline silicon, the number of steps can be significantly reduced. In addition, nMOS is a buried channel type, p.
Since the MOS is operated as a surface channel type, it is possible to realize a CMOS transistor having performance equal to or better than conventional ones. [Example] An example of the present invention will be described below with reference to FIGS. 1 to 4.

Embodiment 1 First, as shown in FIG. 2, an N+ type buried layer 2 and a P type diffusion layer 3 are provided in a part of a p type silicon substrate 1, and an epitaxial layer is grown. Next, silicon dioxide 4 is formed using a normal oxide film separation method. Thereafter, as shown in FIG. 3, a p-type diffusion layer 5 is provided to form a base region. Next, a gate oxide film is formed, an opening is provided in a part of the base region, and p-type polycrystalline silicon 6 and silicon dioxide 7 are subsequently deposited. After this, nMOS and p. A MOs gate electrode and a bipolar base electrode are formed at the same time. Next, silicon dioxide is deposited on the element surface, and side spacers 8 of silicon dioxide are provided by using a dry etching technique. Finally, by forming the rI type diffusion layer 9 and the p type diffusion layer 1o, the BiC
MOS LS is completed. Incidentally, as shown in FIG. 4, it is also possible to form a bipolar n-type emitter diffusion layer 9' using n-type polycrystalline silicon 12. In this case, the emitter diffusion layer 9 in FIG.
Compared to this, the depth of the diffusion layer can be made shallower, so the bipolar characteristics can be improved.

Embodiment 2 FIG. 5 shows another embodiment of the present invention. In this example,
A bipolar p-type base extraction electrode 6 was formed to surround the n-type emitter diffusion layer 6. As a result,
BiCMO with performance equivalent to or better than the semiconductor device shown in Figure 1
We were able to realize S LSI. It goes without saying that the present invention is effective even if the conductivity types of all n(5) type and p type are reversed in Examples 1 and 2 above. [Effects of the Invention] As explained above, the present invention can form a BjCMOS LSI using only the first layer of P-type polycrystalline silicon.
The number of steps can be reduced. For example, using the present invention, 4 M
bj. As a result of trial manufacturing of tBiCMOS d R A M , the number of steps was reduced from 450 to 350. Furthermore, as a result of using a high-performance bibolar L S process,
The circuit speed has also been significantly improved, achieving read and write times of approximately 5 ns.

[Brief explanation of drawings]

1 to 4 are process cross-sectional views of an element showing one embodiment of the present invention. Moreover, FIG. 5 is a process sectional view of an element showing another embodiment of the present invention.

Claims (1)

[Claims] 1. In BiCMOSLSI, the gate electrodes of the n-type MOS transistor and the p-type MOS transistor, and the base electrode of the bipolar transistor are made of the same semiconductor material or the same semiconductor material and metal. A semiconductor device characterized in that it is formed of a multilayer film. 2. The semiconductor device according to claim 1, wherein the semiconductor material is p-type polycrystalline silicon.