JPH03214739A - Insulated gate type fet and its manufacture - Google Patents
Insulated gate type fet and its manufactureInfo
- Publication number
- JPH03214739A JPH03214739A JP2009712A JP971290A JPH03214739A JP H03214739 A JPH03214739 A JP H03214739A JP 2009712 A JP2009712 A JP 2009712A JP 971290 A JP971290 A JP 971290A JP H03214739 A JPH03214739 A JP H03214739A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- insulating film
- film
- insulated gate
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁ゲート型ＦＥＴとその製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate FET and a method for manufacturing the same.
従来技術による絶縁ゲート型ＦＥＴの製造方法について
、第３図（ａ）〜（ｄ）を参照して説明する。A conventional method for manufacturing an insulated gate FET will be described with reference to FIGS. 3(a) to 3(d).
はじめに第３図（ａ）に示すように、Ｐ型シリコン基板
１の表面にゲート酸化膜５を形成し、ポリシリコンまた
はタングステンなどからなるゲート電極材７を堆積した
のちフォトレジスト８を形成する。First, as shown in FIG. 3(a), a gate oxide film 5 is formed on the surface of a P-type silicon substrate 1, a gate electrode material 7 made of polysilicon, tungsten, or the like is deposited, and then a photoresist 8 is formed.
つぎに第３図（ｂ）に示すように、ＲＩＥ法によりフォ
トレジスト８をマスクとしてゲー１・電極材７をエッチ
ングｌ，て、ゲート電極７を形成してＯ２プラズマエッ
チングによりフォトレジスト８を除去する。Next, as shown in FIG. 3(b), the gate electrode material 7 is etched using the photoresist 8 as a mask by the RIE method to form the gate electrode 7, and the photoresist 8 is removed by O2 plasma etching. do.
つぎにゲート電極７をマスクとして、燐イオン（３１Ｐ
” ）を加速エネルギー１ ５０ｋｅＶ、注入量（ドー
ス）Ｉ Ｘ １ ０”ｃｍ−２注入して層抵抗１５００
Ω／口、接合深さ０．３μｍのソース１０とドレイン１
１とを形成する。Next, using the gate electrode 7 as a mask, phosphorus ions (31P
) was implanted at an acceleration energy of 150 keV and an implantation amount (dose) of I x 10"cm-2 to achieve a layer resistance of 1500.
Ω/mouth, junction depth 0.3 μm source 10 and drain 1
1.
つぎに第３図（ｃ）に示すように、ＰＳＧ膜９を堆積し
て、ソースートレインコンタクトを開口する。Next, as shown in FIG. 3(c), a PSG film 9 is deposited and a source-train contact is opened.
最後に第３図（ｄ）に示すように、アルミニウムなどか
らなるソース電極１２とドレイン電極１３とを形成して
素子部が完成する。Finally, as shown in FIG. 3(d), a source electrode 12 and a drain electrode 13 made of aluminum or the like are formed to complete the element section.
半導体集積回路の高速化、高集積化のため、ゲート長が
短縮されるに伴ないゲート抵抗が増大する傾向にある。2. Description of the Related Art As semiconductor integrated circuits become faster and more highly integrated, gate resistance tends to increase as gate lengths become shorter.
ゲート抵抗の増大を食い止めるため、ゲート電極を厚く
する必要があり、サブミクロンのゲート長においては、
実現不可能なほど大きなアスペクト比になってしまう。In order to prevent an increase in gate resistance, it is necessary to thicken the gate electrode, and for submicron gate lengths,
This results in an unrealizably large aspect ratio.
本発明の絶縁ゲート型ＦＥＴは、半導体基板表面に絶縁
膜からなる１対の側壁が形成され、上方に側壁の内法を
はみ出し、外法より短いゲー１・電極が形成されている
。In the insulated gate FET of the present invention, a pair of sidewalls made of an insulating film are formed on the surface of a semiconductor substrate, and a gate electrode is formed upwardly protruding from the inner edge of the sidewall and shorter than the outer edge.
本発明の絶縁ゲート型ＦＥＴの製造方法は、半導体基板
表面に第１の絶縁膜と犠牲膜とを順次堆積し、犠牲膜と
第１の絶縁膜とを選択エッチングして開口を設ける工程
と、全面に第２の絶縁膜を堆積しＲＩＥ法によりエッチ
ングしてゲート開口に側壁を形成してからゲート酸化膜
とゲー■・電極とを形成する工程と、犠牲膜を除去して
から、ゲ− １−電極と側壁とをマスクとしてイオン注
入法によりソースートレインコンタクトを開口し、ソー
スートレイン電極を形成するものである。The method for manufacturing an insulated gate FET of the present invention includes the steps of sequentially depositing a first insulating film and a sacrificial film on the surface of a semiconductor substrate, and selectively etching the sacrificial film and the first insulating film to form an opening. A second insulating film is deposited on the entire surface and etched using the RIE method to form side walls in the gate opening, and then a gate oxide film and a gate electrode are formed. After removing the sacrificial film, a gate electrode is formed. 1 - Using the electrode and sidewall as a mask, a source-train contact is opened by ion implantation to form a source-train electrode.
本発明の第１の実施例について、第１図（ａ）〜（ｄ）
を参照して説明する。Regarding the first embodiment of the present invention, FIGS. 1(a) to (d)
Explain with reference to.
はじめに第１図（ａ）に示すように、Ｐ型シリコン基板
１の表面に絶縁膜２と燐ドープボリシリコン膜などから
なる犠牲膜３とを順次堆積し、ＲＩＥ法により長さ０．
５μｍのゲート開口を形成してからＣＶＤ法により厚さ
０．２μｍの絶縁膜４を形成する。First, as shown in FIG. 1(a), an insulating film 2 and a sacrificial film 3 made of a phosphorus-doped polysilicon film or the like are sequentially deposited on the surface of a P-type silicon substrate 1, and are made to have a length of 0.5 mm by RIE.
After forming a gate opening of 5 μm, an insulating film 4 with a thickness of 0.2 μm is formed by CVD.
つぎに第１図（ｂ）に示すように、ＲＩＥ法により絶縁
膜４をエッチングし、犠牲膜３の側壁に絶縁膜４を残し
、長さ０．３μｍのゲートを開口する。Next, as shown in FIG. 1(b), the insulating film 4 is etched by the RIE method, leaving the insulating film 4 on the side wall of the sacrificial film 3, and opening a gate with a length of 0.3 μm.
つぎに熱酸化法によりゲート酸化膜５を形成する。この
とき犠牲膜３の表面にも薄い酸化膜６が形成される。Next, a gate oxide film 5 is formed by thermal oxidation. At this time, a thin oxide film 6 is also formed on the surface of the sacrificial film 3.
つぎにスバッタ法によりタングステンによるゲート電極
材７を堆積してから側壁４の内法より長く、外法より短
いゲート電極パターンのフォトレジスト８を形成する。Next, a gate electrode material 7 made of tungsten is deposited by a sputtering method, and then a photoresist 8 having a gate electrode pattern that is longer than the inner sidewall 4 and shorter than the outer sidewall 4 is formed.
つぎに第１図（ｃ）に示すように、ＲＩＥ法により塩素
系のガス（ＣＩ！２＋０２混合ガス）を用いてゲート電
極材７をエッチングして、ゲート電極７を形成してから
フォトレジスト８を除去す５
る。Next, as shown in FIG. 1(c), the gate electrode material 7 is etched using a chlorine-based gas (CI!2+02 mixed gas) by the RIE method to form the gate electrode 7, and then the photoresist 8 is etched. Remove 5.
つぎに薄い酸化膜６を除去してから、弗酸硝酸を用いた
ウェットエッチングまたは塩素系ガスを用いたＲＩＥに
より犠牲膜３を除去する。Next, after removing the thin oxide film 6, the sacrificial film 3 is removed by wet etching using hydrofluoric acid and nitric acid or RIE using a chlorine gas.
つぎに第１図（ｄ）に示ずように、側壁を形成している
絶縁膜４およびゲート電極７をマスクとして燐イオン（
３１ｐ＋）を加速エネルギー１５０ｋｅＶ、注入量（ド
ース） Ｉ Ｘ １ ０”ｃｍ−２注入して、層抵抗１
５００Ω／口、接合深さ０．３μ■１のソース１０とド
レイン１１とを形成する。Next, as shown in FIG. 1(d), phosphorus ions (
31p+) was implanted at an acceleration energy of 150 keV and an implantation amount (dose) of I
A source 10 and a drain 11 having a resistance of 500Ω/hole and a junction depth of 0.3 μm are formed.
最後にＰＳＧ膜９を堆積し、ソースートレインコンタク
トを開口してアルミニウムなどからなるソース電極１２
およびトレイン電極１３を形成して素子部が完成する。Finally, a PSG film 9 is deposited, a source-train contact is opened, and a source electrode 12 made of aluminum or the like is formed.
Then, train electrodes 13 are formed to complete the element section.
つぎに本発明の第２の実施例について第２図（ａ′）〜
（ｄ）を参照して説明する。Next, regarding the second embodiment of the present invention, FIG. 2(a') to
This will be explained with reference to (d).
今度はＬＤＤ楕造に適用したものである。This time, it is applied to an LDD elliptical structure.
第２図（ａ）において、絶縁膜４としてたとえば燐を添
加したＰＳＧ膜を用いることにより、第２図（ｄ）にお
いて浅いＮ型領域１０ａ．ｌｌａ６
が形成される。In FIG. 2(a), by using, for example, a PSG film doped with phosphorus as the insulating film 4, shallow N-type regions 10a. lla6 is formed.
本発明においてゲー１・開口に絶縁膜からなる側壁が形
成されているため、側壁の内法に安定した微細なゲート
長が得られる。In the present invention, since the sidewall made of an insulating film is formed in the gate 1 opening, a fine gate length that is stable within the sidewall can be obtained.
ゲー１・開口を０．５μｍとし、絶縁膜の厚さを０．２
μｍとすると、０．３μｍのゲート長が得られることに
なる。Gate 1: The opening is 0.5 μm, and the thickness of the insulating film is 0.2
If it is μm, then a gate length of 0.3 μm will be obtained.
さらにゲート電極が側壁を越えて、外法近くまで上方に
はみ出しているので、ゲート抵抗を低減することができ
る。Furthermore, since the gate electrode protrudes upward beyond the sidewalls to near the outer edge, gate resistance can be reduced.
第１図（ａ）〜（ｄ）は本発明の第１の実施例を工程順
に示す断面図、第２図（ａ）〜（ｄ）は本発明の第２の
実施例を工程順に示す断面図、第３図（ａ）〜（ｄ）は
従来技術による絶縁ゲート型ＦＥＴを工程順に示す断面
図。
１・・・Ｐ型シリコン基板、２・・・絶縁膜、３・・・
犠牲膜、４・・・絶縁膜、５・・・ゲート酸化膜、６・
・・薄い酸化膜、７・・・ゲート電極、８・・・フォト
レジスト、９・・・ＰＳＧ膜、１０・・・ソース、１１
・・・ドレイン、１２・・・ソース電極、１３・・・ト
レイン電極、１４・・ゲート長。FIGS. 1(a) to (d) are cross-sectional views showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (d) are cross-sectional views showing the second embodiment of the present invention in the order of steps. 3(a) to 3(d) are cross-sectional views showing an insulated gate FET according to the prior art in the order of steps. 1... P-type silicon substrate, 2... Insulating film, 3...
Sacrificial film, 4... Insulating film, 5... Gate oxide film, 6.
... Thin oxide film, 7... Gate electrode, 8... Photoresist, 9... PSG film, 10... Source, 11
...Drain, 12...Source electrode, 13...Train electrode, 14...Gate length.
Claims (1)
成され、上方で前記側壁の内法をはみ出し、外法より短
いゲート電極が形成されていることを特徴とする絶縁ゲ
ート型ＦＥＴ。 ２、側壁直下の半導体基板表面に浅いＮ型領域が形成さ
れていることを特徴とする請求項１記載の絶縁ゲート型
ＦＥＴ。 ３、半導体基板表面に第１の絶縁膜と犠牲膜とを順次堆
積し、犠牲膜と第１の絶縁膜とを選択エッチングして開
口を設ける工程と、全面に第２の絶縁膜を堆積しＲＩＥ
法によりエッチングしてゲート開口に側壁を形成してか
らゲート酸化膜とゲート電極とを形成する工程と、前記
犠牲膜を除去してからゲート電極と側壁とをマスクとし
てイオン注入法によリソース−ドレインコンタクトを開
口し、ソース−ドレイン電極を形成することを特徴とす
る絶縁ゲート型ＦＥＴの製造方法。[Claims] 1. A pair of side walls made of an insulating film are formed on the surface of the semiconductor substrate, and a gate electrode is formed above the inner wall of the side wall and shorter than the outer wall. Insulated gate type FET. 2. The insulated gate FET according to claim 1, wherein a shallow N-type region is formed on the surface of the semiconductor substrate directly under the sidewall. 3. Sequentially depositing a first insulating film and a sacrificial film on the surface of the semiconductor substrate, selectively etching the sacrificial film and the first insulating film to form an opening, and depositing a second insulating film on the entire surface. R.I.E.
A step of forming a gate oxide film and a gate electrode after forming a sidewall in the gate opening by etching using a method, and a step of removing the sacrificial film and then using an ion implantation method to remove a resource using the gate electrode and sidewall as a mask. A method for manufacturing an insulated gate FET, which comprises opening a drain contact and forming a source-drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009712A JPH03214739A (en) | 1990-01-19 | 1990-01-19 | Insulated gate type fet and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009712A JPH03214739A (en) | 1990-01-19 | 1990-01-19 | Insulated gate type fet and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03214739A true JPH03214739A (en) | 1991-09-19 |
Family
ID=11727868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009712A Pending JPH03214739A (en) | 1990-01-19 | 1990-01-19 | Insulated gate type fet and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03214739A (en) |
-
1990
- 1990-01-19 JP JP2009712A patent/JPH03214739A/en active Pending
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