JPH03214772A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a specific capacitor to be formed without increasing the element space by a method wherein a conductive layer for capacitor formed in the not-yet used wiring region in a wiring region is connected to an element formed in an element region. CONSTITUTION:When it is anticipated that the capacitor stabilizing the inner reference voltage (a) will run short due to the restricted space, etc., of the arrangement region and others from the beginning of design, an Al layer 48 for capacitor is to be formed in the not-yet used wiring region 46 in a wiring region 4. That is, the Al layer 48 formed on an n type epitaxial layer 8 through the intermediary of a silicon oxide film 14 is connected to the capacitor electrode 34 of a capacitor 36 formed on a macro region 2 through the intermediary of a wiring layer 50 and the second layer wiring layer 52 comprising Al. Thus, a capacitor 54 having capacity C2 given by the Al layer 48, the wiring layer 50 and the second layer wiring layer 52 can be formed. Accordingly, a base electrode 18 of a transistor 22 is connected to the pn junction capacity IC of a capacitor 36 and the wiring capacity C2. Through these procedures, specific C1+C2 can be given to the capacitor 36 without increasing the element space.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor device, and particularly to a semiconductor device in which an element region where an element is formed and a wiring region where a wiring layer is formed are separated, without increasing the element area and improving reliability. The purpose of the present invention is to provide a semiconductor device in which a capacitor of a desired capacitance can be formed without deteriorating the performance. In the semiconductor device, a conductive layer for a capacitor is formed in an unused area of the wiring region, and the conductive layer for the capacitor is connected to an element formed in the element region.

[Industrial Field of Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an element region where an element is formed and a wiring region where a wiring layer is formed are separated.

2 [Conventional technology] In recent years, various types of capacitors have been used, such as capacitors for stabilizing the internal reference voltage of LSI (semiconductor integrated circuits) and AC (alternating current) coupling capacitors for increasing the speed of circuits. In some cases, a large capacitor is required.

Such capacitors are typically provided in the bulk layer with p
- It is formed by the junction capacitance of the n junction.

For example, a case of a gate array having a capacitor for stabilizing an internal reference voltage will be explained.

FIG. 4 <a) is a plan view showing a conventional gate array, FIG. 4 <b> is a schematic cross-sectional view taken along line A-A, and FIG. 4(c)
is its equivalent circuit diagram.

Elements are formed in the macro region 2 of the gate array. That is, the n-type epitaxial layer 8 is formed on the n-type diffusion layer 6.
is formed on the surface of this n-type epitaxial layer 8.
A type base region 10 is formed, and an n-type emitter region 12 is further formed on the surface of this p-type base region 10. In addition, these mouth-type epitaxial layer 8, p-type base region 1
A silicon oxide film 1 is formed on the 0 and n type emitter regions 12.
A collector electrode 16, a base electrode 18, and an emitter electrode 20 are connected through contact holes opened in 4, respectively.
is formed. In this way, the transistor 22 is formed.

Furthermore, a p-type resistance region 24 is provided on the surface of the n-type epitaxial layer 8.
is formed, and a resistor made of A1 [! 26, 28
is formed. In this way, the resistor 30 is formed.

Furthermore, a p-type capacitor region 32 is formed on the surface of the n-type epitaxial layer 8 so as to reach the n-type diffusion layer 6.
A -n junction is formed, and a capacitor electrode 34 made of Aj is formed on this p-type capacitor region 32 through a contact hole opened in the silicon oxide film 14. The pn junction capacitance C thus formed in the bulk layer
A capacitor 36 having a value of 1 is formed.

And the collector electrode 16 and base electric potential fi! of the transistor 22! 18 are connected via wiring layers 38 and 40, respectively.
It is connected to the resistor fi 26 of the resistor 30 and the capacitor electrode 34 of the capacitor 36.

Capacitor 36 having p-n junction capacitance C1 at this time
is used as a capacitor to stabilize the internal reference voltage.

On the other hand, in the wiring region 4, first wiring layers 42 and 44 are formed to connect the elements formed in the macro region 2, and at the same time, an unused wiring region 46 exists between them.

Next, a case of a gate array having an AC coupling capacitor for increasing the speed of the circuit, for example, will be explained.

FIG. 5(a) is a plan view showing a conventional gate array;
Figure (b) is its equivalent circuit diagram.

In the macro region 2 of the gate array, a collector electrode 56,
A transistor 62 is formed having a base electrode 58 and an emitter electrode [i60]. Moreover, the resistance electrodes 64, 6
6 is formed. Further, a capacitor 7 having a p-n junction capacitance C3 formed in the bulk layer
0 is formed.

And 1. Collector voltage f of transistor 62! 56 is connected to the capacitor electrode 7 of the capacitor 70 via the wiring layer 72.
4 is connected. Further, the emitter electrode 60 is connected to the resistor electrode [i64] of the resistor 68 via the wiring layer 76, and is connected to the internal gate input/output via the wiring layer 78 and the second wiring layer 80. . P- at this time
Capacitor 70 having n-junction capacitance C3 is used as an AC coupling capacitor for speeding up the circuit.

On the other hand, in the wiring region 4, first wiring layers 82, 84, 86
, 88 are formed, and a second wiring layer 90 connects them.
, 92 are formed. At the same time, wiring unused areas 94, 96, 98, and 100 exist between them.

[Problems to be Solved by the Invention] However, in the conventional gate array described above, for example, the capacitor C1 for stabilizing the internal reference voltage and the AC coupling capacitor C3 for increasing the speed of the circuit have larger capacitances than originally designed. If necessary, p
A method of increasing the junction area of the -n junction has been used. That is, when forming a P-type capacitor region on the surface of the n-type epitaxial layer 8 to reach the n-type diffusion layer 6, in contrast to the conventional p-type capacitor region 32 as shown in FIG. As shown in FIG. 6(a), a p-type capacitor region 32a is formed by increasing its area. Accordingly, the capacitor electrode 34a also has a larger area than the conventional capacitor electrode 34. Therefore, the element area becomes large, creating a space problem that becomes a factor in increasing the degree of integration.

Furthermore, by increasing the impurity concentration of the conventional n-type diffusion layer 6 and p-type capacitor region 32 as shown in FIG. 7(a), the n-type diffusion layer 6b as shown in FIG. 7(b) is added. and p
Although there is a method of increasing the junction capacitance of the pn junction by forming a type capacitor region 32b, in this case, defects etc. are likely to occur in the silicon crystal. Therefore, reliability problems such as deterioration of the characteristics of the element and reduction in reliability have occurred.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device in which a capacitor of a desired capacity can be formed without increasing the element area or reducing reliability.

[Means for Solving the Problems] The above problem is to solve the above problems in a semiconductor device having an element region where an element is formed and a wiring region where a wiring layer connecting the elements is formed. This is achieved by a semiconductor device characterized in that a conductive layer for a capacitor is formed, and the conductive layer for a capacitor is connected to an element formed in the element region.

The present invention is also achieved by the semiconductor device described above, characterized in that the conductive layer for the capacitor is connected to a Pn junction capacitor formed in the element region.

[Function] That is, in the present invention, a conductive layer for a capacitor is formed by utilizing an unused area of a wiring area, that is, an empty area, so that the device area does not increase or reliability decreases. There's nothing to do. Further, by connecting this conductive layer for a capacitor with an element formed in the element region, wiring capacitance of the conductive layer can be added to the element. Furthermore, by connecting this capacitor conductive layer to a pn junction capacitor formed in the element region, a large capacitance capacitor can be formed.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 1(a) is a plan view showing a gate array according to the first actual fiber example of the present invention, FIG. 1<b> is a schematic cross-sectional view taken along line AA", and FIG. It is.

In the case of a gate array, a macro region 2 in which elements are formed and a wiring region 4 in which signal lines connecting the elements in the macro region 2 are wired are separated in advance. Therefore, in the macro region 2, for example, an n-type epitaxial layer 8 is formed on the n-type diffusion layer 6;
A p-type base region 10 is formed on the surface, and an n-type emitter region 12 is further formed on the surface of this p-type base region 10. A collector electrode 16 made of A1 and a base electrode 18 are connected to the n-type epitaxial layer 8, the p-type base region 10, and the n-type emitter region 12 through contact holes opened in the silicon oxide film 14, respectively.
and an emitter electrode 20 are formed. In this way, a transistor 22 is formed.

Similarly, a p-type resistance region 24 is formed on the surface of the n-type epitaxial layer 8, and an A.D. Resistance electrodes 26 and 28 made of II are formed. In this way, the resistor 30 is formed.

Similarly, a p-type capacitor region 32 is formed on the surface of the n-type epitaxial layer 8 so as to reach the n-type diffusion layer 6, thereby forming a p-n junction.

Then, on this p-type capacitor region 32, A'
A capacitor t[. 34 is formed. In this way, a capacitor 36 having a p1n junction capacitance C1 formed in the bulk layer is formed.

The collector electrode 16 and base electrode 18 of the transistor 22 are respectively A. Wiring layers 38, 4 consisting of
0, the resistive electrode 26 of the resistor 30 and the capacitor 3
It is connected to the capacitor electrode 34 of No. 6. The capacitor 36 having the pn junction capacitance C1 at this time is used as a capacitor for stabilizing the internal reference voltage.

On the other hand, in the wiring area 4, signal lines are wired, but in this case, there always appears an area 11 where the wiring is not used. For example, while the first wiring layers 42 and 44 made of Aj are formed, an unused wiring area 46 exists between them.

Let's assume that a capacitor for stabilizing the internal reference voltage was included from the beginning of the design. If a capacity shortage is expected due to constraints on the placement area or other space, an AJl layer 48 for a capacitor is formed in an unused wiring area 46 of the wiring area 4. That is, on the n-type epitaxial layer 8, the A.I. 0 layer 48 is formed. The capacitor electrode 34 of the capacitor 36 formed in the macro region 2 and the A. Connection is made through a wiring layer 50 consisting of 0 and a second wiring layer 52.

Thus A. 0 layer 48, wiring layer 50 and second wiring layer 5
A capacitor 54 having a wiring capacitance C2 of 2 is formed. And the base voltage of transistor 22 'J#l18
By connecting the p-n junction capacitance C1 of the capacitor 36 and the wiring capacitance C2 of the capacitor 54, the capacitor for stabilizing the internal reference voltage has a desired capacitance value C1+C.
It becomes 2.

12 In the case of a gate array, since the wiring widths of the first wiring layers 42 and 44 in the wiring area 4 are limited to several types, the capacitor A' formed in the wiring unused area 46 is
If the width of the layer 48 is also limited to a specific width, that is, if it is a dummy wiring pattern, the A. The Q layer 48 can be formed simultaneously with the first wiring layers 42, 44, etc., and can be formed mainly in the A. The wiring capacitance C2 can be easily controlled by the length of the G layer 48.

In this way, according to the first embodiment, the unused wiring area that inevitably occurs in the wiring area 4 is utilized, and the A. By forming the Q layer 48, A. ! By adding the wiring capacitance C2 of the capacitor 54 formed by the first layer 48, etc., the capacitor for stabilizing the internal reference voltage can be made to have a desired capacitance value Ci102. By using these two capacitors 36 and 54 in combination, it is possible to increase the capacity efficiently.

1 3 At this time, by making the width of the wiring capacitance C2 equal to the wiring width of the other first wiring layers 42, 44, etc., the l layer 48 for the capacitor can be easily formed. , A'' layer 48 can easily control the capacitance value.

Another advantage is that capacitors can be formed anywhere as long as the wiring is not used.

Next, a second embodiment of the present invention will be described using FIG.

FIG. 2(a) is a plan view showing a gate array according to a second embodiment of the present invention, and FIG. 2(b) is an equivalent circuit diagram thereof.

In the macro region 2 of the gate array, a transistor 62 having a collector electrode 56, a base electrode 58, and an emitter electrode 60 is formed in the same manner as in FIG. 1 above.

Further, a resistor 68 having resistive electrodes 64 and 66 is formed. Furthermore, the p-n junction capacitance C formed in the bulk layer
3 is formed.

The collector electrode 56 of the transistor 62 is connected to the capacitor electrode 74 of the capacitor 70 via the 1 4 wiring layer 72 . Further, the emitter electrode 60 is connected to the resistance voltage [!] of the resistor 68 via the wiring layer 76. 64, and also connected to the internal gate input/output via the wiring layer 78 and the first wiring layer 80. The capacitor 70 having the pn junction capacitance C3 at this time is used as an AC coupling capacitor for increasing the speed of the circuit.

On the other hand, in the wiring region 4, first wiring layers 82, 84, 86
, 88 are formed, and a second wiring layer 90 connects them.
, 92 are formed, and at the same time, unused wiring areas 94, 96, 98, and 100 exist between them.

Now, hypothetically, the AC coupling capacitor for speeding up is
If a capacity shortage is predicted from the beginning of the design due to layout area or other space constraints, the first wiring layers 82, 84, 86, 88 are placed in the unused wiring area 100 of the wiring area 4.
An A1 layer 102 for a capacitor having the same wiring width as the above is formed. And A. for this capacitor. Capacitor voltage @74 of capacitor 70 formed in Q layer 102 and macro region 15 region 2
are connected via the wiring layer 104 and the second wiring layer 106.

In this way, a capacitor 108 having a wiring capacitance C4 is formed by the AA layer 102 and the like. and transistor 62
By connecting the p-n junction capacitance C3 of the capacitor 70 and the wiring capacitance C4 of the capacitor 108 to the collector electrode 56, the AC coupling capacitor for speeding up has a desired capacitance value C3+C4.

In this manner, according to the second embodiment, the Aj layer 1 for the capacitor is formed by utilizing the unused wiring area that inevitably occurs in the wiring area 4.
02 etc., the p-
By adding the wiring capacitance C4 to the n-junction capacitance C3, the AC coupling capacitor for increasing the speed of the circuit has the desired capacitance value C.
3-1-C4. And this 2
By using two capacitors together, it is possible to efficiently increase the capacity.

16 Next, a third embodiment of the present invention will be described using FIG.

FIG. 3(a) is a plan view showing a gate array according to a third embodiment of the present invention, and FIG. 3(b) is an equivalent circuit diagram thereof.

Note that the same components as those of the gate array shown in FIG. 2 are given the same reference numerals and their explanations will be omitted.

In the macro region 2 of the gate array, in the same manner as in FIG.
66 is formed. The emitter electrode 60 of the transistor 62 is connected to the resistor electrode [i64] of the resistor 68 via the wiring layer 76, and is also connected to the internal gate input/output via the wiring layer 78 and the first wiring layer 80. There is.

On the other hand, in the wiring region 4, first wiring layers 82, 84, 86
, 88 are formed, and second wiring layers 90, 92 are formed to connect them, and at the same time, unused wiring areas 94, 96, 98, 100 exist between them.

Then, A1 layers 102 and 110 for capacitors are formed in the wiring unused areas 100 and 94 of the wiring area 4, respectively.
Connection is made via the second wiring layer 112. And A. for this capacitor. The Il layer 102 and the collector voltage 'Ifl56 of the transistor 62 are connected via the wiring layer 114 and the second wiring layer 106.

In this way, the wiring capacitance C is reduced by the AJI layers 102, 110, etc.
A capacitor 116 having a capacitance of C5 is formed and connected to the collector electrode 56 of the transistor 62, thereby becoming an AC coupling capacitor with a desired capacitance value C5 for speeding up. If a capacitance value larger than the wiring capacitance C5 is required as an AC coupling capacitor for high speed, for example, a capacitor AJ is installed in the unused wiring area 96.
An I layer is formed, and a capacitor A. It may be connected to the 0 layer 110. In this way, the required capacitance value can be obtained.

In this way, according to the third embodiment, no p-n junction capacitor is formed in the bulk layer of the macro region 2, and capacitor A is formed only in the unused region of the wiring region 4.
By forming the p-layers 102, 114, etc., it is possible to form a high-speed AC coupling capacitor having a desired capacitance value C5 without increasing the device area.

The capacitance value C5 of this wiring capacitance can also be easily controlled in a subsequent process.

In the first to third embodiments described above, the explanation is made using a gate array, but the invention is not limited to this, and a semiconductor in which a region where an element is formed and a wiring region where a wiring layer is formed are separated to a certain extent. The present invention can be applied to any device.

[Effects of the Invention] As described above, according to the present invention, in a semiconductor device having an element region in which an element is formed and a wiring region in which a wiring layer connecting the elements is formed, a capacitor is provided in an unused area of the wiring region. By forming a conductive layer for the capacitor and connecting the conductive layer for the capacitor to the element formed in the element region, a desired wiring capacitance by the conductive layer can be added to the element.

Thereby, a desired capacitor can be formed without increasing the element area or reducing reliability.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a gate array according to a first embodiment of the invention, FIG. 2 is a diagram showing a gate array according to a second embodiment of the invention, and FIG. 3 is a diagram showing a third embodiment of the invention. FIGS. 4 and 5 are diagrams showing conventional gate arrays, respectively. FIGS. 6 and 7 are diagrams for explaining conventional gate arrays. In the figure, 2... Macro region, 20 4... Wiring region, 6... N-type diffusion layer, 8... N-type epitaxial layer, 10...・・・・・・
・P-type base region, 12...N-type emitter region, 14...Silicon oxide film, 16, 56...Collector electrode, 18, 58...
...Base electrode, 20, 60...Emitter electrode, 22, 62...
...Transistor, 24...P-type resistance region, 26, 28, 64, 66...Resistance electrode, 30,
68...Resistance, 32...P-type capacitor region, 34, 74...
...Capacitor electrode, 36, 54, 70, 108,
116... Capacitor, 38, 40, 50, 72, 76, 78, 104, 114
...Wiring layer, 42, 44, 82, 84, 86, 88...1st layer 91st wiring layer, 46, 94, 96, 98, 100...No wiring Usage area: 48, 102, 110...A'' layer, 52, 80
, 90, 92, 106, 112... Second wiring layer.

Claims (1)

[Claims] 1. In a semiconductor device having an element region for forming an element and a wiring region for forming a wiring layer connecting the elements, a conductive layer for a capacitor is provided in an unused area of the wiring region. A semiconductor device, wherein the conductive layer for the capacitor is connected to an element formed in the element region. 2. The semiconductor device according to claim 1, wherein the capacitor conductive layer is connected to a pn junction capacitor formed in the element region.