JPH03214773A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the deterioration in performances by junction leakage etc. due to the process contamination of a semiconductor device by a method wherein a semiconductor element is formed on an SOI (Silicon On Insulator) formed on an insulating layer provided on a holding substrate. CONSTITUTION:The title semiconductor device is provided with a semiconductor holding substrate 1, a defective layer 2 formed of numerous defects D, an intersubstrate insulating layer 3, an SOI substrate 4 wherein a semiconductor element is formed, a hole or groove 5 and a buried semiconductor layer 6. At this time, the contaminants e.g. Fe<+> etc., permeating into the SOI substrate 4 in every heat treatment process are shifted to semiconductor holding substrate 1 through the intermediary of the semiconductor layer 6 buried in the hole or groove 5 passing through the SOI substrate 4 and the insulating layer 3 while the upper part side of the layer 6 is in direct contact with the SOI substrate 4 on the other hand, the lower end part of the buried semiconductor layer 6 is also in contact with the semiconductor holding substrate 1 so that contaminants may successively reach the defect separating layer 2 in the holding substrate 1 to be trapped by the defects D. Through these procedures, the SOI substrate 4 can be cleaned up by decreasing the contaminants so that deterioration in performances by junction leakage, etc., due to the contaminants in the semiconductor element formed on the SOI substrate 4 may be avoided.

Description

[Detailed Description of the Invention] [Summary] Regarding semiconductor devices, particularly SOI structure semiconductor devices equipped with IG means, the aim is to improve the performance and reliability of SOI structure semiconductor devices, and to prevent the formation of defective layers. an insulating layer formed on the supporting substrate, an SOI substrate provided on the insulating layer, and a hole or hole penetrating the SOI substrate and the insulating layer and reaching into the supporting substrate. has a groove and a semiconductor layer filled in the hole or groove, and has a structure in which a semiconductor element is formed on the SOI substrate.

[Industrial application field]

The present invention relates to semiconductor devices, particularly IG (Intrinsic
S O I (S
The present invention relates to a semiconductor device having an ilicon on insulator structure.

In recent years, by forming semiconductor elements on a semiconductor substrate (SOI substrate) disposed on a semiconductor support substrate via an insulating layer, element performance has been improved by reducing parasitic capacitance, and performance deterioration due to parasitic elements (for example, latch-up) has been improved. ) and improved radiation resistance by separating the supporting substrate part.
Semiconductor devices with an OI structure have been provided, but even in semiconductor devices with an SOI structure, reductions in yield and reliability due to contamination during the process have become apparent as elements become smaller, and countermeasures are desired.

[Conventional technology]

In semiconductor devices in which elements are formed on a normal semiconductor substrate, IG (In-trinsic
A method called ``Gettering'' is used. This is a technology that passivates contaminants, especially heavy metals, by forming defects deep within the substrate and trapping the contaminants in the defects.

As manufacturing technology advances, the level of process contamination is decreasing, but as elements become smaller, the allowable contamination level also decreases, so in order to maintain high performance in DRAM etc. The current situation is that we have no choice but to rely on them.

On the other hand, in recent years, semiconductor devices with the SOI structure have been provided due to their advantages such as excellent radiation resistance, improved transistor performance, and ability to prevent defects due to parasitic elements. Semiconductor substrate (
Because there is an insulating layer below the element substrate (element substrate) that separates it from the support substrate, even if a defective layer is created on the support substrate, as in the case of a normal semiconductor device in which elements are formed on the semiconductor substrate surface,
Contaminants that have entered the device substrate during processing cannot be trapped within the defect layer.

[Problem to be solved by the invention]

Therefore, in conventional SOI structure semiconductor devices, IG means have not been applied, and therefore, when microscopic elements sensitive to small-level contamination are disposed, performance and reliability due to the process contamination may be affected. There was a marked decline in sexuality.

Therefore, the present invention provides a So
The purpose of the present invention is to provide a structure for a Sol structure semiconductor device and to improve the performance and reliability of a Sol structure semiconductor device.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the same figure, l is a semiconductor support substrate, 2 is a large number of defects D
3 is an inter-substrate insulating layer, 4 is a Sol substrate on which a semiconductor element is formed, 5 is a hole or groove, 6 is a defect layer in which a defect layer is formed;
indicates a buried semiconductor layer.

As shown in FIG. 1, the problem is as follows: a semiconductor support substrate (1) on which a defective layer (2) is formed; an insulating layer (3) formed on the support substrate (1); S provided above
an OI substrate (4), the SOI substrate (4) and the insulating layer (
3) having a hole or groove (5) penetrating through the support substrate (1) and a semiconductor layer (6) filled in the hole or groove (5), the Sol substrate (4) This problem is solved by a semiconductor device according to the present invention in which a semiconductor element is formed in a semiconductor device.

[For production]

That is, in the structure of the present invention, contaminants such as iron (Fe+) that have entered the SOI substrate (4) during the process penetrate through the SOI substrate (4) and the insulating layer (3) each time the heat treatment is performed. A semiconductor supporting substrate with which the bottom end of the buried semiconductor layer (6) is in direct contact via a buried semiconductor layer (6) which is buried in a hole or groove (5) and whose upper side surface is in direct contact with the SOI substrate (4). (1), and sequentially reaches the defect precipitation layer (2) in the supporting substrate (1), and the defect (
D) is trapped.

Therefore, the amount of contaminants in the Sol substrate (4) is reduced and the surface becomes clean, thereby preventing performance deterioration of semiconductor elements formed on this SO substrate (4) due to junction leakage caused by contaminants. be done.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 2 shows an embodiment of the present invention in a DRAM. Formula plan view (a), sectional view taken along the line A-A (b), and Figure 3 (a) -
(h) is a process cross-sectional view of the method for forming the SOI substrate according to the above example.

Identical objects are designated by the same reference numerals throughout the plan.

A Sol structure DRAM to which the present invention is applied, for example,
As shown in FIGS. (a) and (b), for example, on a Si supporting substrate body 11 having a defect layer l2 in which defects (D) are deposited at a high density over the entire area in the surface direction and the thickness direction, Silicon oxide (
SOI in which elements are formed through an insulating film 13
A p-type Si element base 14 having a thickness of about 0.3 to 0.5 μm is laminated as a base, and the element base 14 includes memory regions 19A, 19B, etc. in which memory elements are arranged, and peripheral circuits that drive the memory. Peripheral area 2OA where elements are arranged
, 20B, etc. Within the dicing line 17 used to individually divide the chip regions 18A, 18B, etc.,
Element substrate l4 and inter-substrate Sin2 insulating film 13 below it
For example, two rows of trenches 15 are formed that penetrate through the support substrate 11 and reach into the support substrate 11, and the trenches 15 are filled with a phosphorus-doped poly-Si buried layer 16 that reaches from the bottom surface to the opening surface. An SOI substrate is used. Then, in the area defined by the field oxide film 23 for element isolation in the memory area 19A of the chip area 18A of the element substrate l4, for example, a gate oxide film 24 and an upper n+ type poly-Si etc. are formed. A word line 25A, a cell transistor consisting of an n1 type source/drain (S/D) region 26A and an n+ type charge storage region 26B formed in a self-aligned manner on the word line 25A, and a cell transistor made of n+ type poly-Si to store the above charge. The adjacent word line 2 is connected to the self-element word line 25A, which is in contact with the storage layer 26B and on which the SiO2 insulating film 27 with a thickness of about IOOOA is deposited.
A charge storage electrode 28 extending over the charge storage electrode 28 and a silicon nitride (Si) layer formed on the surface of the charge storage electrode 28
a dielectric film 29 with a thickness of about 200 A made of sNa) film,
and a capacitor consisting of a counter electrode 30 made of n+ type poly Si or the like which covers the charge storage electrode 28 via the dielectric film 29, and the S via the contact window 32A of the interlayer insulating film 3l covering the element formation surface A memory element 34 is formed by a bit line 33A made of aluminum (Aβ) or the like in contact with the /D region 26A.

Further, for example, in the area defined by the field oxide film 23 for isolation between elements in the peripheral area 20B of the chip area 18B,
For example, a gate oxide film 24, a gate electrode 25C1 made of n+ type poly-Si or the like on the gate oxide film 24, formed at the same time as the word line 25A, and an S/D region of the memory element 34 in self-alignment with the gate electrode 25C. Consisting of an n+ type source region 26C and an n+ drain region 26D formed simultaneously with the 2f3A and n1 type charge storage region 26B,
The source region 26C and the drain region 26 are connected to each other through the contact windows 32B and 32C of the interlayer insulating film 3l covering the element.
A peripheral transistor 35 is formed from which a source wiring 33B and a drain wiring 33C such as Aβ in contact with D are led out.

With this structure, contaminants such as heavy metal contaminants such as iron (Fe'') that have invaded the surface of the SOI substrate, that is, the Si element substrate 14 during the process of forming the memory element 34 and the peripheral transistor 35, can be removed by dicing. The upper side surface of the groove 15 provided in the line l7 is in direct contact with the St element substrate l4, and the lower side surface and bottom surface are in direct contact with the support substrate 11.
The defect precipitation region 12 of the support substrate 11 is connected to the buried poly 9 directly in contact with the defect layer 12 of the support substrate 11 via the silicon layer 16.
The amount of contaminants such as heavy metals in the Si element substrate (SOI substrate) 14 after the completion of the process in which the memory element and peripheral transistors are formed is greatly reduced. .

Therefore, in the DRAM shown in the above embodiment, it has become possible to extend the retention time more than three times that of the conventional one.

Next, a method for forming the SOI substrate used in the above embodiment will be described for one embodiment with reference to process cross-sectional views.

Refer to FIG. 3(a). First, an ordinary Si support substrate l1 formed by the CZ method is repeatedly heated to about 800 to 1100°C in a non-oxidizing atmosphere, and Defects (D) are formed by precipitating oxygen over the entire area. (12
(indicates a defective region) Referring to FIG. 3(b), a second, for example, p-type Si substrate 114, which will become an element substrate (Sol substrate), is heated to a thickness of 10? by thermal oxidation. For example, about 2,000 to 3,000 thermal oxide films 113 are formed.

Referring to FIG. 3(C), the second p-type St is then placed on the p-type Si support substrate 11.
The substrate 1l4 is inverted and placed with the thermal oxide film 113 facing down, and a thermal oxide film is formed on the p-type St support substrate 11 by an electrostatic deposition method in which an electrostatic pulse is applied between the substrates while pressing the substrates together. A second p-type Si substrate 114 is attached via 113.

Referring to FIG. 3(d), the second p-type Si substrate 114 is then polished from the back side to a thickness of, for example, 0.3 to 0.5 μm, which is suitable for use as an element substrate. Here, a p-type Si element substrate 14 with a thickness of 0.3 to 0.5 μm is placed on the p-type St support substrate 11 via an inter-substrate SiO2 insulating film 13 consisting of a thermal oxide film 113.
An SO'I substrate having a structure similar to the conventional one is formed, in which the wafers are laminated.

Referring to FIG. 3(e), next, in the method according to the present invention, a thermal oxide film 36 with a thickness of about 300 Å is formed on the p-type Si element substrate 14 with a thickness of 11 mm. Then, chemical vapor deposition (C
VD) SiO2 film 37 is formed, then a poly-Si film 38 with a thickness of about 2000A is formed by CVD method, and then a phosphosilicate glass (P) film with a thickness of about 3000A is formed by CVD method.
SG) film 39 is formed, and then the inside of the dicing line 17 of the p-type Si element substrate 14 is formed by normal photolithography.
P-type Si passes through the D-SiOz film 37 and the thermal oxide film 36.
An etching opening 40 exposing the element substrate 14 surface is formed.

Referring to FIG. 3(f), the element substrate 14 exposed in the etching opening 40 is selectively removed using the PSG film 39 as a mask by ordinary anisotropic dry etching means. The inter-substrate SiO is exposed in the etching opening 40 using the film 38 as a mask. The film 13 is selectively removed (the PSG film 39 on the polySt film 38 is also removed), and then the poly-Si film 38 is removed by anisotropic dry etching means to form a CVD-Sx02
The membrane 37 is exposed. At this time, the surface of the Si supporting substrate 11 exposed in the etching opening 40 is etched l2? As a result, a recess 41 is formed. Incidentally, here, Si is applied to the Si element substrate l4 by penetrating the lower intersubstrate SiO2 film 13.
A groove 15 reaching into the support substrate 11 is formed.

Referring to FIG. 3(g), a phosphorus-doped polySt layer, for example, is formed on the substrate to a thickness that completely fills the groove 15, and the polySi layer on the CVD-SiO film 37 is removed by well-known etch-back means. By selectively removing and over-etching, a phosphorus-doped poly-Si buried layer 16 having a height approximately equal to the upper surface of the St element substrate 14 is selectively formed in the groove l4.

Referring to FIG. 3 (11), the CVD-SiO film 37 on the upper surface and the thermal oxide film 36 below it are removed by well-known wet or dry etching means to form a Si element in which a semiconductor element according to the present invention is formed. A base (SOI base) 14 and a Si supporting substrate 11 having a defect layer 12 are buried in a groove 15 penetrating the element base 14 and the inter-substrate SiO2 insulating film 13 below it and reaching into the Si supporting substrate 11. An SOI substrate according to the present invention, similar to that used in Example 13 above, is completed, communicating through the embedded poly-Si layer 16.

Thereafter, as shown in FIG. 2, semiconductor elements such as memory elements and transistors are formed on the Si element base of the SOI substrate according to a normal manufacturing process.
At this time, contaminants that enter during the process move into the support substrate through the poly-Si layer in the groove that reaches the support substrate, and are trapped in the defects formed there and become passivated. , the inside of the element substrate is cleaned, so
Performance deterioration such as junction leakage due to contaminants of the semiconductor element formed within the element base is prevented. As mentioned above, in DRAM, the retention time is more than three times that of the conventional one.

Note that the SOI substrate used in forming the SOI substrate according to the present invention
The method for forming the I-substrate (element substrate) is not limited to the method of bonding two substrates together as used in the above example, but may also include recrystallization of a polySt layer formed on an inter-substrate insulating film by laser irradiation. Of course, it may be formed by a method such as 14 or a SIMOX method.

Furthermore, the same effect as described above can be obtained even if the defect layer is formed not over the entire area of the supporting substrate but only in a part thereof, and the buried poly-Si layer in the through groove does not reach the defect layer.

In addition, in the embodiments of the method for forming a semiconductor device and an SOI substrate, the number of grooves in which the poly-Si layer formed on the dicing line is embedded is set to 1 to 2 for ease of illustration.
As explained in the book, in an actual SOI structure semiconductor device, the number of grooves described above is formed within a dicing line from several to several tens of grooves with a width of about 1 μm.

Furthermore, in the examples, grooves were used to connect the element substrate and the support substrate, but this connection may also be made using holes, and the connection portion is not limited to within the dicing line, but may be made within the chip area. Of course, there is nothing wrong with that.

〔Effect of the invention〕

As explained above, according to the present invention, performance deterioration such as junction leakage due to process contamination of the SOI structure is prevented. DRAM and COD
It is effective in improving the performance and reliability of

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a schematic diagram of an embodiment of the present invention in a DRAM, fa) is a plan view, (b) is a sectional view taken along the line A-A, and FIG. a) to (hj) are process cross-sectional views of an embodiment of the method for forming an SOI substrate according to the present invention. Hole or groove, l 6 6 indicates a buried semiconductor layer. l 7 '-y--no

Claims (1)

[Claims] 1. A support substrate (1) made of a semiconductor on which a defect layer (2) is formed; an insulating layer (3) formed on the support substrate (1); an SOI substrate (4) made of a semiconductor provided; a hole or groove (5) that penetrates the SOI substrate (4) and the insulating layer (3) and reaches into the support substrate (1); and the hole or groove. A semiconductor device comprising: (5) a semiconductor layer (6) filled therein, and a semiconductor element is formed on the SOI base (4). 2. The semiconductor device according to claim 1, wherein the hole or groove is formed on a dicing line.