JPH03214867A - Synchronizing signal detection circuit - Google Patents

Abstract

PURPOSE:To obtain a vertical synchronizing signal with a fixed phase relationship without being affected by an external condition by digitally detecting a vertical synchronizing signal. CONSTITUTION:At a equalized pulse detector 1, a signal Sa formed by taking out the leading edge part of a horizontal synchronizing signal detected from a digital video signal of a D2 standard, and a signal Sb formed by taking out the leading edge part of the horizontal synchronizing signal detected from the digital video signal of the D2 standard and the leading edge part of an equalized pulse, are supplied, and an equalized pulse Sd is outputted by the exclusive OR of the signals Sa and Sb. At a horizontal synchronizing detector 2, a horizontal synchronizing signal Se is outputted only when the time difference of the signal Sa and a signal Sc, formed by taking out the trailing edge part of the horizontal synchronizing signal detected from the digital video signal of the D2 standard and the trailing edge part of the equalized pulse, is coincident with the time difference other than a vertical synchronization period. At a counter 3, the pulse Sd is counted only when the signal Se is not inputted, and a vertical synchronizing signal Sf is outputted when a prescribed count is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal detection circuit used in televisions, and more particularly to a synchronization signal detection circuit capable of detecting a vertical synchronization signal from a D2 standard digital video signal.

[Conventional technology]

It is well known that in a television receiver, a horizontal synchronization signal and a vertical synchronization signal are separated from a transmitted video signal, and images are obtained on a CRT based on these synchronization signals.

In particular, recently, with the development of digital technology, this digital technology has been applied to television receivers, video equipment, and the like. Television systems that employ digital technology in this way employ various standards.

FIG. 3 is a circuit diagram showing a conventional synchronization signal detection circuit that detects a vertical synchronization signal from a digital video signal adopting the D2 standard.

The synchronous signal detection circuit shown in FIG. 3 consists of a monostable multivibrator M? connected to a resistor RA and a capacitor CA for testing the time constant TA. A and time constant T
, and a monostable multi-vibration brake MMB to which a resistor RB and a capacitor CI1 are connected are connected in series.

Furthermore, both multivibrators MMA SM Me are designed to input signals to their inverting input terminals, multivibrator MMA outputs signals from their inverting output terminals, and multivibrator M M n outputs signals from their non-inverting output terminals. It is outputting. Both resistor RASR and power supply V. It is connected to 0.

The operation of such a conventional synchronization signal detection circuit will be explained with reference to FIG. In FIG. 4, the horizontal axis represents time T, and the vertical axis represents the on/off state of each signal.

First, the time constants T- and TB of both multivibrators MMASMMI1 are set so that the period of the horizontal synchronization signal is T. Then, Tl( > TA > Tl1 / 22T ■ >
It is determined that TIl>T.

Here, the period of the input horizontal synchronizing signal (a) is the fourth
As shown in the period T, ~T2 in the figure, T. When , the period of the signal (a) is larger than the time constant TA, so the multi-by-break MMA outputs a pulse that becomes "0" for the time constant T^ and then returns to the initial state.

Further, when the period of the manually inputted horizontal synchronizing signal (a) is TH/2 as shown in the period T2 to T in FIG.
Since the period of the signal (a) is smaller than the time constant TA, the multi-by-break M M A does not return to the initial state while outputting "0".

Furthermore, the period of the input horizontal synchronization signal (a) is the fourth
During the period T in the figure, when TH is reached as shown below, the signal (
Since the period of a) is larger than the time constant TA, the multi-by-break MMA has a period of time constant T. After outputting a pulse that becomes "0", the initial state is restored.

On the other hand, Multivi Break MM. is the period T1 in Figure 4.
~T2, the pulse signal (b) with time constant TA of a period smaller than time constant TB is multi-by-break MMA.
Since the signal is always input from C
) is output and does not return to the initial state.

However, since the multi-bye break MMB no longer receives the pulse signal (b) from the multi-bye break MM after the period T 2 in FIG. Output the number (C).

Again, from time T3 onwards, from multi-bye break MM.”
When the pulse signal (b) of "1" is input, the multivibrator MM. outputs the signal (C) of "1" and continues this state.

In this way, the vertical synchronization signal (C) can be detected. [Problem to be solved by the invention] However, such conventional synchronization signal detection
In the detection of the vertical synchronization signal by the
1 Ibrator MM. Since the time constant T8 is determined by the time constant T8, the following problem occurs. That is, the capacitor CB determines the time constant T, and the resistor R.
If the value of is changed due to temperature or changes over time, the above-mentioned phase relationship will change.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to provide a synchronization signal detection circuit whose phase relationship does not change due to temperature or the like.

[Means to solve the problem]

In order to achieve the above object, the synchronization signal detection circuit of the present invention equalizes a first horizontal synchronization signal detected from a digital video signal and a second horizontal synchronization signal containing an equalization pulse detected from the digital video signal. Horizontal synchronization that outputs a horizontal synchronization signal only during periods other than the vertical synchronization period from an equalization pulse detector that extracts only pulses and a third horizontal synchronization signal that includes the equalization pulses detected from the first horizontal synchronization signal and the digital video signal. The horizontal synchronization signal from the detector and this horizontal synchronization detector is taken in as a reset signal, and when this reset signal is not present, the equalization pulses from the equalization pulse detector are counted and output as a vertical synchronization signal at a predetermined position. It is characterized by being composed of a counter.

According to such a synchronization signal detection circuit, a vertical synchronization signal having a constant phase relationship can be obtained without being influenced by external conditions or the like.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the synchronization signal detection circuit of the present invention.

The equalization pulse detector 1 shown in FIG. A signal sb formed by extracting the leading edge portion of the horizontal synchronizing signal and the leading edge portion of the equalization pulse is supplied.

The equalization pulse detector 1 has a circuit configuration that can obtain an equalization pulse Sd by calculating the exclusive OR of the signal Sa and the signal sb.

The signal 3a is also supplied to a horizontal synchronization detector 2 for detecting horizontal synchronization signals other than the vertical synchronization period. The horizontal synchronization detector 2 is also manually supplied with a signal Sc which is formed by extracting the trailing edge portion of the horizontal synchronizing signal detected from the D2 standard digital video decoding and the trailing edge portion of the equalization pulse. The horizontal synchronization detector 2 outputs the horizontal synchronization signal Se only when the time difference between the signal Sa and the signal Sc matches a time difference other than the vertical synchronization period.
By outputting , the circuit is configured such that the horizontal synchronization signal Se is not output during the vertical synchronization period.

The equalization pulse Sd and the horizontal synchronization signal Se are provided to the counter 3. The counter 3 is configured to count the equalization pulses Sd only when the horizontal synchronization signal Se is not input, and output the vertical synchronization signal Sf when a constant count value is reached.

The operation of the embodiment configured as described above will be explained with reference to FIG. 2.

In Figure 2, the horizontal axis shows time, and the vertical axis shows the signal Sa~
The state of signal Sf is taken.

Signal Sa and signal sb are input to an equalization pulse detector l. In the equalization pulse detector 1, the signal Sa and the signal sb
The period t1 ~ in Fig. 2 is taken.
After t2 and time t, the equalizing pulse Sd is not output, and during the period t2 to t3, the equalizing pulse Sd is output. Of course, it goes without saying that even after time t3, the equalization pulse detector 1 operates in the same manner as during the period t2 to t in the vertical synchronization period. This equalization pulse Sd
is supplied to the signal input terminal of the counter 3.

Further, the signal Sa and the signal Sc are input manually to the horizontal synchronization detector 2. In the horizontal synchronization detector 2, a built-in counter counts the time difference between the signal Sa and the signal Sc, and the counted value matches the time difference of the horizontal synchronization signal other than the vertical synchronization period (period 1 t2 to t3 in FIG. 2). horizontal synchronization signal S only when
Output e. Therefore, the horizontal synchronization signal Se is not output during the vertical synchronization signal section. This horizontal synchronization signal Se
is input to the recent terminal of the counter 3.

The counter 3 is reset each time the horizontal synchronization signal Se is manually input (during the period t1 to t2, or at the time t3).
After that), since the horizontal synchronization signal Se is not input within the vertical synchronization period, the equalization pulses Sd are counted. Then, the counter 3 outputs the vertical synchronizing signal Sf at a predetermined position of the equalization pulse Sd, thereby generating the vertical synchronizing signal S.
f can be detected.

Such an operation is thereafter performed every vertical synchronization period to detect a vertical synchronization signal.

〔Effect of the invention〕

As described above, the present invention detects the vertical synchronization signal digitally, so that it is possible to obtain the vertical synchronization signal with a constant phase relationship without being influenced by external conditions.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing diagram for explaining the operation of the embodiment, Fig. 3 is a block diagram showing a conventional synchronization signal detection circuit, and Fig. 4 is a block diagram showing an embodiment of the present invention. FIG. 3 is a timing diagram for explaining the operation of a conventional device. 1...Equalization pulse detector, 2...Horizontal synchronization detector, 3...Counter.

Claims (1)

[Scope of Claims] An equalization pulse detector that extracts only equalization pulses from a first horizontal synchronization signal detected from a digital video signal and a second horizontal synchronization signal containing equalization pulses detected from the digital video signal; a horizontal synchronization detector that outputs a horizontal synchronization signal only during a period other than the vertical synchronization period from the first horizontal synchronization signal and a third horizontal synchronization signal including an equalization pulse detected from the digital video signal; and a counter that receives a horizontal synchronizing signal as a reset signal, and when the reset signal is absent, counts equalizing pulses from the equalizing pulse detector and outputs the counted equalizing pulses to a predetermined position as a vertical synchronizing signal. Synchronous signal detection circuit.