JPH03214873A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To reduce the number of sample-hold circuits which operate at high speed by further executing a sample-and-hold after subjecting an input signal to the sample-and-hold. CONSTITUTION:Sample-hold circuits 3A, 3D successively and alternately sample and hold an input video signal VR by pulses SH1, SH4, and outputs this. This output is supplied to sample-hold circuits 2A, 2D, 2G, successively subjected to the sample-and-hold by pulses SH11, SH22, SH14, and drives drain busses DB1, DB7, DB4. The pulses SH1, SH4 are generated at a timing corresponding to the timing for each pulses SH11, SH22, SH14. The currents 2A, 2D, 2G execute the sampling and holding to the signals subjected to sampling and holding at the circuits 3A, 3D by the corresponding pulses SH11, SH14 and SH22.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a liquid crystal display device, and particularly to a liquid crystal display device configured to sample an input video signal at a predetermined timing and drive pixels of a liquid crystal panel using the sampled signal. Related to display devices.

[Conventional technology]

An example of a conventional liquid crystal display device of this type is shown in FIG.

This liquid crystal display device includes a plurality of pixels PC of each color arranged in a matrix in the horizontal and vertical directions, and a plurality of pixels PC in the horizontal direction.
A plurality of gate bus lines GB1 to GBn for sequentially selecting pixels for each line one line at a time, and a plurality of drain bus lines DBI to DB9 for sequentially driving each pixel PC of one selected horizontal line. A liquid crystal display panel 1 is provided corresponding to each drain bus line DBI to DB9, and an input video signal V of each color is supplied.
l, Vo, V, from shift registers 4a, 4b as Zumble hold pulses SH51~SH55SH61~SH
62, a plurality of sample and hold circuits 2a to 21 which sample and hold data at predetermined timings and sequentially drive each drain bus line DB1 to DB9, and input a start pulse S'l and clock pulses CK and CK to these circuits. Sample 7' sample hold circuit 7L controls the sampling and bold timing of sample hold circuits 2a to 2l.
z Dovals SH51~SH5 5, SH6 1-SH6
2, and an inverter 5 that generates a clock pulse CK.

Each pixel PC is formed including a thin film 1 and a transistor, and one of the gate bus lines GBI to GBn to which one horizontal line of pixel PCs is connected is sequentially selected by a horizontal line selection signal HW1=HWn. game I
- A predetermined image is displayed on the liquid crystal display panel 1 by sequentially driving the thin film transistors of the pixel PCs of the bus lines (one of GB 1 to GBn) by the blue bold circuits 2a to 21 during the selection period. .

FIG. 6 shows the timing relationship of signals of each part of this liquid crystal display device.

[Problem to be solved by the invention]

In the conventional liquid crystal display device described above, the zumble hold circuits 2a to 21 that drive each pixel PC in one horizontal line of the liquid crystal display panel 1 receive the input video signal VR. Since VC and VB are directly sampled and held, a large number of sample and hold circuits 2a to 21 operating at high speed are required, resulting in a high resolution image.

For example, in the horizontal direction, there are 6 red, green, and blue pixels PC each.
In order to perform television display using 40 liquid crystal display panels, 1920 sample hold circuits operating at approximately 30 MHz are required.

In this way, in order to implement a large number of sample and hold circuits to an extent that poses no practical problems, it is necessary to integrate multiple sample and hold circuits into ICs. Manufacturing the built-in IC is technically difficult and expensive.

An object of the present invention is to provide a liquid crystal display device that can reduce the number of sample and hold circuits that operate at high speed and reduce the cost.

[Means to solve the problem]

The liquid crystal display device of the present invention includes a plurality of pixels arranged in a matrix in the horizontal and vertical directions, and a plurality of gate bus lines for sequentially selecting one line of pixels in the horizontal direction, one line at a time. A liquid crystal front panel is provided with a plurality of drain bus lines for sequentially driving each selected pixel in one horizontal line, and a liquid crystal display panel is provided corresponding to each of the drain bus lines, and a predetermined signal to be supplied is provided. a plurality of first sample and hold circuits that sample and hold the input signal at a timing corresponding to the sampling timing of each of the first sample and hold circuits, and sequentially drive each of the drain bus lines; and a high-speed second sample and hold circuit that samples and holds the sample and supplies it to each of the first sample and hold circuits.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, N is 2 as stated in claim 2.
The case is shown below.

This embodiment is similar to the conventional liquid crystal display device 1-1 shown in FIG.
The difference is in the timing for each sampling of each (first) sample and hold circuit 2A to 2I that respectively drive each drain bus line DBI to DB9 of the liquid crystal display panel 1, and the timing for each color corresponding to the timing for each sampling. ,
For each color, the input video signal VR. (Second) sample and hold circuits 3A/3D+3B/3E, 3C/3F are provided which sequentially and alternately sample Vo and VB, hold and output them, and these sample bold circuits 3. =/30.3B
Sample bold circuits (2, A, 2D/20), (2C/2F, 2I) corresponding to the output signals of /3E, 3o/3F
), (28.2 E/ 2 H), respectively, and these sample bold circuits 2, ~ 2E, 2F
Zumble Bold Pulse SHII to ~2l~SH15
, SH21 to SH24 are transferred to shift register 4A. 4B.

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart of signals of various parts for explaining the operation of this embodiment.

■ Input video signal of one color so that the explanation is not confusing. I will explain about it.

The sample hold circuits 3A, 3D sequentially and alternately process the input video signal by sample hold pulses SHI, SH4 corresponding to the timing of each sample hold pulse SHI 1, SH22, SHI 4 supplied to the sample hold circuits 2A, 2o, 2o. Sample VR, hold it, and output it.

This Zumble hold circuit 3, . , 3ゎ output signals are supplied to the Samplepoort circuits (2A, 2D), 20,
Sample hole F pulse 3H1 1, SH2 2, SH
Drain bus D
It is designed to drive BI, DB7, and DB4.

The sample-and-hold pulses SHI and SH4 supplied to the sample-and-hold circuits 3A and 3D are generated at timings corresponding to each sample-and-hold pulse SHI 1, SH22, and SHI 4, so the sample and hold circuits 3A and 3D are different from those of the conventional example. Sample bold circuit 2
．． ~2, high-speed operation equivalent to 2 is required.

On the other hand, the sample and hold circuits 2,=,2D,20 sample and hold the signals once sampled and held by the high-speed sample bold circuits 3A, 3D using the corresponding sample and hold pulses SHI 1, SHI 4, and SH22, respectively. Therefore, the sample-and-hold circuits 2a, 2d, and 2g of the conventional examples can operate at a lower speed.

Comparing Figures 2 and 6, we can see that the pulse width of the start pulse ST can be three times that of the conventional example, so the sample bold circuits 2A to 2I only need to operate at 1/3 of the operating speed of the conventional example. I understand that.

In this way, only 6 high-speed sample and hold circuits are required, which can be significantly reduced compared to 1920 in the conventional example.

FIG. 3 is a block diagram showing a second embodiment of the invention.

In this embodiment, the input signal is the digital image signal D V n
．． An example is shown in which N=2 as in the first embodiment, and the digital image signals D V n , D V a , D V , The second sample and hold circuits are latch circuits 6A to 6F, and these latch circuits 6A to 6F are controlled by clock HALS CK2, and sample hold pulses SH3 1 to SH35 to the first sample and hold circuits 2A to 2, SH41 to SH44 are generated by shift registers 4C and 4D.

FIG. 4 is a timing diagram of signals of various parts for explaining the operation of this embodiment.

In this embodiment, sample and hold circuits 2A to 2. The sampling and bold operations can be performed at twice the period of the latch circuits 6A to 6F, and the operation speed can be reduced to 1/2.

〔Effect of the invention〕

As explained above, the present invention can significantly reduce the number of sample-and-hold circuits that operate on the input signal at high speed in the first sample-and-hold circuit, and therefore has the effect of reducing costs. be.

4

[Brief explanation of drawings]

1 and 2 are block diagrams of a first embodiment of the present invention and timing diagrams of signals of each part for explaining the operation of this embodiment, and FIGS. 3 and 4 are respectively block diagrams of a first embodiment of the present invention. FIGS. 5 and 6 are a block diagram of an example of a conventional liquid crystal display device and a timing diagram for explaining the operation of this example, respectively. FIG. 4 is a timing diagram of signals of various parts. l...Liquid crystal display panel, 2A-2. ,2,~2
3A~36...Sample hold circuit, 4A~
4D, 4a, 4b...Shift register, 5.5
A, 5... Inverter, 6, ~6F...
Latch circuit, DBI to DB9...Drain bus line, OBI to GBn...Gate bus line, P
C...Pixel.

Claims (2)

[Claims] (1) A plurality of pixels arranged in a matrix in the horizontal and vertical directions, a plurality of gate bus lines for sequentially selecting one line of pixels in the horizontal direction, and the selected horizontal line. A liquid crystal front panel is provided with a plurality of drain bus lines for sequentially driving each pixel in one line in a direction, and a liquid crystal front panel is provided corresponding to each of the drain bus lines, and the supplied signals are sampled at a predetermined timing. a plurality of first sample and hold circuits that hold and sequentially drive each of the drain bus lines; A liquid crystal display device comprising: a high-speed second sample-and-hold circuit that supplies data to the first sample-and-hold circuit. (2) Provide N second sample and hold circuits (N is an integer of 2 or more), and sequentially switch the pixels of one horizontal line, the drain lines corresponding to these pixels, and the first sample and hold circuit in the driving order. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is divided into N systems, and the output signal of each of the N second sample and hold circuits is supplied to each of the first sample and hold circuits of the N systems, respectively. .