JPH03216034A - Reception synchronizing circuit - Google Patents

Abstract

PURPOSE:To take a reception timing without increasing the constitution even in the case of reception of plural stations by providing a storage means storing plural sets of time difference information relating to a time difference between a defection timing of a unique word and a start time of an aperture period. CONSTITUTION:Time difference information relating to a time difference between a detection timing of a unique word by a unique word detection section 1 and a start time of an aperture period is detected by a shift register 2 and the time difference information is stored in a RAM 4. When the time represented by the time difference information stored in the RAM 4 elapses from the start time of the aperture period, a prescribed pseudo detection signal is generated at a shift register 5. In this case, since the RAM 4 stores plural sets of time difference information, when plural reception stations exist, the time difference information of each reception station is stored respectively in the RAM 4. Thus, even in the case of reception of plural stations, the reception timing is taken without increasing the constitution.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a method for determining the reception timing of data transmitted in a time division multiple access (TDMA) system, for example, in a satellite communication system. This invention relates to a reception synchronization circuit.

(Prior Art) FIG. 3 is a diagram showing an example of a TDMA frame when three transmitting stations perform data transmission using the TDMA method.

In this way, each transmitting station is assigned time slots indicated by A, B, and C in the figure, and a burst signal is inserted into each of the assigned time slots. Note that a guard time (protection time) that cannot be assigned to any transmitting station is provided between each evening time slot.

The burst signal transmitted by each transmitting station is constructed by adding a prefix to the front of the transmission data (DATA), as shown in the figure. Here, the prefix is demodulation symbol (CBR
), unique word (UW), station identification code (SIC),
It consists of the meeting line (OW), etc.

For example, when transmitting data using a TDMA frame configured as described above, the receiving station detects a unique word in the prefix added to the burst signal to be received, and from the timing of the detection of this unique word. This is used to obtain the reception timing. That is, as shown in FIG. 4, the unique word detection signal (UW detection signal)
A reception timing signal is generated in synchronization with the . Data reception is performed in synchronization with this reception timing signal.

However, due to deterioration of the line condition or the like, it may not be possible to detect a unique word. Therefore, conventionally, a counter is provided that operates in synchronization with the detection of a unique word and counts a time T that is slightly longer than one cycle of a TDMA frame. If no unique code is detected before this counter counts up, the reception timing is obtained based on when the counter counts up. In addition,
If a unique word is detected before the counter counts up, the counter is reset.

However, with such a configuration, for example, 3 of A, B, and C
When receiving data transmitted in multiple time slots, such as receiving all data transmitted in one time slot, it is necessary to set the reception timing for each time slot, and the burst signal to be received must be In other words, the same number of counters as the number of receiving stations (for example, three in the case of receiving all the data transmitted in three time slots A, B, and C) must be provided.

(Issue 8 to be solved by the invention) As described above, conventionally, a counter is used in case a unique word cannot be detected, so when receiving multiple stations, the same number of stations as the number of receiving stations is used. A counter had to be provided, and as the number of receiving stations increased, the configuration became large-scale.

The present invention has been made in consideration of these circumstances, and its purpose is to provide a reception system that allows reception timing to be determined without increasing the configuration even when receiving from multiple stations. The purpose is to provide a synchronous circuit.

[Configuration of the Invention (Means for Solving the Problems) The present invention provides a synchronization word detection means for detecting a synchronization word (unique word) from transmitted data within an aperture period, and a synchronization word detection means using the synchronization word detection means. A time difference detection means such as a shift register for detecting time difference information regarding the time difference between the synchronization word detection timing and the start point of the aperture period, and a RAM or the like capable of storing a plurality of pieces of time difference information detected by the time difference detection means. storage means,
Synchronization is performed by pseudo detection signal generating means such as a shift register, which outputs a predetermined signal when the time indicated by the time difference information stored in the storage means has elapsed from the start of the aperture period, and the synchronization word detecting means. a detection presence/absence determination means for determining whether or not a word has been detected; and when the detection presence/absence determination means determines that a synchronization word has been detected, selectively outputting a detection signal output by the synchronization word detection means; Further, when it is determined that the synchronization word has not been detected, the signal outputted by the pseudo detection signal generating means is selectively output.

(Function) By taking such measures, time difference information regarding the time difference between the synchronization word (unique word) detection timing and the start time of the aperture period is detected, and this time difference information is stored in the storage means. Then, a predetermined pseudo detection signal is generated when the time indicated by the time difference information stored in the storage means has elapsed from the start of the aperture period, and it is determined whether or not the synchronization word has been detected by the synchronization word detection means. In response to this, when a synchronization word is detected, a detection signal output by the synchronization word detection means is selectively outputted;
Further, when no synchronization word is detected, the pseudo detection signal is selectively output.

Therefore, when a synchronization word is not detected, a pseudo detection signal is output at the same timing as the previous synchronization word detection, and this pseudo detection signal is selectively output to ensure reception timing.

Here, the storage means can store a plurality of pieces of time difference information, so when the number of receiving stations is plural, the time difference information of each receiving station can be stored in the storage means.

(Embodiment) Hereinafter, a reception synchronization circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the reception synchronization circuit. In the figure, 1 is a unique word detection section, which is composed of a shift register 1as, a unique word judgment section 1b, and an AND gate IC. Here shift register 1
a has the same digit as the number of bits n of the unique word.

Then, the output Ql of each digit of the shift register 1b. Q2...
- Each Qn is input to the unique word determination unit 1b. The unique word determination unit 1b uses each output Q. of the shift register 1b. , Q2..., Qn are at respective predetermined levels, and the shift register 1
Each output Q1. When all of Q2..., Qn are at their respective predetermined levels, a pulse signal is output. The AND gate 1c receives the pulse signal output from the unique word determination unit 1b and the aperture gate signal which is at the rHJ level for a predetermined period at a predetermined cycle, and outputs the pulse signal only during the period when the aperture gate signal is at the rHJ level. .

2 is a shift register in which the aperture gate signal is r
It has the same order of magnitude as the period m of the reproduced clock (clock signal reproduced from the received signal) corresponding to the period when the HJ level is reached. Then, the output Q1 of each digit of the shift register 2. Q
2..., Qm are games}3a, 3b..., 3, respectively
It is connected to RAM4 via m. Note that a reproduced clock is input to the clock terminal of the shift register 2.

Reference numeral 5 designates a shift register, which, like the shift register 2, has the same order of magnitude as the period m of the regenerated clock (clock signal regenerated from the received signal) corresponding to the period in which the aperture gate signal is at the rHJ level. And a brisset terminal P for each digit. ．． P1...Pm are connected to RAM4. Note that the shift register 5 has an A. A reproduced clock is input to the clock terminal via the ND gate 9.

Reference numeral 6 denotes an address generator, which generates an address for writing or reading from the RAM 4 according to predetermined conditions.

7 is a unique word detection/non-detection determining section.

The unique word detection/non-detection determining unit 7 receives the aperture gate signal and the output signal of the AND gate 1c, and determines whether or not a UW has been detected from both signals. Then, in accordance with the result of this determination, write permission of the RAM 4, gate ON control, and switching control of the selector 8 are performed. Selector 8 is the final stage output Qm of shift register 2
and the final stage output Qm of the shift register 5 are respectively input, and one of these is selected and output.

Next, the operation of the reception synchronization circuit configured as described above will be explained as follows.
This will be explained with reference to signal waveform diagrams of each part shown in the figure. First, the received data is input to the unique code detection section 1, and the unique code is detected as follows.

That is, first, the shift register 1a extracts consecutive n bits from the received data and outputs them in parallel. The number n of bits to be extracted is the same value as the number of bits of the unique word, as described above. The n-bit parallel outputs of this shift register 1a are each input to a unique word determination section 1b.

Next, the unique word determining unit 1b determines whether each output Ql, Q2..., Qn of the shift register 1a is at a respective predetermined level set in advance according to the unique word pattern. , it is determined whether the n-bit parallel output of the shift register 1a has the same pattern as the unique word. The unique word determination unit 1b then selects each output Q l of the shift register 1a.
A predetermined pulse signal is output when rQ2 . Here, in order to avoid misidentifying this communication data as a unique word when data having the same pattern as a unique word exists in the communication data, the communication data is outputted via an AND gate IC which is opened and closed by an aperture gate signal.

In this way, the unique word is detected, and the output of the AND gate 1c becomes the unique word detection signal. That is, this unique word detection section detects a unique word (synchronization word), and functions as a synchronization word detection means.

Unique words are detected in the unique word detector 1 as described above, and the output detection signal is input to the shift register 2. The shift register 2 sequentially shifts the detection signals in accordance with the reproduced clock. As a result, each output Q1, Q2..., Q of the shift register 2
m changes as shown in FIG. Note that FIG. 2 shows an example in which the period during which the aperture gate signal is at the rHJ level (hereinafter referred to as the aperture period) is five cycles of the reproduced clock, and the shift register 2 is 5 digits, that is, m is 5. ing.

At the same time, the unique word detection/non-detection determining section 7 receives the detection signal and the aperture gate signal. This unique word detection/non-detection determining section 7 monitors whether a detection signal is input within the aperture period (period TA in FIG. 2). And the aperture period T
When a detection signal is input during A, it is determined that a unique word has been detected, and when a detection signal is not input manually, it is determined that a unique word has not been detected. In other words, this unique word detection/non-detection determination section works as a detection/non-detection determination means.

When the unique word detection/non-detection determining unit 7 determines that a unique word is detected, the aperture period T
At the end of A, a write enable (WE) signal is output at T2. This WE signal is connected to the WE terminal of RAM4 and gate 3.
The signals are input to gate signal terminals a, 3b, . . . , 3m, respectively. Along with this, the gates 3a, 3b, . . . , 3m are turned on, the RAM 4 is put into a writing state, and each output Q 1r of the shift register 2 at time T2
Q2...+Qm are written into RAM4. In addition, the second
In the state shown in the figure, data ro0010J is written into the RAM 4. For example, r00010
The part of the data J where "1" stands is information indicating the detection position of the unique word within the aperture period TA. For example, the data r00010J is the time difference from the start time T1 of the aperture period TA until the unique word is detected. It indicates information. That is, the shift register 2 functions as a time difference detection means, and the RAM 4 functions as a storage means.

On the other hand, when the unique word detection/non-detection determining section 7 determines that no unique word is detected, it switches and controls the selector 8 at the end of the aperture period TA T2. Here, selector 8 normally selects shift register 2, but selects shift register 5 under the above switching control.

Incidentally, the shift register 5 is preset with the data stored in the RAM 4 through the above procedure in synchronization with the start time T1 of the aperture period. A reproduced clock is input to this shift register 5 via an AND gate 9 which is opened and closed by a signal obtained by inverting the aperture gate signal. That is, the shift register 5 operates during periods other than the aperture period TA. As a result, for example, as described above, when the data r00010J is stored in the RAM 4 and this data r00010J is reset to the shift register 5, no clock signal is given to the shift register 5 during the aperture period TA. , is maintained in the state shown in FIG. When the aperture period TA ends, a clock signal is applied to the shift register 5, and the data held in each stage is sequentially shifted. In the example shown in the second diagram, the aperture period T
The first clock pulse after the end of A causes the output Q5 to r
It becomes HJ level. This is the same timing when the final stage output Q5 of the shift register 2 becomes rHJ level. That is, the shift register 5 generates the same detection signal as the detection signal output by the shift register 2 from the data stored in the RAM 4. The signal output from this shift register 5 is a pseudo detection signal, and this shift register 5 functions as a pseudo detection signal generating means.

As described above, when the unique word detection/non-detection determining section 7 determines that no unique word is detected and performs switching control on the selector 8, the pseudo detection generated in the shift register 5 as described above is detected. The signal is on selector 8
Selected output is made by The output signal of this selector 8 is a reception timing signal.

When the unique word detection section 1 is able to detect a unique word, the detection signal output from the unique word detection section 1 is outputted via the shift register 2 as a reception timing signal. In addition, the unique word detection unit 1
If a unique word cannot be detected, a pseudo detection signal is generated in the shift register 5 based on information indicating at which position within the aperture period the detection signal in the previous unique word detection was output, and this The pseudo detection signal is output as a reception timing signal. Therefore, it is possible to secure the reception timing when a unique word is not detected.

By the way, when receiving from a plurality of stations using the reception synchronization circuit having this configuration, information on each unique word detection timing may be stored in a separate area of the RAM 4.

That is, the same number of addresses as the number of receiving stations are set in the address generator 6. The address generating section 6 switches the generated address every time the aperture gate signal rises. Specifically, for example, if the number of receiving stations is three, addresses for stations A, B, and C are set in advance, and each time the aperture gate signal reaches the rHJ level, the addresses for station A are set. Address for station B Address for station C
Addresses are generated sequentially in the following order: station address → A station address, and so on.

As a result, the above-described operation is performed for each station, and each station is synchronized.According to this embodiment, the detected position of the unique word within the aperture period TA is detected, and this is transmitted to the RA.
Since the information is stored in M4, by selectively using the storage area of RAM4, it is possible to cope with an increase in the number of receiving stations without any increase in the circuit configuration. Also, RAM
The data stored in RAM 4 is, for example, the number of cycles of the regenerated clock corresponding to the aperture period TA, that is, about 5 bits, so even one RAM 4 can store data for a considerable number of stations, and the number of receiving stations is It can handle even if there are a lot of them.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, a shift register is used as the time difference detection means and the pseudo signal generation means, but it is also possible to use a counter, a first-in first-out (FIFO) memory, or the like. Furthermore, the storage means is not limited to RAM; for example, the shift register 5 may be of a multi-stage type to have the function of storage means, or memory other than RAM or other various storage media may be used. be. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] According to the present invention, there is provided a synchronization word detection means for detecting a synchronization word (unique word) from transmitted data within an aperture period, a synchronization word detection timing by the synchronization word detection means, and a time difference detection means such as a shift register for detecting time difference information regarding the time difference from the start point of the aperture period; a storage means such as R A Fv1 capable of storing the time difference information detected by the time difference detection means; A pseudo detection signal generating means such as a shift register outputs a predetermined signal when the time indicated by the time difference information stored in the storage means has elapsed from the start of the period, and the synchronizing word detecting means detects the synchronizing word. and a detection presence/absence determination means for determining whether or not the detection has been completed, and when the detection presence/absence determination means determines that a synchronization word has been detected, selects and outputs the detection signal output by the synchronization word detection means; When it is determined that word detection has not been performed, the signal output by the pseudo detection signal generating means is selectively output, so even when receiving from multiple stations, the reception timing can be adjusted without increasing the configuration. It becomes a receiving synchronization circuit that can be used.

[Brief explanation of drawings]

1 and 2 are diagrams explaining a reception synchronization circuit according to an embodiment of the present invention. FIG. 1 is a block diagram showing the configuration, and FIG. 2 shows signal waveforms of each part in FIG. 1. The figures shown in FIG. 3, FIG. 4, and FIG. 4 are diagrams explaining the prior art, respectively. 1...Unique word detection unit, 1a...Shift register, 1b...Unique word determination unit, IC...A
ND gate, 2...Shift register, 3a-3m...
・Gate, 4...RAM, 5...Nft register,
6...Address generator, 7...Unique word detection/non-detection determination section, 8...Selector, 9...AND gate.

Claims (1)

[Claims] In a reception synchronization circuit that determines the reception timing of data transmitted in a time division multiple access system, within an aperture period,
a synchronization word detection means for detecting a synchronization word from the transmitted data; a time difference detection means for detecting time difference information regarding a time difference between a synchronization word detection timing by the synchronization word detection means and a start point of the aperture period; a storage means capable of storing a plurality of pieces of time difference information detected by the time difference detection means; and a storage means that outputs a predetermined signal when the time indicated by the time difference information stored in the storage means has elapsed from the start of the aperture period. pseudo detection signal generating means; detection presence/absence determining means for determining whether or not the synchronizing word has been detected by the synchronizing word detecting means; Selectively output the detection signal output by the detection means,
The receiving synchronization circuit further comprises a selection means for selectively outputting the signal outputted by the pseudo detection signal generation means when it is determined that no synchronization word has been detected.