JPH03216035A - Line switching system - Google Patents

Abstract

PURPOSE:To shorten the time required for line switching by providing an address storage section for delay circuit storing a write address of a cell to a common buffer and acting like a delay circuit in addition to an address storage section by an output port. CONSTITUTION:An address storage section 36d for a delay circuit is provided, which stores a write address of a cell to a common buffer 21 and acts like a delay circuit in addition to address storage sections 36a-36c by each output port in a common buffer switch having the address storage sections 36a-36c by each output port storing a write address of a cell to the common buffer 21 by each output port and applying queue processing. After a desired delay is implemented by the address storage section 36d for a delay circuit, an address stored by the address storage section 36d for a delay circuit is read in the older order and the result is fed to the queue of the address storage sections 36a-36c by each output port corresponding to the output port to which the delayed cell is to be outputted. Thus, since no real cell arrival interval detection circuit is required, the time required for line switching is shortened.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is utilized for time division multiplexing digital transmission, and in particular,
The present invention relates to a line switching method for switching a working line or transmission line that transmits an information string in units of cells to a protection line or transmission line. Line or transmission line switching refers to switching and switching back transmission lines in the event of node or transmission line failures, relocating and switching back transmission lines due to node expansion or transmission line construction, load balancing on transmission lines, or installation of new lines. This is necessary for line accommodation replacement, etc.

[Conventional technology]

FIG. 7 is a block diagram showing an example of a conventional line switching system (see Japanese Patent Application No. 1-299051). Further, FIG. 6 is an explanatory diagram showing the format of an information string (cell) on a transmission path for explaining the concept of a cell transmission system.

First, FIG. 6 will be explained. In Figure 6, VCI
．． SVCI and VC I3 are call identifiers (hereinafter referred to as VCI) assigned to each call that indicate the destination, and VPIO.
and VP I, is a route identifier (hereinafter referred to as VPI) given to each line indicating the transmission route, H is the header, ■ is the main information, E is the bit data collection for identifying empty cells, and empty is used. The format of the information string consists of real cells and empty cells. However, when transmitting a frame by adding an overhand that includes a frame pattern to multiple cells,
The format of the information string on the transmission path is composed of real cells, empty cells, and the above-mentioned overhead. VCI or VPI
Different subscripts indicate different calls or lines.

A flow of cells given the same VPI becomes a line.

VPI allows a relay device to handle multiple calls in a uniform manner by assigning the same value to multiple calls transmitted to the same destination. Same VPI
The transmission speed of the line can be arbitrarily selected depending on the number of calls to be assigned.

The same VCI is assigned to the main information of the same call from call origination to call termination. Therefore, the flow of sensors assigned the same VCI can be viewed as one line. Furthermore, since the transmission line is treated as one line or multiple lines in a unified manner, it can also be seen as one line.

Also, OAM (OperationsSAdm+n+
strat+onand Maintenance)
In other words, an OAM cell is defined to convey maintenance, management, and operation information within the network, and the OAM cell is given its own VPI to distinguish it from the line that carries calls. It is also possible to transfer between nodes. In this case, the OAM information is inserted into the main information area I of the cell. This flow of OAM cells assigned the same VPI can also be viewed as a type of line. However, ○
AM cells may also be terminated at cross-connect nodes within the network.

A line configured by VCI or VPI is not a physical line that always exists on a transmission path, but a logical line that exists only when a call occurs.

Therefore, the relay device only sends the cell to the intended outgoing route according to the VCI or VPI of each cell only when the cell arrives. For this reason, each relay device
It has a table in which exit route numbers are written for each I or VPI.

Next, FIG. 7 will be explained. In FIG. 7, 1 is a transmitting side device, 2 is a receiving side device, 3 is a working line or transmission line, 4 is a protection line or transmission line, 5 is a cross-connect switch (XSW) that switches on a cell-by-cell basis,
6 is an OAM cell generation circuit (OCG), 7 is a control circuit (CT), 8a and 8b are real cell arrival interval detection circuits (RCDT), 9a and 9b are real cell arrival interval designation signals or real cell arrival intervals Detection signal, lOa and Lo
ll is ○AM cell separation circuit (OCS), lla and llb are ○AM cell signals, 12a and 12b are real cell separation circuits (RCS), 13a and 13b are real cell separation designation signals or real cell separation release signals, and 14 is First-in-first-out memory (hereinafter referred to as FIFO), 15 is a read clock, 16 is an empty signal,
17 is a control circuit (CT), 18 is a AM cell generation instruction signal, and 19 is a header conversion table rewrite signal.

Here, the function of the delay circuit is performed by the FIFO 14.

The OAM cell generation circuit (OCG) 6 is activated by an OAM cell generation instruction signal 18 such as a switching signal indicating the end of an information string.
It generates an AM cell and sends the OAM cell to a cross-connect switch (XSW) 5. The cross-connect switch (XSW) 5 manually creates a header conversion table for each transmission line in which the VPI for identifying all the lines accommodated in the input transmission line and the output route number of each line are written in correspondence with the VPI. and with its header conversion table,
According to the VPI in the header of each arriving real cell, the cell is sent out to the corresponding outgoing route. The header conversion table is added to and rewritten as necessary by a header conversion table rewrite signal 19 from the control circuit (CT) 7.

The real cell arrival interval detection circuits (RCDT) 8a and 8b normally allow arriving cells to pass through as is, but when they receive actual cell arrival interval designation signals 9a and 9b from the control circuit (CT) 17, they will arrive after that. The control circuit (CT) 17 measures the arrival interval of real cells and if no real cell arrives for a time longer than the specified real cell arrival interval.
Real cell arrival interval detection signals 9a and 9b are sent out, respectively, after which the normal state returns to the above-mentioned state.

OAM cell separation circuits (OCS) 10a and 10b are
When an OAM cell such as a switching signal indicating the end of an information string is a cell addressed to the own node, the cell is separated and the control circuit (C
T) Send to 17. Real cell separation circuit (RCS) 12a
and 12b normally pass each arriving cell as is, but upon receiving real cell separation designation signals 13a and 13b from the control circuit (CT) 17, they separate real cells that have arrived thereafter and send them to the PIFO 14. . The real cell separation circuits (RCS) 12a and 12b each receive a real cell separation release signal 13a from the control circuit (CT) 17.
and 13b, thereafter returns to the normal state.

If the read clock 15 has not arrived, the FIFO 14 stores the written actual cells and receives the subsequent clock 15.
If the actual cell has arrived, the accumulated real cells are read out by the successive clock 15. When a real cell in the FIF○14 becomes empty, an empty signal 16 indicating this is sent to a control circuit (CT) 17.

Next, referring to FIG. 7, an explanation will be given of the operation of switching transmission lines without momentary interruption.

First, when the control circuit (CT) 17 of the receiving side device 2 receives a line switching signal from a center device (not shown), it sends out a header conversion table rewriting signal 19 to the spare header in the cross-connect switch (XSW) 5. Transmission line and FIFOl4
The contents of the header conversion table corresponding to the current transmission line to be switched are copied to the header conversion table corresponding to the current transmission line to be switched. Further, the output of the read clock 15 is stopped, and the real cell separation designation signal 13b is sent to the real cell separation circuit (RCS>12b).

Next, the control circuit (CT) 7 of the sending device 1 controls the OAM cell generation circuit (CT) in the cross-connect switch (XSW) 5.
A header conversion table rewriting signal 19 is sent to the header conversion table corresponding to OCG) 6 so as to output the OAM cell to the working transmission line 3. Next, the control circuit (CT) 7 adds the current transmission line 3 to the header conversion table corresponding to all the input transmission lines in the cross-connect switch (XSW) 5.
A header conversion table rewriting signal 19 is sent out so that all lines output to the standby transmission line 4 are output to the protection transmission line 4. Immediately after that, the control circuit (CT) 7 starts the OAM cell generation circuit (
○ΔM cell generation instruction signal 18 is sent to ○CG) 6 to send an OAM cell with a switching signal inserted therein indicating the end of the information string.

On the other hand, the control circuit (CT) 17 of the receiving side device 2 includes an OAM cell separation circuit (OCS) 10a corresponding to the working transmission line 3.
After receiving the OAM cell signal 11a into which the switching signal has been inserted from the OAM cell signal 11a, the transmission of the successive clock 15 is started. After that, after receiving the empty signal 16 from the control circuit (CT) 17i and PIF'014, the real cell separation circuit (RCS) 12
From b to FIF○14, cross connect switch (
A real cell arrival interval designation signal 9b is sent to a real cell arrival interval detection circuit (RCDT) 3b, with the delay time to the output terminal of the XSW) 5 as a real cell arrival interval. Thereafter, the control circuit (CT) 17 controls the real cell arrival interval detection circuit (RC).
Immediately after receiving the real cell arrival interval detection signal 9b from DT) 8b, the real cell separation release signal 13b is sent out, and the transmission path switching is completed. Switching back the transmission line can also be performed in the same manner as the switching described above.

In addition, line switching is performed by changing the real cell arrival interval detection circuits (RCDT) 3a and 8b to the real cell arrival interval detection circuit of the specified VPI and the real cell separation circuits 12a and 12b to the real cell separation circuit of the specified VPI in FIG. This can be done in the same manner as in the case of the transmission line switching described above, by changing the header conversion table with respect to the VPI that identifies the line to be switched.

[Problem that the invention seeks to solve]

The transmission path switching and line switching in the conventional example shown in FIG.
w) It is necessary in addition to the buffer in 5, which has the disadvantage of increasing the hardware scale.

In addition, when disconnecting the PIFO 14 as a delay circuit from the protection transmission line or the protection line, in order to prevent the order of cells from being reversed, a time period corresponding to the time during which no reversal of the order of cells occurs in the actual cell arrival interval detection circuit is required. , is performed when there are consecutive empty cells. This method is mainly used because the delay time passing through the cross-connect switch (XSW) 5 varies. However, when the usage rate of the transmission path or line is high, there is a drawback that the waiting time until the desired continuous empty cells arrive becomes long.

Another drawback is that a real cell arrival detection circuit is required for each transmission path. Furthermore, switching of transmission lines or lines may need to be performed for multiple lines, and switching back is also required, and in order to share the FIFO as a delay circuit, it is necessary to switch the FIFO as a delay circuit after each switching.
It is necessary to cut it out.

SUMMARY OF THE INVENTION An object of the present invention is to provide a line switching system that has a small hardware scale and can switch at high speed by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a common buffer that temporarily stores arriving real cells, an address storage section for each output port that stores the write address of this common buffer, and an address that is read from the address storage section for each output port as an empty address. In the line switching system, the transmitting side apparatus includes a sending side apparatus and a receiving side apparatus, and has a switching means for switching a working line to a protection line on a cell-by-cell basis. A first line switching control means for switching from a working line to a protection line at an arbitrary break in the line, and indicating the end of the information string after the last cell of the working line due to switching passes through the first line switching control means. switching signal transmitting means for generating a switching cell containing a switching signal and transmitting it to a working transmission path including a working line, the receiving side device detecting the switching signal from the sent switching cell; a detection means, and a delay circuit address storage unit that sequentially stores addresses at which real cells arriving from a protection line are written into the common buffer and operates as a delay circuit;
When the switching signal is detected by the switching signal detecting means, the addresses stored in the delay circuit address storage section are read in chronological order, and the output port-specific address corresponding to the output port to which the delayed actual cell is to be output is determined. After all the addresses stored in the storage section have been read out, the address of the real cell arriving from the protection line written into the common buffer is directly input to the address storage section for each output port. The present invention is characterized in that it includes a second line switching control means.

Further, the present invention provides that when the switching signal is detected by the switching signal detection means instead of the second line switching control means, the address stored in the delay circuit address storage section is transferred to a delayed real cell. is read out with priority over the address stored in the address storage unit for each output port corresponding to the output port to which the output port is to be output, inputted to the address storage unit for each output port, and stored in the delay circuit address storage unit. After all the addresses have been read out, a third line switching control means is provided for controlling the address written in the common buffer from the actual cell arriving from the protection line directly to the address memory for each output port. It is characterized by

[Effect]

In the present invention, in a common buffer type switch having an address storage section for each output port that stores write addresses of cells to a common buffer for each output port and performs queuing processing, a common A delay circuit address storage section that stores a write address of a cell in a buffer and functions as a delay circuit is provided, and after a desired delay is performed by the delay circuit address storage section, the delay circuit address storage section The addresses stored in the memory are read in chronological order and added to the queue of the output port address storage unit corresponding to the output port to which the delayed cell is to be output, or By performing priority control to perform address reading from the output port-specific address storage unit corresponding to the output port to which the delayed cell is to be output, the conventional cross-connect switch Since there is no reversal of the order of cells caused by delay fluctuations, the actual cell arrival interval detection circuit becomes unnecessary. Additionally, the time required for line or transmission line switching is therefore shortened. Furthermore, this delay circuit stores only the address of the cell written to the common buffer, so compared to the conventional delay circuit that had to store the cell itself, each cell has 53 bytes. Assuming that the number of address bits is IO bits, the required memory amount may be 1740 or less. Note that since the common buffer is used in common for all transmission lines, there is sufficient free memory capacity for delaying cells on the protection line or transmission line.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, 3a to 31 are current transmission lines, 39 is an interface circuit (IF) for optical-to-electrical conversion, bit synchronization, cell synchronization, etc., 40 is a cell multiplexing circuit (MUX),
20 is a header conversion circuit (HC), 21 is a common buffer (CBF), and 22 is a cell multiplexing/demultiplexing circuit (DEMUX).
, 23 and 24 are selectors (S), 25 is a write address of the common buffer 21, 26 is a read address of the common buffer 2l, 27 is an OR circuit, 28 is an empty signal,
29 and 30 are readout cloths, 31 is a selector (S)
24 control signal, 32 and 33 FIFO read clock, 34 header conversion table rewriting signal, control signal or OAM cell signal, 35 control signal of selector (S) 23, 36a, 36b and 36C each current transmission line 3d (3g), 3e (3h) and 3f (
FIFO as an address storage section for each output port corresponding to 3i), FIFO 36d as an address storage section for delay circuits, FIFO○ as an empty address storage section 36e
, 37 is an interface circuit (IF) for cell synchronization button insertion and electrical-to-optical conversion, and 38 is a control circuit (
CT), and the rest is the same as in FIG. 7. Hereinafter, 36a, 36b, and 36C will be referred to as output port address storage units or simply FIFOs, and similarly, 36a, 36b, and 36C will be referred to as output port address storage units or simply FIFO.
6d is the delay circuit address storage section or FIF0, 36
e is written as an empty address storage unit or FIFO.

A cell multiplexing circuit (MUX) 40 includes a transmission path and an OAM
Cells arriving from the cell generation circuit (OCG) 6 are multiplexed cell by cell and output to a high-speed internal highway whose speed is approximately several times faster than the speed of the human transmission line. Header conversion circuit (HC
) 20 indicates the correspondence between the VPI that identifies the line and the transmission line number to which cells of that VPI should be output, and the new VPI.
It has a header conversion table in which VPI is written for conversion.

When a real cell arrives from the high-speed internal highway, the successive clock 33 is sent to the empty address storage section 36e, one empty address is read out, and after decoding the VPI in the header of the arrived real cell, the cell is converted from the header conversion table. reads the transmission line number and new VPI to be output, and inserts the new VP into the real cell,
In the selector (S) 23, an address storage unit 36a, 36b or 36 for each output port corresponding to the transmission line number
A control signal 35 is sent so that c is selected. Also,
At the same time, the arrived real cells are transferred to a common buffer (CB).
F) Send to 21. As a result, the real cell is stored in the empty address storage section 36e of the common buffer (CBF) 21.
is written to the empty address read from. Further, the address at which the real cell is written in the common buffer (CBF) 21 is stored in the address storage units 36a and 3 for each output port corresponding to the output transmission path to which the real cell is to be output.
6b or 36C. In addition, the header conversion circuit (HC) 20 converts the arrived real cell into an OAM addressed to its own node.
If it is a cell, it reads a switching signal indicating the end of the information string contained in the cell and sends the OAM cell to the control circuit (CT) 38.

A common buffer (CBF) 21 writes a real cell using a write address 25, reads it using a subsequent address 26, and transfers the read real cell to a cell multiplexing/demultiplexing circuit (DEM).
UX) Send to 22. Cell multiplexing/demultiplexing circuit (DEMUX)
) 22 converts the arriving real cells to the transmission path speed according to the order of arrival, and then connects the working transmission path 3d (3g),
Sort into 3e (3h) and 3f (31).

During times when no real cells arrive, empty cells are sent to the corresponding transmission path. F T F 036a-36e send out the stored address while the read clock is applied. When there are no more Mm addresses in F IF 036a to 36e, an empty signal is sent.

The selector (S) 24 stores an output port address storage unit 3 corresponding to the output transmission path selected by the control signal 31.
6a, 36b or 36C, and the address storage section 36a for each output port.
, 36b or 36C,
The read address 26 is sent to the common buffer (CBF) 21, and the empty address is sent to the empty address storage unit 36e.
Send to. The control signal 31 is transmitted through a cell multiplexing/demultiplexing circuit (
DEMUX) 22, the working transmission line 3d (3g
), 3e (3h), and 3f (3l), the output port address storage units 35a, 36b, and 36c are repeatedly selected in this order.

○． The 8M cell generation circuit (OCG) 6 is a control circuit (CT
) ○AM that inserts an OAM signal such as a switching signal indicating the destination node number and the end of the information string when instructed by 38.
Generates a cell and sends the cell to a cell multiplexing circuit (MUX)
40.

The feature of the present invention is that in FIG. 1, the transmitting side device 1 includes a header conversion circuit (HC) as a first line switching control means
20 and an OAM cell generation circuit (OCG) 6 as a switching signal sending means, the receiving side device 2 includes a header conversion circuit (HC) 20 as a switching signal detecting means, and a delay circuit address register 1, α. F I F 035d as a section, an OR circuit 27 as a second line switching control means, selectors (S) 23 and 24, and a control circuit (CT) 3
8.

Next, the operation of the first embodiment will be explained.

The first embodiment can be used for switching lines without momentary interruption. Below, the procedure for switching the line from the working line passing through the working transmission lines 3a-36-3g to the protection line passing through the working transmission lines 3a-3e3g and switching back will be explained.

First, the control circuit (CT) 38 of the receiving side device 20 receives a line switching signal from a center device (not shown). When it receives the header conversion table rewrite signal 34, the real cell sent from the protection line in the working transmission line 3e is transferred to the common huffer (
The VPI for identifying the protection line and the delay circuit address are stored in the header conversion table in the header conversion circuit (HC) 20 so that the address written in the CBF) 21 is stored in the delay circuit address storage unit 36d. Storage section 36
The number corresponding to d and the new VPI used by the protection line within the working transmission line 3g are written.

Next, the control circuit (CT) 38 of the transmitting side device 1 sends a header conversion table rewrite signal so that the cell of the working line sent to the working transmission line 3d is sent to the protection line passing through the working transmission line 3e. 34 is sent.

A new VPI different from that of the working line is used for cells on the protection line passing through the working transmission line 3e. The control circuit (CT) 3g of the sending device 1 receives the header conversion table rewriting signal 3.
4, an OAM cell generation instruction is issued to the OAM cell generation circuit (OCG) 6 to transmit an OAM cell addressed to the receiving device 2 with a switching signal indicating the end of the information string inserted to the working transmission path 3d. Send signal 1B.

On the other hand, the header conversion circuit (HC) 20 of the receiving side device 2
When the OAM cell containing the switching signal addressed to the node is received, the OAM cell is sent to the control circuit (CT) 38, and at the same time, during the occupation time of the empty cell that arrives thereafter, the read clock 30 is sent to the delay circuit. address storage unit 36
The address of the cell of the protection line written in the common buffer (cBF) 21 is read from d, and the OR circuit 27
send to At the same time, a selector (S
) 23 control signal 35 is sent out. On the other hand, the control circuit (C
T) 38, after receiving the OAM cell containing the switching signal,
Immediately after receiving the empty signal 28 from the delay circuit address storage section 36d, the header conversion table is configured so that the address of the spare line cell written into the common buffer (CBF) 21 is directly written into the address storage section 36a for each output port. A rewrite signal 34 is sent. Header conversion circuit (
HC) 20 identifies the protection line of the header conversion table immediately after receiving the header conversion table rewriting signal 34.
The output transmission line number corresponding to PI is changed to the value corresponding to the current transmission line 3g, and thereafter, the transmission of the read clock to the delay circuit address storage section 36d is stopped.

This completes line switching. Switching back the line can also be performed in the same manner as the switching described above.

As a matter of course, if the transmission delay time of the switching destination protection line is longer than that of the working line, no address will be stored in the delay circuit address storage section 36d. However, even in that case, the line switching procedure is the same as in the above case.

As described above, the speed of the high-speed internal highway is not so high, and after the control circuit (CT) 38 receives the empty signal 28 from the delay circuit address storage section 36d, it outputs the header conversion table rewrite signal 34. The time it takes to rewrite the header conversion table in the header conversion circuit (HC) 20 is determined by the header conversion circuit (HC) 20.
C) If the transit time in 20 is small compared to the transit time of one cell, the order of the cells will not be reversed, so the actual cell arrival interval detection circuit will not be necessary. Furthermore, since the delay circuit address storage section 36d only needs to store addresses,
It requires less memory capacity than the conventional method.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In FIG. 2, 41 is a header conversion circuit (HC), 42
and 63 is a selector (S), 64 is a special address holding circuit (M), and 65 is a special address detection and removal circuit (D).
, and 66 are special address detection signals, and the others are the same as in FIG.

The header conversion circuit (HC) 41 has the same function as the header conversion circuit (HC) 20 shown in FIG. 1, except that it does not send out the successive clock 30. The selector (S) 42 is
Output port address storage unit 36a, 36b, or 36 corresponding to the output transmission path selected by the control signal 31
At the same time, the read clock 32 is applied to C, and the address read from the address storage unit 36a, 36b or 36c for each output port is sent to the common buffer (CBF) 21 as a read address 26 and is sent to the empty address storage B as an empty address. 3 6 Sends to e. The control signal 31 is normally sent to the cell multiplexing/demultiplexing circuit (DE to IU).
x) In 22, the working transmission line 3d (3g),
In order to separate the cells at around j of 3e (3h) and 3f (3i), an address storage section 36 for each output port is provided.
A, 36b and 36c are repeatedly selected in this order. However, when it is necessary to read an address from the delay circuit address storage section 36d, the control circuit (CT) 3g uses an output port-specific address corresponding to the transmission line to which the delayed protection line cell should be output. Storage part 3
The control signal 31 is sent to select the delay circuit address memory 136d instead of selecting 5a, 36b or 36c.

The special address holding circuit (M) 64 is a common buffer (CB
F) Holds a special address that is never used in 21. The selector (S) 63 normally selects the output port specific address record 1'. I! M36a
, 36b or 36c1 or the delay circuit address storage section 36d, but the address conversion circuit (HC)
When there is an instruction from 41, the special address from the special address holding circuit (M) 64 is sent to the target output port address storage section 36a, 36b or 36c by the control signal 35.

The special address detection and removal circuit (D) 65 allows normal addresses to pass through as is, but when a special address arrives, it detects it, sends out a special address detection signal 66, and removes the special address.

The feature of the present invention is that in FIG.
41 and an OAM cell generation circuit (
OCG) 6, and the receiving side device 2 includes a header conversion circuit (HC) 41 as a switching signal detection means, an FIF 036d as a delay circuit address storage section, and a third line switching control means. selectors (S) 42 and 63, control circuit (CT) 38, special address holding circuit (M) 64 and special address detection and removal circuit (D
) 65.

Next, the operation of the second embodiment will be explained.

In the second embodiment, line switching can be performed without momentary interruption. Below, a procedure for switching and switching back the line from the working line passing through the working transmission lines 3a-3d-3g to the protection line passing through the working transmission lines 3a-3e-3g will be explained.

The line switching procedure is the same as that shown in Fig. 1 except for the method of removing the delay circuit address storage section 36d of the receiving side device 2 from the protection line and the handling of special addresses. The operation after 41 receives an OAM cell addressed to its own node including a switching signal will be described.

When the header conversion circuit (HC) 41 of the receiving side device 2 receives an OAM cell addressed to its own node that includes a switching signal indicating the end of the information string, the header conversion circuit (HC) 41 converts the OAM cell to the control circuit (CT) 38.
At the same time, the control signal 35 causes the selector (S
) 63 to send the special address from the special address holding circuit (M) 64 to the address storage section 36a for each output port. The delay circuit address storage unit 36d stores the address at which the control circuit (CT) 38 receives the OAM cell and writes the cell of the protection line into the common buffer (CBF) 21 until the special address detection signal 66 is received. accumulate. When the control circuit (CT) 38 receives the OAM cell and further receives the special address detection signal 66, it temporarily stops sending out the read clock 29 to the address storage section 36a for each output port according to the control signal 31, and
Instead, a read clock is sent to the delay circuit address storage section 36d, and the address read from the delay circuit address storage section 36d is set as the subsequent address 26. As a result, the delayed cells of the protection line written in the common buffer (CBF) 21 are output to the working transmission line 3g.

Thereafter, immediately after receiving the empty signal 28 from the delay circuit address storage section 36d, the control circuit (CT) 38 directly converts the address written in the cells of the protection line into the common buffer (CBF) 21 into the address for each output port. A header conversion table rewriting signal 34 is sent so as to be written into the storage section 36a. Immediately after receiving this header conversion table rewriting signal 34, the header conversion circuit (HC) 41 changes the output transmission line number corresponding to the VPI for identifying the protection line in the header conversion table to a value corresponding to the working transmission line 3g. . After sending out the header conversion table rewriting signal 34, the control circuit (CT) 38 stops sending out the read clock 29 to the delay circuit address storage section 36d in accordance with the control signal 31, and instead transfers the read clock 29 to the address storage section 36a for each output port. A successive clock 29 is sent to the target.

This completes line switching. Line switching can also be performed in the same way as the previous line switching.

In the above explanation, address reading from the delay circuit address storage section 36d is performed using the output port address storage section 36d.
Although we have described the case where complete priority control is given to the address read from a, the delay circuit address storage section 36
The read clock may be sent to the delay circuit address memory 836d and the output port specific address memory section 36a at a constant selection ratio until there are no more addresses in d, and the read address may be used as the subsequent address 26.

In addition, in the line switching method explained above, the control circuit (CT
) 38 receives the empty signal 28 from the delay circuit address storage section 36d until the header conversion table rewriting signal 34 is sent and the header conversion table in the header conversion circuit (HC) 41 is rewritten. Between,
The address where the cells of the protection line are written to the common buffer (CBF) 21 is stored in the delay circuit address storage section 36.
It is assumed that no new data will be written to d. However, if the speed of the high-speed internal highway is high and the occupation time of one cell is short, there is a possibility that a new address will be written to the delay circuit address storage section 36d before the header conversion table is rewritten. In that case, the control circuit (CT) 38 operates in the delay circuit address storage section 36d.
After receiving the empty signal 28 from the header conversion circuit (HC) 4, a header conversion table rewriting signal 34 is sent out.
Even after the header conversion table in 1 is rewritten, the control signal 31 prioritizes the delay circuit address storage section 36d over the output port address storage section 36a for a while. When the address in 36d is completely exhausted, the priority control is canceled and the address for outputting the cell to the current transmission line 3g is read out from the address storage B3 for each output port.
The read clock 29 is sent only to the clock 6a.

In addition, in FIG. 2, the special address holding circuit (M) 64,
and special address detection and removal circuit (D) 65,
The header conversion circuit (HC) 41 writes the cell of the working line immediately before receiving the OAM cell into which the switching signal indicating the end of the information string is inserted into the common buffer (CBF) 21, and the address is stored as an address for each output port. A method is adopted in which the point in time when the light passes through the section 36a is detected. However, instead of that method, as shown in FIG. It is also possible to set the number of memory addresses for , subtract 1 from the set value every time an address is read from the address storage unit 36a for each output port, and use the point in time when the value becomes zero. . In FIG. 3, 76 is a write clock, 6B is address data to be written, 69 is address data to be read out, 70 is an up/down counter (C), 71 is a count value, 7
2 is a down counter (DC), 73 is a set signal, and 74 is a count value zero signal, and the other circuits are the same as in FIG.

In addition, FIG. 3 shows the relationship between one F I F 036a and the control circuit (CT) 38, and F I F 0
36b and 36c also have up/down counters (C) 7
0 and a down counter (DC) 72 are required. However, in FIG. 2, the write clock 76 is omitted.

The up/down counter (C) 70 is counted up by one by the write clock 76 and counted down by one by the successive clock 29. Therefore, the count value 71 indicates the number of addresses currently in the FIF○36a. A down counter (DC) 72 sets a count value 71 by a set signal 73, counts down the set value by a read clock 29, and sends out a count value zero signal 74 when the value reaches zero. Therefore, the control circuit (CT) 38 may send out the set signal 73 immediately after receiving the OAM cell, and after receiving the count value zero signal 74, proceed to the next operation.

Further, as a matter of course, if the transmission delay time of the switching destination protection line is longer than that of the working line, no address is stored in the delay circuit address storage section 36d. However, even in that case, the line switching procedure is the same as in the above case.

As described above, when the delay circuit is disconnected from the protection line in the line switching, the order of the cells is not reversed, so the actual cell arrival gap detection circuit is not required. Furthermore, since the delay circuit address storage section 366 only needs to store addresses, the memory capacity can be reduced compared to the conventional art.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

In FIG. 4, 43 is a common buffer (CBF), 45
, 46, 47, 48 and 49 are selectors (S), 4
4 is a control signal for selectors 45, 46 and 47, 50 and 51 are address chain data, 52a to 52d
, 53a to 53d1 and 54a to 54d are flip-flops (F to F4), 55a to 55d are address comparison circuits (C to C4), 56 is a set signal or address match signal, 67 is an address match signal, and 57 is a selector 48 and 49. , and 58 is a control circuit (CT), and the others are the same as in FIG.

The header conversion circuit (HC) 41 is a VPI that identifies the line.
It has a header conversion table in which the correspondence between the VPI and the transmission line number to which cells of that VPI should be output and the VPr for converting to a new VPI are written. When a real cell arrives from the high-speed internal highway, the successive clock 33 is sent to the empty address storage section 36e, one empty address is read out, and after decoding the VPI in the header of the arrived real cell, the cell is converted from the header conversion table. reads the transmission path number and new VPI that should be output, and outputs the new VPI.
Insert PI into the real cell and selector (S)
At 45, 46 and 47, a control signal 44 is sent out so that the output to the flip-flop or the manual input from the flip-flop corresponding to the transmission path number is selected. At the same time, the real cell and address chain data 50 that have arrived are written into the common buffer (CBF) 43 using the write address 25. by this,
The address read from the empty address memory ifl36e is sent to the flip-flop D (F, −F. > 52a to 52) corresponding to the transmission path to which the actual cell is to be output.
d is manually operated.

Further, flips 7 0 7 (F+ -F4) 52a to 5 corresponding to the transmission path through which the actual cells are to be output are
The address latched in 2d is the selector (S) 46
The address chain data 50 is outputted to the flip-flops (F, -F4) 53a to 53d corresponding to the transmission path to which the actual cell is to be output. Furthermore, flip-flops (Fl to F4) 53a to 53d corresponding to the transmission path through which the actual cells are to be output
The address latched in passes through the selector (S) 45 and becomes the write address 25. Common buffer (C
Address chain data 50 written to BF) 43
indicates the stored address of the real cell to be read next for a real cell written to the same address as the real cell and output to the same output transmission path. In addition,
Flip-flop (F+ ~F'4) 52a ~ 52
d, 53a to 53d1, and 54a to 54d are constructed from a plurality of flip-flops that can latch one address.

Furthermore, when the actual cell that has arrived is an OAM cell addressed to its own node, the header conversion circuit (HC) 41 sends the cell to the control circuit (CT) 58.

The common buffer (CBF) 43 writes the real cell and address chain data 50 using the write address 25, reads it using the subsequent address 26, sends the read real cell to the cell multiplexing/demultiplexing circuit (DEMUX) 22, and also writes the address chain data. 51 to the selector (S) 48. Flip-flop (F+) 52a,
53a and 54a are flip-flops and flip-flops (F2) corresponding to the current transmission line 3d (3g).
52b, 53b and 54b are the current transmission line 3e (3h
) corresponding flip-flop, flip-flop (F
3) 52c, 53c and 54C are the working transmission line 3
Flip-flops corresponding to f(3i) and flip-flops (F4) 52d, 53d and 54d are flip-flops corresponding to delay circuits.

A common buffer (CBF) 43 functions as a real cell delay circuit and its address chain. The selectors (S) 48 and 49 are controlled by a control signal 57 and are normally connected to flip-flops (F., F2, F
3) 54a, 54b, 54c are repeatedly selected in this order. However, the delayed real cells are stored in a common buffer (C'
When reading from the BF) 43, instead of selecting the flip-flops (F. to F3) 54a to 54C corresponding to the output transmission path through which the delayed actual cell is to be output, the flip-flop (F4) 54d is selected. select. The address from the selected flip-flop (F1-F4) 54a-54d passes through the selector (S) 49 and becomes the read address 26, and is stored as an empty address in the empty address storage section 36e. Address chain data 51 read by the read address 26: Well, the selected flinopfronop (Fl to F4) 54a
~54d is latched.

Address comparison circuit (C+ = C4) 55a to 55d
is usually a flip-flop (F l- F 4 )
The addresses latched in 53a to 53d and (F, to F<) 54a to 54d are compared, and if they match, an address match signal 56 is output. Note that if the addresses match, this indicates that there is no real cell or delayed real cell stored in the common buffer (CBF) 43 that should be output to the corresponding transmission path.

In addition, address comparison circuits (C, -Cl) 55a to 55C
sends the address latched to the flip-flops (F. to F:+) 53a to 53c by the set signal 56 from the control circuit (CT) 58, and transfers the set address and the flip-flops (F1 to F3) 54a to 53c. 5
The address is compared with the address latched in 4C, and if they match, an address match signal 56 is sent out. In addition,
In this case, the point at which the addresses match is the common huffer
(CBF) 43 indicates the point in time at which the empty cell is read out from the cell stored at the address set above.

The feature of the present invention is that in FIG.
and an OAM cell generator (OC) as a switching signal transmission means.
G) 6, the receiving side device 2 includes a header conversion circuit (HC) 41 as a switching signal detection means, and a flip-flop (F4) 52 as a delay circuit address storage section.
d, 53d and 54d, and selectors (S) 46, 47, 48 and 4 as third line switching control means.
9, comparison circuits (C. to C,) 55a to 55d, and a control circuit (CT) 58 are included.

Next, the operation of the third embodiment will be explained.

In the third embodiment, line switching can be performed without momentary interruption. Below, a procedure for switching and switching back the line from the working line passing through the working transmission lines 3a-3d-3g to the protection line passing through the working transmission lines 3a-3e-3g will be explained.

First, when the control circuit (CT) 58 of the receiving side device 2 receives a line switching signal from a center device (not shown), it sends out a header conversion table rewrite signal 34 and sends it from the protection line in the working transmission line 3e. A common huffer (C
The VPI for identifying the protection line is stored in the header conversion table in the header conversion circuit (HC) 41, and the flipflops (F.) 52d and 53d related to the delay circuit are stored in the delay circuit of the BF) 43. The corresponding number and the new V that the protection line uses within the working transmission line 3g.
Write PI.

Next, the control circuit (CT) 58 of the transmitting side device 1 sends a header conversion table rewriting signal so that the cell of the working line sent to the working transmission line 3d is sent to the protection line passing through the working transmission line 3e. 34 is sent.

A new VPI different from that of the working line is used for cells on the protection line passing through the working transmission line 3e. The control circuit (CT) 58 of the sending device 1 receives the header conversion table rewriting signal 3.
4, the OAM cell is sent to the OAM cell generating circuit (OCG) 6 so as to transmit the ○AM cell addressed to the receiving device 2 to the working transmission path 3d, into which a switching signal indicating the end of the information string has been inserted. Send generation instruction No. 13 1B.

On the other hand, the header conversion circuit (HC) 41 of the receiving side device 2
When the OAM cell addressed to the own node containing the switching signal is received, the OAM cell is sent to the control circuit (CT) 58. When the control circuit (CT) 53 receives the OAM cell, it sends the set signal 56 to the address comparison circuit (C+) b5a.
Send to. Thereafter, when the control circuit (CT) 58 receives an address match signal from the address comparison circuit (C1) 55a, it temporarily suspends the selection of the flip-flop (F1) 54a in the selectors (S) 48 and 49, and instead The control signal 57 is changed to select the flip-flop (F.) 54d. As a result, the real cells of the protection line stored in the common buffer (CBF) 43 are read out and sent to the working transmission line 3g. Thereafter, the control circuit (CT) 58 controls the address comparison circuit (C4
) Immediately after receiving the address match signal 56 from the address matching signal 55d, the header conversion table rewriting signal Q.1 is sent to write the cells of the protection line directly into the area within the common buffer (CBF) 43 corresponding to the working transmission line 3g. do. Immediately after receiving this header conversion table rewriting signal 34, the header conversion circuit (HC) 41 changes the output transmission line number corresponding to the VPI for identifying the protection line in the header conversion table to a value corresponding to the working transmission line 3g. . This completes line switching. Switching back the line can also be performed in the same manner as the switching described above.

In the above explanation, the flip-flop (F4) 54d and the flip-flop 7' (F,)5 related to the delay circuit are
We have described the case of priority control in which the selection is given complete priority to F4a, but the flip-flop (F4) is selected at a constant selection ratio until there are no cells on the protection line in the delay circuit.
54d and (F+) 54a may be selected.

In addition, in the line switching method explained above, the control circuit (CT
) 58 is an address comparison circuit (C4) related to the delay circuit.
) The protection line is It is assumed that no new cells will be written to the Common Hanwha (CBF) 43.

However, when the speed of the high-speed internal highway is high and the occupation time of one cell becomes short, the cell of the protection line is changed to the common vanofa (CBF) 43 before the header conversion table is rewritten.
may be written to.

In that case, even after the header conversion table of the header conversion circuit (HC) 41 has been rewritten, the control circuit (CT) 58 continues to operate the flip-flop (F+) 54a using the control signal 57 for a while. Flip flop (F4)
54d, and when there are no cells on the protection line in the delay circuit, the priority control is canceled and the address for outputting the cells to the working transmission line 3g is selected. Fl). 1) 4a
Select only

Also, as a matter of course, if the transmission delay time of the switching destination protection line is longer than that of the working line, cells of the protection line will not be accumulated in the delay circuit. but,
Even in that case, the line switching procedure is the same as in the above case.

Since the control is performed as described above, there is no need for an actual cell arrival interval detection circuit to prevent the order of cells from being reversed.

Further, since the delay circuit address storage section 36d only needs to store addresses, the memory capacity can be reduced compared to the conventional method.

The line switching systems in the first, second, and third embodiments described above can be similarly applied to the case where there is a relay node device between the sending device 1 and the receiving device 2.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention.

In FIG. 5, 3j, 3k, and 3m are backup transmission lines, and 36f is a FIF○ as an address storage section for the delay circuit.
, and 75 are delay adjustment circuits, and the others are the same as in FIG.

Normally, the selector (S) 42 selects the cells read from the common buffer (CBF) 21 according to the addresses read from the output port address memories a36a and 36b, respectively, to the working transmission lines 3d (3g) and 3e (3h).
) is controlled by a control signal 31 so that it is output to Delay circuit address storage units 36f and 36[j are
Normally, working transmission lines 3d (3g) and 3e (3g) are used, respectively.
h) An address memory for a delay circuit for delaying cells to be output. The delay adjustment circuit (A, +75) is a circuit that provides a delay equivalent to the delay caused by the special address detection and removal circuit (D) 65.

The feature of the present invention is that in FIG.
41, and an OAM cell generation circuit (OCG) 6 as a switching signal sending means, and the receiving side device 2 includes a header conversion circuit (HC) 41 as a switching signal detection means, and an OAM cell generation circuit (OCG) 6 as a switching signal detection means, and an OAM cell generation circuit (OCG) 6 as a switching signal detection means. FIFO36f and 36d
, selectors (S) 63 and 42 as third line switching means, special address holding circuit (M) 64, special address detection and removal circuit (D) 65, and delay adjustment circuit (A) 7.
5 and a control circuit (CT) 38.

Next, the operation of the fourth embodiment will be explained.

In the fourth embodiment, transmission path switching can be performed without momentary interruption. The procedure for switching from the working transmission line 3d to the protection transmission line 3k and switching back will be described below.

First, when the control circuit (CT) 38 of the receiving side device 2 receives a transmission path switching signal from a center device (not shown), it sends out a header conversion table rewrite signal 34 to each of the signals sent from the backup transmission path 3k. The real cells of the line are stored in a common buffer (CBF).
) 21 is stored in the delay circuit address storage unit 36f corresponding to the transmission path to which each line is to be output.
or the header conversion circuit (H
C) In the header conversion table in 41, the VPI for identifying each line in the protection transmission line, the corresponding number in the delay circuit address storage section 36f or 36d, and whether each line is the working transmission line 3g or 3h. Write the new VPI to be used within the program.

Next, the control circuit (CT) 38 of the transmitting device 1 first
The control signal 31 is stored in the output port address storage units 36a and 36b and the delay circuit address memory tIi36f.
The address read from the common huffer (CB
F) Each cell read from 21 is connected to the working transmission line 3.
d and 3e and the backup transmission line 3k. After that, control circuit (CT) 38',
The TSUDA conversion table rewrite signal 34 is sent out so that all lines sent out to the working transmission line 3d are sent out to the protection transmission line 3k.

As a result, the address storage unit storing the address of the cell sent to the current transmission line 3d stored in the common buffer (CBF) 21 is transferred from the output port address storage unit 36a to the delay circuit address storage unit 36a. The address is changed to the address storage section 36f. A new VPI different from each line in the working transmission line 3d is used for each line passing through the protection transmission line 3k.

The control circuit (CT) 38 of the transmitting side device 1 inserts a switching signal indicating the end of the information string to the OAM cell generation circuit (OCG) 6 immediately after sending the header conversion table rewriting signal 34. The OAM cell generation instruction signal 18 is sent out so as to send out the 0 AM cell addressed to 2 to the working transmission line 3d.

On the other hand, the header conversion circuit (HC) 41 of the receiver side station 2 is
When an OAM cell addressed to the node containing the switching signal is received, the ○AM cell is sent to the control circuit (CT) 38, and the selector (S) 63 is controlled by the control signal 35, and the special address holding circuit (M ) 64 to output port-specific address storage units 36a and 36b.
Send to. Delay circuit address storage units 36f and 3
6d, after the control circuit (CT) 38 receives the OAM cell, the address storage unit 36 for each corresponding output port
Special address detection and removal circuit corresponding to a or 36b (
D) The addresses written in the cells of the protection transmission line are stored in the common buffer (CBF) 21 until the special address detection signal 66 is received from 65. The control circuit (C
When the T) 38 receives the special address detection signal 66 from the special address detection/removal circuit (D) 65 corresponding to the output port address storage section 36a after receiving the OAM cell, the control signal 31 determines the output port address. Sending out the continuous clock 29 to the storage section 36a is temporarily stopped, and instead, the continuous clock 29 is sent to the delay circuit address storage section 36f, and the delay circuit address record {. !
The address read from the section 36f is defined as the subsequent address 26. Further, when the control circuit (CT) 38 receives a special address detection signal 66 from the special address detection/removal circuit (D) 65 corresponding to the address storage unit 36b for each output port, the control circuit (CT) 38 detects each output port by control signal 31. The transmission of the read clock 29 to the address storage section 36b is temporarily stopped, and instead, the delay circuit address storage section 36d
The address read out from the delay circuit address storage section 36d is sent to the read address 26.
shall be. With these, common buffer (CBF) 2]
The delayed cells written on the protection transmission line are output to the working transmission lines 3g and 3h.

Thereafter, when the control circuit (CT) 38 receives the empty signal 28 from the delay circuit address storage section 36f, immediately after receiving the empty signal 28, it should be output to the working transmission line 3g of the protection transmission line. The cells of the line are shared by a common carrier (C
BF) The address written to 21 is directly output as an address for each port {:! The header conversion table rewrite signal 34 is sent to write to i36a. Control circuit (CT)
38 sends out this header conversion table rewriting signal 34, and then uses the control signal 31 to cause the delay circuit address storage section 36f to
The transmission of the read clock 29 to the output port address storage section 36a is stopped, and instead, the transmission of the read clock 29 to the output port address storage section 36a is stopped.
to be sent. Further, when the control circuit (CT) 38 receives the empty signal 28 from the delay circuit address storage section 36d, immediately after receiving the empty signal 28, the control circuit (CT) 38 outputs the signal to the working transmission line 3h of the protection transmission line. A header conversion table rewrite signal 34 is sent so that the address of the line cell written into the common buffer (CBF) 21 is directly written into the output port specific address storage section 36b.

After sending out the header conversion table rewriting signal 34, the control circuit (CT) 38 stops sending out the read clock 29 to the delay circuit address storage section 36d in response to the control signal 31, and instead writes address information for each output port. The continuous clock 29 is sent out to the portion 36b. Through these controls, transmission line switching is completed. Switching back the transmission line can also be performed in the same manner as the switching described above.

In the above explanation, a case has been described in which the successive addresses from the delay circuit address register Ic sections 36f and 36d are completely prioritized and controlled over address reading from the address storage sections 36a and 36b for each output port. The read clock is sent to the delay circuit address storage section 36f (36d) and the output port address storage section 36a (36b) at a constant selection ratio until there are no more addresses in the address storage section 36f (36d) for the delay circuit. The issued address may be used as the subsequent address 26.

In addition, in the transmission line switching method explained above, the control circuit (C
T) 38 is the delay circuit address storage section 36f or 36
After receiving the empty signal 28 from d, the header conversion table rewrite signal 34 is sent to the 7da conversion circuit (
Until the header conversion table in the HC) 41 is rewritten, the cells on the protection transmission line are transferred to the common huffer (C
It is assumed that the address written to the BF) 21 will not be newly written to the delay circuit address storage section 36f or 36d. However, high-speed internal No. 1
If the wireless speed is high and the occupation time of one cell is short, there is a possibility that a new 'r address will be written to the delay circuit address storage section 36f or 36d before the header conversion table is rewritten.

In that case, after receiving the empty signal 28 from the delay circuit address storage section 36f or 36d, the control circuit (CT) 38 sends out a header conversion table rewrite signal 34 to update the header in the header conversion circuit (HC) 41. Even after the conversion table is rewritten, the control signal 3 remains unchanged for a while.
1, the output port address storage section 36a (36b
), the delay circuit address storage unit 36 f (
36d), and the delay circuit address storage section 36
When the addresses in f (36d) are completely exhausted, the priority control is canceled and the cell is transferred to the current transmission line 3g.
At the timing of reading the address for output to 3h and 3h, each output port address storage unit 36a
and 36b only. 7 Ku 29 is sent out and shifted.

In addition, in FIG. 5, the special address holding circuit (~1) 64
, and the special address detection and removal circuit (D) 65, the header conversion circuit (HC) 41 converts the cell on the current transmission line immediately before receiving the OAM cell into which the switching signal indicating the end of the information string has been inserted. The address written to the common buffer (CBF) 21 is stored in the address storage unit 3 for each output port.
6a and 36b are detected. However, instead of that method, as shown in FIG. 3, immediately after the header conversion circuit (HC) 41 receives the OAM cell into which the switching signal indicating the end of the information string is inserted, the header conversion circuit (HC) 41 stores the address by output port. Set the number of memory addresses in the unit 36a, subtract 1 from the set value every time an address is read from the address storage unit 36a for each output port, and use the point in time when the value becomes zero. You can.

Also, as a matter of course, if the transmission delay time of the protection transmission line to which switching is made is greater than that of the working transmission line, the addresses are stored in the delay circuit address register 1, sections 36f and 36(). However, even in that case, the procedure for switching the transmission path is the same as in the case described above.

As described above, when the delay circuit is separated from the backup transmission line in the transmission line switching, the order of cells is not reversed, so the actual cell arrival interval detection circuit is not required. Further, the delay circuit address storage units 36f and 36
Since d only needs to store addresses, it requires less memory capacity than the conventional method.

〔Effect of the invention〕

As described above, the present invention provides a common buffer type switch having an address storage section for each output port that stores write addresses of cells to a common buffer for each output port and performs queue processing. Separately, a delay circuit address storage section is provided which stores write addresses of cells to the common buffer and functions as a delay circuit, and after performing a desired delay using this delay circuit address storage section, Notes on address memory for circuits: Read out the addresses in order of oldest address and add them to the queue of the output port address storage section corresponding to the output port to which the delayed cell is to be output, or Priority control for performing address reading from the delay circuit address memory part with priority over address reading from the address storage part for each output port corresponding to the output port to which the delayed cell is to be output. By performing this, there is no reversal of the order of the cells, so there is an effect that the actual cell arrival interval detection circuit, which was conventionally necessary, is no longer necessary. In addition, this has the effect of shortening the time required for switching the t1 line or transmission line.

Furthermore, because this delay circuit only remembers the address of a cell written to a common buffer, it requires much less memory than a conventional delay circuit that had to store the cell itself. It has a soothing effect.

4

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a block diagram showing a second embodiment of the present invention. FIG. 3 is a block diagram showing another example of the address record/Tabe. FIG. 4 is a block diagram showing a third embodiment of the present invention. FIG. 5 is a block diagram showing a fourth embodiment of the present invention. FIG. 6 is an explanatory diagram showing an example of an information example format in the present invention. FIG. 7 is a block diagram showing a conventional example. 1... Sending side device, 2... Receiving side device, 3... Working line (transmission line), 3a to 3l... Working transmission line, 3J
~3m...Backup transmission line, 4...Backup line (transmission line), 5...Cross connect switch (XSW), 6
...OAM cell generation circuit (OCG),? , 17, 3
8, 58... Control circuit (CT), 8a, 8b... Real cell arrival interval detection circuit (RCDT), 9a, 9b.
...Actual cell arrival interval designation signal or real cell arrival interval detection signal, 10a, 10b...○A M cell separation circuit (
OCS), lla. llb...○, M cell signal, 12a, 12b...Real cell separation circuit (RC S)
, 13a, 13b...Real cell separation designation signal or real cell separation release signal, 14...First-in-first-out memory (FIF○), 15, 29, 30,
32, 33... Read clock, 16, 28... Empty signal, 18... OAM cell generation instruction signal, 1
9...Header conversion table rewriting signal, 20, 41...
・Header conversion circuit (HC), 21, 43... Common buffer (CBF), 22... Cell multiplexing/demultiplexing circuit (DEM)
'UX), 23, 24, 42, 45-49, 63...
・Selector (S), 25...Write address, 26・
...Read address, 27...OR circuit, 31, 35,
44, 57... Control signal, 34... Header conversion table rewrite signal, control signal or OAM cell signal, 36a
, 36b, 36c... Address storage section for each output port (FIFO), 36d136f... Address storage section for delay circuit (FIFO), 36e... Empty address storage section (F I F○), 37, 39. ...Interface circuit (IF), 40...Cell multiplexing circuit (MUX),
50, 51... Atres Chain Dake, 52a ~
52d, 53a ~ 53d, 54a ~ 54d
・-y limp flop (Fl ~ F 4 ), 55a
~55d... Address comparison circuit (C+ ~C4), 5
6...Set signal or address match signal, 64...
・Special address holding circuit (M), 65...Special address detection removal circuit (D), 66...Special address detection signal, 68, 69...Address data, 70...Up/down counter (C) , 71... count value,
72...Down counter (DC), 73...Set signal, 74...Count value zero signal, 75...Delay adjustment circuit (A>), 76...Write clock.

Claims (1)

[Scope of Claims] 1. A common buffer that temporarily stores arriving real cells, an address storage section for each output port that stores the write address of this common buffer, and an address storage section for each output port that is read from the address storage section for each output port. In a line switching system comprising a transmitting side device and a receiving side device, the transmitting side device includes a free address storage unit that stores addresses as empty addresses, and has a switching means for switching a working line to a protection line in units of cells. The device includes a first line switching control means for switching from the working line to a protection line at an arbitrary break in the working line, and an information string after the last cell of the working line passes through the first line switching control means. and a switching signal transmitting means for generating a switching cell including a switching signal indicating the end of the switching signal, and transmitting the switching signal to a working transmission line including a working line, and the receiving side device receives the switching signal from the sent switching cell. a switching signal detecting means for detecting the switching signal; a delay circuit address storage section operating as a delay circuit by sequentially storing addresses at which real cells arriving from the protection line are written in the common buffer; and a switching signal detecting means for detecting the switching signal. is detected, the addresses stored in the delay circuit address storage section are read in chronological order and input into the address storage section for each output port corresponding to the output port to which the delayed actual cell is to be output, and the addresses are stored. and a second line switching control means for controlling that, after all the addresses have been read, the address written into the common buffer by the real cell arriving from the protection line is directly input to the address storage unit for each output port. A line switching method characterized by: 2. When the switching signal is detected by the switching signal detecting unit instead of the second switching control unit, the receiving side device converts the address stored in the delay circuit address storage unit into a delayed real address. Read out the address with priority over the address stored in the output port specific address storage unit corresponding to the output port to which the cell is to be output, input it to the output port specific address storage unit, and store the address in the delay circuit address storage unit. and third line switching control means for controlling the address written in the common buffer to the real cell arriving from the protection line to be directly input to the output port-specific address storage unit after all the addresses have been read out. The line switching system according to claim 1.