JPH03216043A - Line switching system - Google Patents

Abstract

PURPOSE:To shorten the time required for line switching by providing an address storage section for delay circuit storing an address written with an arrived real cell to a common buffer in addition to an address storage section by each output port and acting like a delay circuit to a sender equipment. CONSTITUTION:An address storage section 36c for a delay circuit is provided, which stores a write address of a cell to a common buffer 21 and acts like a delay circuit in addition to address storage sections 36a, 36b by each output port in a common buffer switch having the address storage sections 36a, 36b by each output port storing a write address of a cell to the common buffer 21 by each output port and applying queue processing. After a desired delay is implemented by the address storage section 36c for an active transmission line or a cell of the line, a standby transmission line or a standby line is selected or the address storage sections 36a, 36b by each output port are used to delay the cell of the active transmission line by a desired time and the standby transmission line is selected. Thus, the scale of node is small and the switching is attained at a high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is utilized for time division multiplex digital transmission, and in particular,
The present invention relates to a line switching method for switching a working line or transmission line that transmits an information string in units of cells to a protection line or transmission line. Line or transmission line switching refers to switching and switching back transmission lines in the event of node or transmission line failures, relocating and switching back transmission lines due to node expansion or transmission line construction, load balancing on transmission lines, or installation of new lines. This is necessary for line accommodation replacement, etc.

[Conventional technology]

FIG. 9 is a block diagram showing an example of a conventional digital transmission device (see Japanese Patent Application No. 1-299051).

Further, FIG. 8 is an explanatory diagram showing the format of an information string (cell) on a transmission path for explaining the concept of a cell transmission system.

First, FIG. 8 will be explained. In Figure 8, VCI
．． SVCI. and VC I3 is a call identifier (hereinafter referred to as VCI) assigned to each call indicating the destination, VPIO
and VP I, is a route identifier given to each line indicating the transmission route (hereinafter referred to as VP), ■I is a header, ■ is main information, E is a bit string for identifying empty cells, and is an unused bit string, and the format of the information string consists of real cells and empty cells. However, when transmitting a frame by adding an overhead including a frame pattern to multiple cells, the format of the information string on the transmission path is composed of a real cell, an empty cell, and the above-mentioned overhead. . VCI or V
Different subscripts in the PI indicate different calls or lines. The flow of cells given the same VPI becomes a line.

VPI allows a relay device to handle multiple calls in a uniform manner by assigning the same value to multiple calls transmitted to the same destination. Same-VPI
The transmission speed of the line can be arbitrarily selected depending on the number of calls to be assigned.

The same VCI is assigned to the main information of the same call from call origination to call termination. Therefore, the flow of cells assigned the same VCI can be viewed as one line. Also, since the transmission line is treated as one line or multiple lines, it can also be seen as a single line.

A line configured by VCI or vPI is not a physical line that always exists on a transmission path, but a logical line that exists only when a call occurs.

Therefore, the relay device only sends the cell to the intended outgoing route according to the VCI or VPI of each cell only when the cell arrives. For this reason, each relay device has VCI
Alternatively, it has a table in which outgoing route numbers are written for each VPI.

Next, FIG. 9 will be explained. In FIG. 9, ■ is a transmitting side device, 2 is a receiving side device, 3 is a working line or transmission line, 4 is a protection line or transmission line, 5 is a cross-connect switch (XSW) that switches on a cell-by-cell basis,
6 is a real cell arrival interval detection circuit (RCDT); 7 is a real cell arrival interval designation signal or a real cell arrival interval detection signal; 8
9 is a real cell separation circuit (RCS), 9 is a real cell separation designation signal or real cell separation release signal, 10 is a first-in-first-out memory (hereinafter referred to as FIFO),
11 is a series of clocks, 12 is empty (5hi, 13
is a header conversion table rewriting signal, and 14 is a control circuit (CT). Here, the function of the delay circuit is FIFOI
O will do it.

The cross-connect switch (XSW) 5 inputs a header conversion table containing the VPI for identifying all the lines accommodated in the large transmission line and the output route number of each line in correspondence with the VPI for each input transmission line. The header conversion table allows the V in the header of each arriving real cell to be
The cell is sent out to the corresponding output route according to the PI. The header conversion table may be converted to a control circuit (CT) if necessary.
By the header conversion table rewrite signal 13 from 14,
Additions and rewrites are made.

The real cell arrival interval detection circuit (RCDT) 6 normally allows the arrived cells to pass through as is, but the control circuit (CT)
When the real cell arrival interval designation signal 7 belonging to the cells of the plurality of VPIs specified from 14 is received, the arrival interval of the real cells belonging to the cells of the plurality of specified VPIs that arrive thereafter is measured, and the specified real cell is If a real cell belonging to a cell of a plurality of specified VPIs does not arrive for a period of time greater than the cell arrival interval, a real cell arrival interval detection signal 7 is sent to the control circuit (CT) 14, and thereafter the normal operation is performed. Return to state.

The real cell separation circuit (RCS) 8 normally allows each arriving cell to pass through as is, but when it receives the real cell separation designation signal 9 belonging to cells of multiple VPIs specified by the control circuit (CT) 14, it The real cells belonging to the designated plurality of VPI cells that arrive thereafter are separated and sent to the PIFOIO. The real cell separation circuit (RCS) 8 includes a control circuit (
When the actual cell separation release signal 9 is received from CT) 14, the normal state is returned to the above-mentioned state.

If the read clock 11 has not arrived, the FIFOIO stores the written real cells and uses the read clock 11.
If the cell has arrived, the accumulated real cells are read out by the successive clock l1. When a real cell in the FIFOIO becomes empty, an empty signal 12 indicating this is sent to a control circuit (CT) 14.

Next, referring to FIG. 9rl, an explanation will be given of an operation procedure for switching transmission lines without momentary interruption.

First, when the control circuit (CT) 14 of the receiving side device 2 receives a transmission path switching signal from a center device (not shown), it sends out a header conversion table rewriting signal 13 and sends a header conversion table rewrite signal 13 to the spare header in the cross-connect switch (XSW) 5. Copy the contents of the header conversion table corresponding to the current transmission line to be switched to the header conversion table corresponding to the transmission line.

Next, the control circuit (CT) 14 of the transmitting side device 1 controls the cross-connect switch (XSW) when the transmission delay of the protection transmission line is larger than that of the current transmission line in the transmission line switching section.
A header conversion table rewriting signal 13 is sent to all the header conversion tables corresponding to the input transmission paths in 5 so that all lines sent to the working transmission path 3 are sent to the protection 7-transmission path 4. This completes the transmission line switching.

On the other hand, in the transmission line switching section, if the transmission delay of the backup transmission line is smaller than that of the active transmission line, the control circuit (CT) 14
First, the header conversion table rewrite signal 13 is used to write the VPI that identifies all the lines sent to the current transmission path 3 and their The output transmission line number is written so that the cells of VPI are sent to the protection transmission line 4. Next, the control circuit (CT) 14 identifies all the lines sent to the working transmission line 3 to the real cell separation circuit (RCS) 8 while stopping the sending of the read clock 11. A real cell separation designation signal 9 is sent to separate the cells of the VPI. Thereafter, the control circuit (CT) 14 starts transmitting the read clock l1 after a time period equal to or longer than the transmission delay difference between the working and backup transmission lines in the transmission line switching section has elapsed. The cells read out by the successive clock 11 pass through the path (2) in the cross-connect switch (XSW) 5. after that,
When the control circuit (CT) 14 receives the empty signal 12, the control circuit (CT) 14 transfers data from the real cell separation circuit (RCS) 8 to the FIFO 1.
0 to the output terminal of the cross-connect switch (XSW) 5 as the actual cell arrival interval designation signal 7 for seven of all lines passing through the FIFOIO, together with the VPI that identifies those lines. It is sent to the real cell arrival interval detection circuit (RCDT) 6. Thereafter, immediately after receiving the real cell arrival interval detection signal 7, the control circuit (CT) 14 converts the real cell separation release signal 9 and all the header conversion tables corresponding to the human transmission paths in the cross-connect switch (XSW) 5. On the other hand, a header conversion table rewriting signal 13 is sent so that all the lines that were sent to the working transmission line 3 are sent to the protection transmission line 4.

As a result, the line cells sent to the protection transmission line 4 are
The cross-connect switch (XSW) 5 allows the path (■) to be passed through. With the above, the transmission line switching in this case is completed.

Note that the switching back of the transmission line can also be performed in the same manner as the switching described above.

In addition, line switching is performed by a real cell arrival interval detection circuit (RCDT) 6 and a real cell separation circuit (RCS) 8 in FIG.
is a circuit that functions only for the VPI cell that identifies one line to be switched, and the cross connect switch (
By rewriting the header conversion table in XSW 5 only for the line to be switched, it is possible to perform the same procedure as in the case of transmission line switching.

[Problem that the invention seeks to solve]

Transmission path switching and line switching in the conventional example shown in FIG.
W) It is necessary in addition to the buffer in 5, which has the drawback of increasing the hardware scale.

In addition, when disconnecting FIFOIO as a delay circuit from the protection transmission line or protection line, the real cell arrival interval detection circuit (RCDT) 6
This is carried out when continuous empty cells continue for cells in the transmission line or line to be switched for a period of time corresponding to the time during which no cell order reversal occurs. This method is mainly used because the delay time passing through the cross-connect switch (XSW) 5 varies. However, when the usage rate of the transmission path or line is high, there is a drawback that it takes a long time to wait until the desired continuous empty cells arrive.

In addition, a real cell arrival interval detection circuit (RCD) is installed for each transmission path.
T) There is a drawback that 6 is required. Transmission paths or lines may need to be switched for multiple lines, and switching back is also required, and in order to share PIFOIO as a delay circuit, it is necessary to disconnect PIF010 as a delay circuit after each switch. There is a need.

SUMMARY OF THE INVENTION An object of the present invention is to provide a line switching system that has a small node size and can switch at high speed by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a common buffer that temporarily stores arriving real cells, an output port-specific address storage section that stores addresses at which real cells are written to the common buffer, and addresses read from the output port-specific address storage section. In a line switching system comprising a transmitting side device and a receiving side device, including an empty address storage section for recording 1,α as an empty address, and a switching means for switching a working line to a protection line in units of cells. , the transmitting side device includes a delay circuit address storage section which is provided separately from the output port specific address storage section and which stores an address at which an arriving real cell is written into the common buffer and operates as a delay circuit; In the switching section, if the delay time of the protection line or transmission line is greater than the delay time of the working line or transmission line, switching is performed at an arbitrary cell break, and if it is smaller, the actual cell of the working line or transmission line is switched. control for switching to the protection line or transmission line after delaying the signal by a time equal to or longer than the transmission delay difference between the working and protection lines or transmission lines in a predetermined line switching section by using the delay circuit address storage unit. and a first line switching control means that performs the following: the receiving side device multiplexes real cells among the cells transmitted by the working line or transmission line and the protection line or transmission line into one line. It is characterized in that it includes real cell multiplexing means.

Further, the present invention provides a common buffer that temporarily stores arriving real cells, an address storage section for each output port that stores the address at which the real cell is written to this common buffer γ, and an address storage section for each output port that reads from the address storage section for each output port. an empty address storage unit that stores the received address as an empty address,
In a line switching system that includes a transmitting side device and a receiving side device that have switching means for switching a working line to a protection line in units of cells, the sending side device switches between a protection line and a protection line in a predetermined line switching section. If the delay time of the line or transmission line is larger than the delay time of the currently used line or transmission line, switching is performed at an arbitrary cell break, and if it is smaller, the actual cell of the currently used transmission line is switched according to the corresponding output port. A second line that performs control to switch to the protection transmission line after delaying address reading from the storage unit by stopping for a time equal to or longer than the transmission delay difference between the working and protection transmission lines in a predetermined line switching section. The receiving side device includes a switching control means, and the receiving side device includes an actual cell multiplexing means for multiplexing, into one line, real cells among the cells transmitted by the working line or transmission line and the protection line or transmission line. It is characterized by

[Effect]

In the present invention, in a common buffer type switch having an address storage section for each output port that stores write addresses of cells to a common buffer for each output port and performs queue processing,
Separately from the address storage section for each output port, there is provided a delay circuit address storage section that stores write addresses of cells to the common buffer and functions as a delay circuit. After delaying the cells of the transmission line or circuit for a desired time, switching to the protection transmission line or line, or after delaying the cells of the working transmission line for a desired time using the address storage unit for each output port. By switching to the backup transmission line, the cell order reversal caused by delay fluctuations in the conventional cross-connect switch is eliminated, so the actual cell arrival interval detection circuit is no longer necessary. Additionally, the time required for line or transmission line switching is therefore shortened. Furthermore, this delay circuit stores only the address of a cell written to the common buffer, so compared to a conventional delay circuit that had to store the cell itself, each cell has 53 bytes of address information. Assuming that the number of bits is 10 bits, the required memo IJ ffi may be 1/40 or less. Note that since the common buffer is used in common for all transmission lines, there is sufficient free memory capacity for delaying cells on the protection line or transmission line.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, 3a to 3[ are current transmission lines, 39 is an interface circuit (IF) for optical-to-electrical conversion, bit synchronization, cell synchronization, etc., 40 is a cell multiplexing circuit (MUX),
20 is a header conversion circuit (HC), 21 is a common buffer (CBF), and 22 is a cell multiplexing/demultiplexing circuit (DEMUX).
, 23 and 24 are selectors (S), 25 is a write address of the common buffer (CBF) 21, 26 is a continuation address of the common buffer (CBF) 21, 27 is an OR circuit, 2
8 is an empty signal, 29 and 30 are read clocks, 31 is a control signal for the selector (S) 24, 32 and 3
3 is a FIFO read clock, 34 is a header conversion table rewrite signal or control signal, and 35 is a selector (S) 23.
The control signals 36a and 36b are F I F0, 36c as address storage units for each output port corresponding to the current transmission lines 3C (3e) and 3d (3f), respectively.
is l” I F O as an address storage section for the delay circuit.
, 36d is empty address record 1, FIFO as α section,
37 is an interface circuit (IF>) for cell synchronization button insertion and electrical-to-optical conversion, etc.; 38 is a control circuit (CT);
41 is a write clock to FFO, 42 is a control signal, 4
3 is an up/down count (C), 46 is a count value, 44 is a down count (DC), and 45 is a set signal or a count value zero signal.

Hereinafter, as necessary, 36a and 36b will be referred to as output port address storage 1, α section, or simply FIFO, and similarly, 36C will be referred to as delay circuit address storage section or FIFO,
36d is denoted as an empty address storage unit or FIFO.

A cell multiplexing circuit (MUX) 40 multiplexes cells arriving from the transmission line in units of cells, and outputs the multiplexed cells to a high-speed internal highway at a speed several times the input transmission line speed.

A header conversion circuit (HC) 20 has a VPI that identifies the line.
It has a header conversion table in which the correspondence between the VPI and the transmission line number to which cells of that VPI should be output and the VPI to be converted to a new VPI are written. When a real cell arrives from the high-speed internal highway, the read clock 33 is sent to the empty address storage section 36d, one empty address is read out, and after decoding the VPI in the header of the arrived real cell, the cell is converted from the header conversion table. reads the transmission path number and new VPI that should be output, and outputs the new VPI.
Insert PI into the real cell and select (S)
At step 23, a control signal 35 is sent out so that the output port address storage section 36a or 36b corresponding to the transmission line number is selected. Also, at the same time, the arrived real cell is sent to the common buffer (CBF) 21. As a result, the real cell has a common buffer (CBF) 21
is written into the empty address position read from the empty address storage section 36d. Further, the address at which the real cell is written in the common buffer (CBF) 21 is stored in the output port address storage unit 36a or 36b corresponding to the output transmission line to which the real cell is to be output.

A common buffer (CBF) 21 writes a real cell at a write address 25, reads it at a subsequent address 26, and sends the read real cell to a cell multiplexing/demultiplexing circuit (DE).
MUX) 22. Cell multiplexing/demultiplexing circuit (DEMU)
X) 22 converts the arriving real cells to the transmission path speed according to the order of arrival, and then transfers them to the working transmission path 3c (3e) or 3d.
(3f) and output. During times when no real cells arrive, empty cells are sent to the corresponding transmission path. F I F
036a to 36d send out the stored address while the read clock is applied. When there are no more addresses stored in the FIFO, an empty signal 28 is sent out. Up/down counter (C) 43
is counted up by one by the write clock 41 and counted down by one by the read clock 29. Therefore, count value 46 indicates the number of addresses currently in the FIFO. The down counter (DC) 44 is a control circuit (
The count value 46 is set by the set signal 45 from CT) 38.
is set, the set value is counted down by the successive clock 29, and when the value reaches zero, a count value zero signal 45 is sent to the control circuit (CT) 38.

The selector (S) 24 stores an output port address storage unit 3 corresponding to the output transmission path selected by the control signal 31.
6a and 36b, and output port specific address storage sections 36a and 36b.
The address read out is sent to the common buffer (CBF) 21 as a subsequent address 26, and is sent as an empty address to the empty address storage section 36d. The control signal 31 repeatedly selects the output port address storage sections 36a and 36b in order so that cells can be separated in the order of the working transmission lines 3c (3e) and 3d (3f) in the cell multiplexing and demultiplexing circuit (DEMUX) 22. Give as you please.

The feature of the present invention is that in FIG. 1, the transmitting side device 1 includes a delay circuit address storage section 36C, a header conversion circuit (HC) 20 as a first line switching control means, an OR circuit 27, a selector ( S) 23 and 24, an up/down counter (C) 43, a down counter (DC) 44, and a control circuit (CT) 3g, and the receiving side device 2 includes a cell multiplexing circuit (MUX) as a real cell multiplexing means. )40
It is to include.

Next, the switching operation of the first embodiment will be explained.

The first embodiment can be used for switching lines without momentary interruption. Below, the procedure for switching and switching back the line from the working line passing through the working transmission lines 3a-3c3e to the protection line passing through the working transmission lines 3a-3d3e will be explained.

First, when the control circuit (CT) 38 of the receiving side device 2 receives a line switching signal from a center device (not shown), it sends out a header conversion table rewrite signal 34 from the protection line in the working transmission line 3d. The incoming real cells are stored in a common buffer (
The VPI for identifying the protection line and the output port address are stored in the header conversion table in the header conversion circuit (HC) 20 so that the address written in the CBF) 21 is stored in the output port address storage unit 36a. The number corresponding to the storage unit 36a and its backup line are the working transmission line 3.
Write a new VPI to be used within e. This results in
The receiving side device 2 becomes a real cell multiplexing circuit that multiplexes a working line and a protection line into one line.

Next, in the line switching section, if the transmission delay of the protection line is larger than that of the working line, the control circuit (CT) 38 of the transmitting side device 1 controls the working line that is sent to the working transmission line 3C as is. A header conversion table rewriting signal 34 is sent so that the cell is sent to the protection line passing through the working transmission line 3d.
Send out. When the header conversion circuit (HC) 20 receives this conversion table rewriting signal 34, the header conversion circuit (HC) 20 converts the actual cells sent from the working line in the working transmission line 3a into the common buffer (HC).
Write the old address in BF) 21 in the output port address memory 36b, and write the number corresponding to the output port address memory 36b in the header conversion table and confirm that the line is a backup line. As the current transmission line 3d
Write a new VPI to be used within. Current transmission line 3d
The cell of the protection line passing through the line has a new V
PI is used. With the above steps, line switching in this case is completed.

On the other hand, in the line switching section, if the transmission delay of the protection line is smaller than that of the working line, the control circuit (CT) 38 of the transmitting side device 1 first sends the header conversion table rewrite signal 3.
4, and wrote the actual cell sent from the working line in the working transmission line 3a into the common buffer (CBF) 21 in the header conversion table of the header conversion circuit (HC) 20.The address is set as the address for the delay circuit. The number corresponding to the delay circuit address storage unit 36C and the line are stored in the storage unit 36C as a protection line and are stored in the working transmission line 3d.
Writes a new VPI to be used within. Control circuit (C
Immediately after sending the header conversion table rewriting signal 34, the T) 38 sends a set signal 45 to the down counter (DC>44) corresponding to the output port address storage section 36a.

Thereafter, after receiving the count value zero signal 45 from the down counter (DC) 44, the control circuit (CT) 38 receives the count value zero signal 45 from the down counter (DC) 44, and from that point on, the control circuit (CT) 38 receives the count value zero signal 45 from the down counter (DC) 44. Later, the header conversion circuit (
A control signal 34 is sent to the HC) 20. When the header conversion circuit (HC) 20 receives the control signal 34, it sends out successive clocks 30 during the occupied time of empty cells that arrive thereafter, and transfers the clocks from the delay circuit address storage section 36C to the common buffer (CBF) 21. The written address of the cell of the protection line is read and sent to the OR circuit 27. Also,
At the same time, the address read out from the delay circuit address storage section 36C is output port specific address record 1,
The control signal 35 of the selector (S) 23 is sent out so that it is written into the α section 36b.

Thereafter, immediately after receiving the empty signal 28 from the delay circuit address storage section 36C, the control circuit (CT) 38 writes the cell of the working line into the common buffer (CBF) 21 and directly stores the address for each output port. Header conversion table rewrite signal 3 to write to section 36b
Send 4. Immediately after receiving the header conversion table rewriting signal 34, the header conversion circuit (HC) 20 changes the output transmission line number corresponding to the VPI for identifying the working line in the header conversion table to a value corresponding to the transmission line 3d, and
Thereafter, the transmission of the read clock 30 to the delay circuit address storage section 36C is stopped. This completes the line switching in this case.

Note that switching back the line can also be performed in the same manner as the above-mentioned switching.

As described above, the speed of the high-speed internal highway is not so high, and after the control circuit (C, T) 38 receives the empty signal 28 from the delay circuit address storage section 36c, the header conversion table rewrite signal is sent. If the time from sending out 34 to rewriting the header conversion table in the header conversion circuit (HC) 20 is 10 times smaller than the time taken for one cell to pass through the header conversion circuit (HC) 20, then , since the order of cells is not reversed, an actual cell arrival interval detection circuit is not required. Further, since the delay circuit address storage section 36c only needs to store addresses, the memory capacity can be reduced compared to the conventional method.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In FIG. 2, 47 is a header conversion circuit (HC), 48
is a selector (S), and the others are the same as in FIG.

Header conversion circuit (HC) 47 is similar in function to header conversion circuit (HC) 20 of FIG. 1, except that it does not send out read clock 30. The selector (S) 48 is
The read clock 32 is applied to the output port address register 1, α section 36a or 36b corresponding to the output transmission path selected by the control signal 31, and the address read from the output port address storage section 36a or 36b is read out. , a common buffer (CB
F) Send to 21 and send as an empty address to empty address record 1 and α section 36d. The control signal 31 is normally sent to the address storage units 36a and 36b for each output port so that cells can be separated in the order of the working transmission lines 3c (3e) and 3d (3f) in the cell multiplexing/demultiplexing circuit (DEMUX) 22. Give them a repeat selection in order. However, when it is necessary to read an address from the delay circuit address storage section 36C, the control circuit (CT) 38 uses an output port-specific address corresponding to the transmission line to which the delayed protection line cells are to be output. The control signal 31 is sent to select the delay circuit address storage section 36C instead of selecting the storage section 36a or 36b.

The feature of the present invention is that in FIG. 2, the transmitting device 1 includes a delay circuit address storage section 36C, a header conversion circuit (IC) 47 as a first line switching control means, and a selector (S) 23. and 48, Up Down Count (C
) 43, a down counter (DC) 44, and a control circuit (CT) 38, and the receiving side device 2 includes a cell multiplexing circuit (MIX) 40 as a real cell multiplexing means.

Next, the switching operation of the second embodiment will be explained.

In the second embodiment, line switching can be performed without momentary interruption. Below, the procedure for switching and switching back the line from the working line passing through the working transmission lines 3a-3c-3e to the protection line passing through the working transmission lines 3a-3d-3e will be explained.

The line switching procedure is the same as that shown in FIG. 1, except for the method of removing the delay circuit address memory 836C of the transmitting side device 1 from the backup line, so here, in the line switching section,
The operation of the sending device 1 when the transmission delay of the protection line is smaller than that of the working line will be described.

The control circuit (CT) 3g of the transmitting side device 1 first sends out a header conversion table rewriting signal 34, and the header conversion table of the header conversion circuit (HC) 47 is sent from the working line in the working transmission line 3a. The real cells that come are transferred to a common buffer (C
In order to store the address written in BF) 21 in the delay circuit address memory 36c, the number corresponding to the delay circuit address record 1, α part 36C and the line are stored in the working transmission line 3d as a protection line. New VP used in
Write I. Immediately after sending out the header conversion table rewrite signal 34, the control circuit (CT) 38 controls a down counter (DC) corresponding to the address storage section 36a for each output port.
) 44 and sends out a set signal 45. Thereafter, after receiving the count value zero signal 45 from the down counter (DC) 44, the control circuit (CT) 38 receives the count value zero signal 45 from the down counter (DC) 44, and from that point on, the control circuit (CT) 38 receives the count value zero signal 45 from the down counter (DC) 44. Later, the address storage section 36b for each output port
The address reading from the delay circuit address storage unit 36C is temporarily stopped, and instead of reading the address from the common buffer (C
The control signal 31 is changed so that the address of the cell of the protection line written in the BF) 21 is read out.

After that, the control cycle Ha. Immediately after receiving the empty signal 28 from the delay circuit address storage unit 36C, the (CT) 38 transfers the cells of the working line to the common buffer (CBF) 2.
A header conversion table rewrite signal 34 is sent so that the address written in 1 is directly written in the output port address record 1, α section 36b. Header conversion circuit (HC) 4
Immediately after receiving the header conversion table rewriting signal 34, the output transmission line number corresponding to the VPI identifying the working line in the header conversion table is changed to a value corresponding to the transmission line 3d.

The control circuit (CT) 38 sends out the header conversion table rewrite signal 34 and simultaneously writes the delay circuit address 1, α.
The control signal 31 is changed so as to stop sending the successive clock 29 to the section 36C and instead restart sending the read clock 29 to the output port address storage section 36b. This completes the line switching in this case.

Note that switching back the line can also be performed in the same manner as the above-mentioned switching.

In the following description of L, address reading from the delay circuit address storage section 36c is performed using the address storage section 3 for each output port.
Although we have described the case where the address reading from the address storage section 6b is completely controlled, the delay circuit address storage section 3
A read clock may be sent to the address storage section 3Gc for the κ extension circuit and the address storage section 36b for each output port at a constant selection ratio until there are no more addresses in 6C, and the read address may be used as the subsequent address 26. .

In addition, in the line switching method explained above, the control circuit (CT
) 3g receives the empty signal 28 from the delay circuit address storage section 36C until the header conversion table rewriting signal 34 is sent and the header conversion table in the header conversion circuit (HC) 47 is rewritten. Between,
The address where the cells of the working line are written to the common buffer (CBF) 21 is stored in the delay circuit address storage section 36C.
It is assumed that no new data will be written to. However, when the speed of the high-speed internal highway is high and the occupation time of one cell becomes short, the new address is transferred to the delay circuit address storage section 3 before the header conversion table is rewritten.
There is a possibility that it will be written to 6c. In that case, the control circuit (CT) 38 includes the address register 1 for the delay circuit, the α section 36
After receiving the empty signal 28 from C, the header conversion table rewrite signal 34 is sent to the header conversion circuit (HC).
Even after the header conversion table in 47 is rewritten, the control signal 31 causes the delay circuit address storage 36 to be sent to the output port address storage 36b.
When the address in the delay circuit address storage section 36C is completely exhausted, the 93-advance control is canceled and the output port The read clock 29 is sent only to the separate address storage section 36b.

As described above, when the delay circuit is disconnected from the protection line in the line switching, the order of cells is not reversed, so the actual cell arrival interval detection circuit is not required.

Furthermore, since the address storage section 36C for the delay circuit only needs to store addresses, the memory capacity can be reduced compared to the conventional art.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

In FIG. 3, 3g, 3h and 3l are backup transmission lines, and the others are the same as those shown in FIG.

The control signal 31 from the control circuit (CT) 38 is normally
An address storage unit 36a for each output port is configured so that the cells read from the common buffer (CBF) 21 can be separated in the cell multiplexing/demultiplexing circuit (DEMUX) 22 in the order of the working transmission lines 3c (3e) and 3d (3f). and 36b for repeated selection. In this case, all empty cells are sent from the cell multiplexing/demultiplexing circuit (DEMUX) 22 to the backup transmission line 3h (31).

However, when reading an address from the delay circuit address storage section 36C, this control signal 31 is used to transfer the cell read from the common buffer (CBF) 21 to the cell multiplexing/demultiplexing circuit (DEMUX) 22 through the backup transmission path. 3h
(31) can also be separated, the delay circuit address storage section 36C is also selectively provided.

The feature of the present invention is that in FIG. 3, the delay circuit address storage section 36c also has an up/down counter (C) 43
and down counter (same as in Figure 2 except that DC>44 is added).

The switching operation of the third embodiment will be explained below.

The third embodiment can be used for switching transmission lines without momentary interruption. Below, from the working transmission line 3c to the protection transmission line 3
The procedure for switching the transmission path to h and switching back will be explained.

First, when the control circuit (CT) 38 of the receiving side device 2 receives a transmission path switching signal from a center device (not shown), it sends out a header conversion table rewriting signal 34, and all signals sent from the backup transmission path 3h are In order to output the cells of each line to the same transmission line as the cells of each line sent from the working transmission line 3c, the VPI that identifies all the lines on the protection transmission line 3h and the corresponding VPI are set. Then, the output transmission path number and the new VPI used in the output transmission path are written in the header conversion table of the header conversion circuit (HC) 47. This new VPI is the V of each line in the current transmission line 3c.
The PI is the same as the new VPI to which it is converted. Thereby, the receiving side device 2 becomes a real cell multiplexing circuit that multiplexes each line in the working transmission line and each line in the protection transmission line into one line.

Next, the control circuit (CT) 38 of the transmitting side device 1 controls all of the signals sent to the working transmission line 3C if the transmission delay of the protection transmission line is larger than that of the working transmission line in the transmission line switching section. A header conversion table rewriting signal 34 is sent out so that the line is sent out to the protection transmission line 3h. The header conversion circuit (HC) 47 performs the header conversion table rewriting 34.
When a signal is received, the actual cells of those lines are written into the common buffer (CBF) 21 and the addresses are stored so that all the lines that have been output to the working transmission line 3c are output to the protection transmission line 3h. From the output port address storage unit 36a to the delay circuit address storage RE 3 6
c, for all VPIs that identify those lines in the header conversion table, the number corresponding to delay circuit address 1, @ section 36C and the line of that VPI are reserved. Write a new VPI to be used within the transmission path 3h. Another new VPI is used for the line passing through the protection transmission line 3[1 to distinguish it from the line passing through the working transmission line 3c.

The control circuit (CT) 38 sends a set signal 45 to the down counter (DC) 44 corresponding to the output port address storage section 36a at the same time as sending out the header conversion table rewriting signal 34. After that, the control circuit (CT) 38
After receiving the count value zero signal 45 from the down counter (DC) 44, the selector (S) 48 sends a control signal 31 to select only the output port address storage section 36b and the delay circuit address storage section 36c. change. With the above, the transmission line switching in this case is completed.

On the other hand, the control circuit (CT) 38 of the transmitting side device 1 controls the control circuit (CT) when the transmission delay of the protection transmission line is smaller than that of the working transmission line in the transmission line switching section, compared to the case where the transmission delay is large. After the CT) 38 receives the count value zero signal 45 from the down counter (DC) 44 corresponding to the output port address storage section 36a, from that point on, the current and backup transmission lines in the transmission line switching section are The only difference is that the control signal 31 is changed after I, which is equal to or greater than the transmission delay difference, and the other operations are the same.

In addition, in the above explanation, the control circuit (CT) 38
is the count value zero signal 45 from the down counter (DC) 44 corresponding to the output port address storage section 36a.
Instead of using the address storage section 36a for each output port,
You may also use the embedded signal 28 from.

The transmission path is switched back using the address storage section 36a for each output port.
By simply using the circuit as a delay circuit, the operating procedure can be performed in the same manner as the switching described above.

Since the control is performed as described above, there is no need for an actual cell arrival interval detection circuit to prevent the order of cells from being reversed.

Further, since the delay circuit address storage section 36C only needs to store addresses, the memory capacity can be reduced compared to the conventional method.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

In FIG. 4, 49 and 50 are selectors (S), and the others are the same as shown in FIG. 3.

The operation of the selector (S) 49 is the same as that of the selector (S) 2 in Fig. 3.
It is the same as 3. The successive clock 29 from the selector (S) 50 has three timing phases corresponding to the output transmission path, and the control signal 31 from the control circuit (CT) 38
Therefore, normally, the cells read from the common buffer (CBF) 21 are sent to the cell multiplexing/demultiplexing circuit (DEMUX) 22.
, the working transmission lines 3C (3e) and 3d (3
The read clocks 29 of the first and second timing phases are selected to be repeatedly applied to the output port address storage units 36a and 36b, respectively, so that the separation can be performed in the order of f). In this case, the backup transmission line 3h
At (3i), all empty cells are sent out from the cell multiplexing/demultiplexing circuit (DEMUX) 22. However, depending on the address read from the address storage section 36a or 36b for each output port, the cell read from the common buffer (CBF) 21 is transferred to the backup transmission line 3h (3i) in the cell multiplexing/demultiplexing circuit (DEMUX) 22. In the case of separating into two, the control signal 31 selects so that the successive clock 29 of the third timing phase corresponding to the backup transmission line 3h (3i) is given to the output port address storage unit 36a or 36b. be done.

The feature of the present invention is that in FIG.
7, selectors (S) 49 and 50, up/down counter (C) 43, down counter (D) 44, and control circuit (CT) 38;
Cell multiplexing circuit (MUX) 4 as actual cell multiplexing means
The purpose is to include 0.

Next, the switching operation of the fourth embodiment will be explained.

The fourth embodiment can be used for switching transmission lines without momentary interruption. Below, from the working transmission line 3C to the backup transmission line 3h
The following describes the procedures for switching the transmission path to and switching back to.

First, the receiving side device 2 performs the same control as in the case of FIG.

Next, the control circuit (CT) 38 of the transmitting side device 1 first sends out a header conversion table rewriting code 34 if the transmission delay of the protection transmission line is larger than that of the working transmission line in the transmission line switching section. do. The header conversion circuit (HC) 47 is
When the header conversion table rewriting signal is received, only the VPI to be used in the next transmission line section is set aside for each VPI that identifies the human line in the header conversion table for all lines that have been output to the working transmission line 3C. Change to a new VPI used within the transmission path 3h. Spare transmission line 3h
Another new VPI is used for the line passing through 3C to distinguish it from the line passing through the current transmission line 3C.

The control circuit (CT) 38 sends a set signal 45 to the down counter (DC) 44 corresponding to the output port address storage section 36a at the same time as sending out the header conversion table rewriting signal 34. After that, the control circuit (CT) 38
Immediately after receiving the count value zero signal 45 from the down counter (DC) 44, in the selector (S) 50,
The control signal 3 is used to change the timing phase of the read clock 29 given to the output port specific address storage section 36a to the third timing phase corresponding to the backup transmission line 3h.
Sends 1. With the above, the transmission line switching in this case is completed.

On the other hand, the control circuit (CT) 3g of the transmitting side device 1 controls the control circuit (CT) when the transmission delay of the protection transmission line is smaller than that of the working transmission line in the transmission line switching section, compared to the case where the transmission delay is large. Immediately after the CT) 3g receives the count value zero signal 45 from the down counter (DC) 44 corresponding to the address storage unit 36a for each output port, the transmission delay of the working and backup transmission lines in the transmission line switching section starts from that point. For a time longer than the difference, the control signal 3l stops sending out the readout tarlock 29 to the output port address storage section 36a, and then the output port address storage section 36a corresponds to the backup transmission line 3h. The only difference is that the selector (S) 50 is controlled to provide the third timing phase, and the other operations are the same.

Note that switching back the transmission line can also be performed in the same manner as the switching described above by changing the control of the selector (S) 50.

Since the control is performed as described above, there is no need for an actual cell arrival interval detection circuit to prevent the order of cells from being reversed.

Furthermore, since the output port address register 1, α section 36a, which is also used as a delay circuit, only needs to store addresses, the memory capacity can be reduced compared to the conventional system.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention.

In FIG. 5, 51 is a common buffer (CBF), 52
, 53, 54, 55 and 56 are Selekku (S), 57
are control signals for selectors 52, 53 and 54, 58 and 59 are address chain data, 60a to 6Qc,
61a to 61c, 62a to 62c are flip-flops (F., F2, F3), 63a to 63c
is the address comparison circuit (C,, C2, C3), 64
2 is a set signal or an address match signal, 65 is an address match signal, 66 is a control signal for selectors (S) 55 and 56, and 67 is a control circuit (CT), and the others are the same as in FIG.

A header conversion circuit (HC) 47 has a VPI that identifies the line.
It has a header conversion table in which the correspondence between the VPI and the transmission line number to which cells of that VPI should be output and the VPI to be converted to a new VPI are written. When a real cell arrives from the high-speed internal highway, the successive clock 33 is sent to the empty address register 1, α section 36d, one empty address is read out, and after decoding the VPI in the header of the arrived real cell, the header conversion table is reads the transmission path number and new VPI to which the cell should be outputted, inserts the new VPI into the actual cell, and selects the selector (
S) Flip-flops (F., F2, F3) 60a corresponding to the transmission line numbers in 52, 53 and 54;
Output to ~60C or 6la~61C, Mataha flip-flop (F+, F2, F3) 60a~60
A control signal 57 is sent out so that C or human power from 61a to 61C is selected. At the same time, the real cell and address chain data 58 that have arrived are written into the common buffer (CBF) 51 using the write address 25.

With this, empty address record 1. The address read from the @ section 36d is sent to the flip-flops (F., F2, F3) corresponding to the transmission path through which the actual cell is to be output.
60a, 60b, and 60c are manually operated. Furthermore, flip-flops (F+SF2, F3) 60a, 5Qb,
The address latched in 60C is selector (S) 5
3 to become address chain data 58, and flip-flop 07 (F+, F2, F3) 61a, 6l corresponding to the transmission path to which the actual cell is to be output.
b. Manually powered by 61C. Furthermore, a flip-flop o 7 (
F+, F2, F3) 61a, 6lb, 61
The address latched in c is selector (S) 52
, and becomes the write address 25. Common buffer (
Address chain data 5 written to CBF) 51
Reference numeral 8 indicates the stored address of the real cell to be read next for the real cell written to the same address as the real cell and output to the same output transmission path. Note that the flip-flop (F,, T"2, }"3
60a ~ 60c, 61a ~ 61c
, 62a to 62c are constructed from a plurality of flip-flops that can latch one address.

A common buffer (CBF) 51 writes real cells and address chain data 58 using a write address 25, reads them using a read address 26, sends the read real cells to a cell multiplexing/demultiplexing circuit (DEMUX) 22, and sends the address chain data 59 is sent to the selector (S) 55.

Flip 707 (F+, F2, F3) 60a
, 61a, 62a are flip-flops (F., F.
2, F3) 60b, 6lb, 62b are flip-flops corresponding to the output transmission line 3d (3f),
Flip-flop (F+, F2, F3) 60c
, 61c, and 62c are flip-flops corresponding to delay circuits. A common buffer (CBF) 5 functions as a real cell delay circuit and its address chain.
1 is doing it.

Selectors (S) 55 and 56 are controlled by a control signal 66, and normally flip-flops (F+, F2) 6
2a and 62b are repeatedly selected in this order. The timing at which the flip-flops (F+, F2) 62a, 62b are selected is determined by the output transmission lines 3c (3e), respectively.
3d (3f) compatible. However, when reading a delayed real cell from the common buffer (CBF) 51, a flip-flop (F,, F2 > 62
a, 52b instead of selecting a flip-flop (F
3) Select 62C. Selected flip-flop (
F+, F2, F3) 62a, 62b, 62C
The address from 1. passes through the selector (S) 56 and becomes the read address 26, and is also written as an empty address in the empty address register 1. ! The information is stored in the section 36d. Address chain data 59 read by the subsequent address 26
is the selected flip-flop (F, , F2
, F3) 62a, 62b, 62c.

Address comparison circuit (c+, C2, C3) 63a
~63c is usually a flip-flop (F., F2,
F3) The addresses latched in 61a to 61c and 62a to 62c are compared, and if they match, an address match signal 64 or 65 is output. In this case, if the addresses match, this indicates that there is no real cell or delayed real cell stored in the common buffer (CBF) 51 that should be output to the corresponding transmission path. There is. In addition, the address comparison circuit (C+,
C2 > 63a, 63b is the control circuit (CT) 57
The flip-flop (F+
, F2) 61a, 6lb, compare the set address with the address latched in the flip-flops (F,, F2) 62a, 62b, and if they match, then An address match signal 64 is sent out. In this case, the time point when the addresses match indicates the time point when the cell stored at the set address of the common buffer (CBF) 51 is read out.

The feature of the present invention is that in FIG. 5, the transmitting side device 1 has a flip-flop 07 (F
3) 60C, 61c and 62C, and a header conversion circuit (HC) 47 as a first line switching control means.
, selectors (S) 52 to 56, comparison circuits (C1, C2,
C3) 63a to 63C and ij control circuit (CT)
67, and the receiving side device 2 includes a cell multiplexing circuit (MUX>40) as a real cell multiplexing means.

Next, the switching operation of the fifth embodiment will be explained.

In the fifth embodiment, line switching can be performed without momentary interruption. Below, a procedure for switching and switching back the line from the working line passing through the working transmission lines 3a-3c-3e to the protection line passing through the working transmission lines 3a-36-3e will be explained.

First, when the control circuit (CT) 67 of the receiving device 2 receives a line switching signal from a center neck (not shown), it sends out a header conversion table rewriting signal 34 to switch from the protection line in the working transmission line 3d. A VPJ for identifying the protection line is added to the header conversion table in the header conversion circuit (HC) 47 so that the incoming real cells are sent to the output transmission path 3e.
and flip-flops (F+) 60a and 61. Write the number corresponding to a and the new VPI used by that protection line within the transmission path 3e. This new VPI is the VPI to which the VPI identifying the working line in the working transmission line 3C is converted.
It is the same as PI. Thereby, the receiving side device 2 becomes a circuit that multiplexes the working line and the protection line into one line.

Next, in the line switching section, if the transmission delay of the protection line is larger than that of the working line, the control circuit (CT) 67 of the transmitting side device 1 controls the operation of the working line that is being sent to the working transmission line 3C. A header conversion table rewriting signal 34 is sent so that the cell is sent to the protection line passing through the working transmission line 3d.
Send out. Upon receiving the header conversion table rewrite signal 34, the header conversion circuit (HC) 47 converts the header conversion table so that the actual cells sent from the working line in the working transmission line 3a are sent to the output transmission line 3d. Change the output transmission line number corresponding to the VPI that identifies the working line on the input side to the number corresponding to the output transmission line 3d, and set a new VPI for that line to be used within the working transmission line 3d as a protection line. Write. A new VPI different from that of the working line in the working transmission line 3C is used for cells on the protection line passing through the working transmission line 3d. The above completes the line switching in this case.

On the other hand, in the line switching section, if the transmission delay of the protection line is smaller than that of the working line, the control circuit (CT) 67 of the transmitting side device 1 first sends the header conversion table rewriting signal 3.
4 is sent to the header conversion table of the header conversion circuit (HC) 47 so that the actual cells sent from the working line in the working transmission line 3a are stored in the delay circuit in the common buffer (CBF) 51. , the numbers corresponding to the flip-flops (F3) 60C and 61c as delay circuits and the new VPI whose lines are used as protection lines within the working transmission line 3d are written. The control circuit (CT) 67 sends a set signal 64 to the address comparison circuit (C+) 63a immediately after sending the header conversion table rewrite signal 34.

Thereafter, after receiving the address match signal 64 from the address comparison circuit (C+) 63a, the control circuit (CT) 67 receives the address match signal 64 from the address comparison circuit (C+) 63a, and after a period of time equal to or greater than the transmission delay difference between the working and protection lines in the line switching section has elapsed. , the selection of the flip-flop (F2) 62b is temporarily stopped in the selectors (S) 55 and 56 by the control signal 66,
The change is made so that the flip-flop (F3) 62C is selected instead. After that, the control circuit (CT) 67
Immediately after receiving the address match signal 65 from the address comparison circuit (C+) 63c, cells of the working line sent from the working transmission line 3a are directly sent to the common buffer (CBF) 51.
The header conversion table rewriting signal 34 is sent out so as to be written in the area corresponding to the output transmission path 3d. The header conversion circuit (HC) 47 receives this header conversion table rewrite signal 3.
Immediately after receiving 4, the output transmission line number corresponding to the VPI that identifies the working line on the input side of the header conversion table is transferred to transmission line 3.
Change to the value corresponding to d.

Further, the control circuit (CT) 67 stops the selection of the flip-flop (}'3) 62c in the selectors (S) 55 and 56 by the control signal 66 at the same time as sending out the header conversion table rewrite signal 34, The change is made so that flip-flop (F2) 62b is selected instead. This completes the line switching in this case.

Note that switching back the line can also be performed in the same manner as the above-mentioned switching.

In the above explanation, the flip-flop (F3) 62c and the flip-flop 7" (F2) 6 related to the delay circuit are
We have described the case of priority control in which selection is given complete priority to flip-flop (F3) 6b at a constant selection ratio until there are no cells on the protection line in the delay circuit.
2C and (F2) 62b may also be selected.

In addition, in the line switching method explained above, the control circuit (CT
) 67 is an address comparison circuit (C3) related to the delay circuit.
) The protection line is It is assumed that no cells are newly written to the common buffer (CBF) 51.

However, when the speed of the high-speed internal highway is high and the occupation time of one cell becomes short, cells on the protection line are transferred to the common buffer (CBF) before rewriting the header conversion table.
51.

In that case, even after the header conversion table of the header conversion circuit (HC) 47 is rewritten, the control circuit (CT) 67 continues to control the flip-flop (F2) 62t] using the control signal 66. A timer that prioritizes the flip-flop (Fs) 62c, cancels the priority control when there are no cells on the protection line in the delay circuit, and selects an address for outputting the cells to the transmission line 3d. (In the case of flip-flop (F2) 6
Make sure to select only 2b.

Since the control is performed as described above, there is no need for an actual cell arrival interval detection circuit to prevent the order of cells from being reversed.

In addition, since the address chain for configuring the delay circuit only needs to store addresses, compared to the conventional method, -C
Requires less memory capacity.

The line switching systems in the first, second, and fifth embodiments described above can be similarly applied to the case where there is a relay node device between the sending device 1 and the receiving device 2.

FIG. 6 is a block diagram showing a sixth embodiment of the present invention.

In FIG. 6, each circuit is the same as that used in FIGS. 3 and 5.

Serenota (S) 55 and 56 normally control the control signal 6.
6, flip-flops (F+) 62a and 62
b only to output transmission lines 3c (3e) and 3d, respectively.
Select at the timing corresponding to (3f). In this case, the backup transmission line 3h (3i) has a demultiplexing circuit (D
Empty cells are continuously sent from the EMUX) 22. However, when reading cells to be output to the backup transmission line that is IFed to the common buffer (CBF) 51,
The selectors (S) 55 and 56 also select the flip-flop (F3) 62c at appropriate timings according to the control signal 66.

The features of the present invention in FIG. 6 are the same as those in FIG. 5, and a control circuit (CT) 67 is configured to control transmission line switching.

Next, the switching operation of the sixth embodiment will be explained.

In the sixth embodiment, transmission line switching can be performed without momentary interruption. Here, a procedure for switching from the working transmission line 3C to the protection transmission line 3h and switching back will be explained.

First, when the control circuit (CT) 67 of the receiving side device 20 receives a transmission line switching signal from a center device (not shown), it sends out a header conversion table rewrite signal 34 and converts the header conversion circuit (
HC) 47 is changed in the same way as in the case of FIG.

Next, the control circuit (CT) 67 of the transmitting side device 1 controls all of the signals sent to the working transmission line 3C if the transmission delay of the protection transmission line is larger than that of the working transmission line in the transmission line switching section. A header conversion table rewriting signal 34 is sent out so that the line is sent out to the protection transmission line 3h. Upon receiving the header conversion table rewriting signal 34, the header conversion circuit (HC) 47 outputs all the lines that have been output to the working transmission line 3C to the protection transmission line 3t+.
A common buffer (C
BF) 51 from the address chain area corresponding to the output transmission line 3C to the output transmission line 3 as a backup transmission line.
[To change to the address chain area corresponding to 1,
For all VPIs that identify those lines in the header conversion table, the number corresponding to the flip-flops (F3) 60c and 61C involved in the delay circuit and the line of that VPI are set to the backup transmission line 3h. Write a new VPM to be used within. Another new VPI is used for the line passing through the protection transmission line 3h to distinguish it from the line passing through the working transmission line 3C.

At the same time as sending out the header conversion table rewriting signal 34, the control circuit (CT) 67 sends the address comparison circuit (C3)
A set signal 64 is sent to 63a. Thereafter, the control circuit (CT) 67 controls the address comparison circuit (C+) 63.
After receiving the address match signal 64 from a, selector (S)
At 55 and 56, the flip-flop (F2'
) 62b and (F3) 62c are selected at timings corresponding to the output transmission line 3d and the backup transmission line 3h, respectively. With the above steps, transmission line switching in this case is completed.

On the other hand, the control circuit (CT) 67 of the transmitting side device 1 controls the control circuit (CT) when the transmission delay of the protection transmission line is smaller than that of the working transmission line in the transmission line switching section, compared to the case where the transmission delay is large. After the CT) 67 receives the address match signal 64 from the address comparison circuit 63a corresponding to the output transmission line 3C, from that point on, a time longer than the transmission delay difference between the working and backup transmission lines in the transmission line switching section The only difference is that the control signal 66 is changed after the elapsed time, and the other operations are the same.

The switching back of the transmission line can be carried out in the same manner as the above-described switching procedure by simply using the address chain corresponding to the output transmission line 3C in the common buffer (CBF) 51 as a delay circuit.

Since the control is performed as described above, there is no need for an actual cell arrival interval detection circuit to prevent the order of cells from being reversed.

Furthermore, since the address chain as a delay circuit only needs to store addresses, the memory capacity can be reduced compared to the conventional system.

FIG. 7 is a block diagram showing a seventh embodiment of the present invention.

In FIG. 7, 68, 69, 70, 71 and 72 are selectors (S), 73 is a selector (S) 71 and 7
The other control signals are the same as those shown in FIG.

The operations of selectors (S) 6g, 69 and 70 are similar to those of selectors (S) 52, 53 and 54 in FIG.

Selectors (S) 71 and 72 normally control the control signal 7
3, the flip-flops (F+) 62a and (F
2) Select 62b at timings corresponding to output transmission lines 3c (3e) and 3d (3f), respectively.

In this case, empty cells are continuously sent from the multiplexing/demultiplexing circuit (DEMUX) 22 to the backup transmission line 3h (3i). However, when reading cells stored in the common buffer (CBF) 51 to be output to the backup transmission path, the selectors (S) 7l and 72 use the control signal 73
From, flip-flop (F,)62a, { (F2)
62b} as backup transmission line 3h (3i), flip-flop (F2) 62b ((F.) 62a)
is selected at the timing corresponding to the output transmission path 3c (3e) or 3d (3f).

The feature of the present invention is that in FIG.
) 47, selectors (S) 68 to 71, comparison circuit (C1,
C2) 63a, 63b and control circuit (CT
) 67, and the receiving device 2 includes a cell multiplexing circuit (MUX) 40 as a real cell multiplexing means.

Next, the switching operation of the seventh embodiment will be explained.

The seventh embodiment can be used for switching transmission lines without momentary interruption. Below, from the working transmission line 3c to the backup {transmission line 3
The procedure for switching the transmission path to h and switching back will be explained.

First, the receiving device 2 performs the same control as in the case of FIG.

Next, the control circuit (CT) 67 of the transmitting side device 1 controls all of the signals sent to the working transmission line 3C if the transmission delay of the protection transmission line is larger than that of the working transmission line in the transmission line switching section. A header conversion table rewriting signal 34 is sent out so that the line is sent out to the protection transmission line 3h. Upon receiving the Hesoda conversion table rewrite signal 34, the header conversion circuit (HC) 47 performs the next transmission for each VPI that identifies the human line in the header conversion table for all the lines that have been output to the current transmission line 3C. VPI used in the road section
Only the VP construction will be changed to a new VP construction used within the backup transmission line 3h. The line passing through the backup transmission line 3h is connected to the working transmission line 3.
Another new VPI is used to distinguish it from the line passing through C.

The control circuit (CT) 67 simultaneously sends out the header conversion table rewriting signal 34, and simultaneously sends out the address comparison circuit (C.) 6.
A set signal 64 is sent to 3a. After that, the control circuit (
After receiving the address match signal 64 from the address comparison circuit (C.) 63a, the CT) 67 selects the selector (S) 71.
and at 72, flip-flop (F2) 62b
The control signal 73 is changed so that (F, ) 62a are selected at timings corresponding to the output transmission line 3d and the backup transmission line 3h, respectively. With the above steps, transmission line switching in this case is completed.

On the other hand, the control circuit (CT) 67 of the transmitting side device 1 controls the control circuit (CT) when the transmission delay of the protection transmission line is smaller than that of the working transmission line in the transmission line switching section, compared to the case where the transmission delay is large. Immediately after the CT) 67 receives the address match signal 64 from the address comparison circuit 63a corresponding to the output transmission line 3C, from that point onward, for a period of time longer than the transmission delay difference between the working and backup transmission lines in the transmission line switching section. , the control signal 73 causes the selectors (S) 71 and 72 to stop selecting only the flip-flop (F+) 62a, and then switches the flip-flops (F2) 62b and (F1) 62a to the output transmission path 3d and the backup, respectively. In order to select at the timing corresponding to transmission line 3h,
The only difference is that the control signal 73 is changed, and the other operations are the same.

Note that the transmission path can also be switched back using the selectors (S) 71 and 7.
By changing the control in step 2, it is possible to perform the same switching as described above.

Since the control is performed as described above, there is no need for an actual cell arrival interval detection circuit to prevent the order of cells from being reversed.

Furthermore, since the address chain as a delay circuit only needs to store addresses, the memory capacity can be reduced compared to the conventional system.

〔Effect of the invention〕

In the present invention, in a common buffer type switch having an output port address register 1, α section for storing write addresses of cells to a common panofer for each output port and queuing them, a separate address storage section for each output port is provided. , a delay circuit address storage unit is provided which stores the write address of the cell to the common buffer and functions as a delay circuit, and this delay circuit address storage unit allows cells on the current transmission line or line to be delayed by a desired time. by switching to a backup transmission line or line after the transmission line is in use, or by delaying the cells of the working transmission line for a desired time using the output port address storage unit, and then switching to the backup transmission line. , since there is no reversal of the order of cells, there is an effect that the actual cell arrival interval detection circuit that was conventionally required is not required. Also,
This has the effect of shortening the time required to switch lines or transmission paths.

Furthermore, since this delay circuit only stores the address of a cell written to the common buffer, it requires much less memory than a conventional delay circuit that must store the cell itself. It has the effect of requiring less.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a block diagram showing a second embodiment of the present invention. FIG. 3 is a block diagram showing a third embodiment of the present invention. FIG. 4 is a block diagram showing a fourth embodiment of the present invention. FIG. 5 is a block diagram showing a fifth embodiment of the present invention. FIG. 6 is a block diagram showing a sixth embodiment of the present invention. FIG. 7 is a block diagram showing a seventh embodiment of the present invention. FIG. 8 is an explanatory diagram showing an example of an information string formant in the present invention. FIG. 9 is a block diagram showing a conventional example. 1... Sending side device, 2... Receiving side device, 3... Working line (transmission line), 36-3f... Working transmission line, 3g
~3! ...protection transmission line, 4...protection line (transmission line), 5...cross connect switch (XSW),
6... Real cell arrival interval detection circuit (RCDT), 7...
- Real cell arrival interval designation signal or real cell arrival interval detection signal, 8... Real cell separation circuit (RCS), 9... Real cell separation designation signal or real cell separation release signal, 10...
・First-in first-out memory (FIFO)
), 11, 29, 30, 32, 33... Read clock, 12, 28... Empty signal, 13... Header conversion table rewrite signal, 14, 38, 67... Control circuit (CT), 20... Header conversion circuit (HC), 2
1, 5l... Common buffer (CBF), 22... Cell multiplexing/demultiplexing circuit (DEMUX>, 23, 24, 48~
50, 52-56, 68-72...Selector (S),
25...Writing address, 26...Continuing address, 2
7...OR circuit, 31, 35, 42, 57, 66, 7
3... Control signal, 34... Header conversion table rewriting signal or control signal, 36a, 36b... Address storage section for each output port (FIFO), 36c... Address storage section for delay circuit (FIFO), 36d...Free address storage unit (FIFO), 37, 39...Interface circuit (IF), 40...Cell multiplexing circuit (M
UX), 41...Writing block, 43...Up/down counter (C), 44...Down counter
(DC), 45...Set signal or count: direct zero signal, 46...Count value, 47...Header conversion circuit (HC), 58, 59...Address chain data, 60a to 60c, 61a ~61c, 62a
~62C-7 lip 7 o-7 pu (F,, F2, F3)
, 63a to 63c...Address comparison circuit (C+
, C,, C3), 64...set signal or address match signal, 65...address match signal.

Claims (1)

[Scope of Claims] 1. A common buffer that temporarily stores arriving real cells, an address storage section for each output port that stores the address at which the real cell is written to this common buffer, and a memory section for reading from this address storage section for each output port. A line switching system comprising a transmitting side device and a receiving side device, including a vacant address storage unit that stores the issued address as a vacant address, and a switching means for switching a working line to a protection line in units of cells. In the transmitting side device, a delay circuit address storage section that is provided separately from the output port-specific address storage section and stores an address at which an arriving real cell is written into the common buffer and operates as a delay circuit; In the line switching section, if the delay time of the protection line or transmission line is larger than the delay time of the working line or transmission line, switching is performed at any cell break, and if it is smaller, the delay time of the working line or transmission line is switched. By using the delay circuit address storage section, the cells are delayed for a time longer than the transmission delay difference between the working and protection lines or transmission lines in a predetermined line switching section, and then switched to the protection line or transmission line. and a first line switching control means for performing control, the receiving side device multiplexing actual cells into one line among the cells transmitted by the working line or transmission line and the protection line or transmission line. A line switching system characterized in that it includes real cell multiplexing means. 2. A common buffer that temporarily stores arriving real cells, an address storage section for each output port that stores the address at which the real cell was written to this common buffer, and an address storage section for each output port that stores the address read from the address storage section for each output port. In a line switching system comprising a transmitting side device and a receiving side device, the transmitting side device includes a vacant address storage section for storing addresses, and has switching means for switching a working line to a protection line in units of cells, the transmitting side device In a predetermined line switching section, if the delay time of the protection line or transmission line is larger than the delay time of the working line or transmission line, switching is performed at an arbitrary cell break, and if it is smaller, the delay time of the working line or transmission line is switched. After delaying address readout from the corresponding output port storage unit for a time equal to or longer than the transmission delay difference between the working and backup transmission lines in a predetermined line switching section, a second line switching control means for controlling switching to a transmission line; A line switching system characterized in that it includes real multiplexing means for multiplexing on lines.