JPH03216044A - cell exchange device - Google Patents

Abstract

PURPOSE:To decrease a delay in a cell and to save number of buffers by adopting the constitution such that a buffer number of a buffer with a cell written thereon and its address are managed so that the order of cells is not inverted and the cell is outputted by a designated outgoing line in a prescribed order. CONSTITUTION:A buffer control circuit 15 is managed so that a buffer number of a buffer 11 written with a cell in a destination queue 19 and its address are managed in a way that the sequence of cells is not reversed and plural cells outputted to plural outgoing lines 2 are not written in the same buffer 11 simultaneously by a write buffer management memory 21 through the management. Then an incoming line spatial switch 13 is controlled to select the buffer 11 with a cell stored therein and an outgoing spatial switch 14 is controlled to output cells stored in the buffer 11 to an outgoing line 2 designated by a header part in a prescribed order. Thus, the abort due to collision of cells is less with a few buffers and the scale of the switch connecting the buffers, the incoming and outgoing lines is made small.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a cell switching device that exchanges cells containing blocks of various multimedia information such as voice, data, and images at high speed. .

[Conventional technology]

FIG. 4 is a block diagram showing a conventional cell switching device as shown in the specification and drawing K attached to Patent No. 217,226 of 1988, for example. In the figure, 1I to 1n are n incoming lines into which packets are input, and these packets have a fixed length and each has a header section containing coded destination information.

21 to 2m are m outgoing lines through which the packet is output according to the destination specified in its header.

3, ~3t are t buffers in which the input packets are temporarily stored, and 4 is the incoming line 1I~1 n k s where the packet is input, and empty buffers 3, ~3.
This is an empty buffer selection switch connected to t.

51 to 5t are header storage circuits that are prepared corresponding to each of the buffers 3 and 3t and extract and store only the header part of the packets stored in the associated buffers 3 and 3t. It is. Reference numerals 61 to 6t are outgoing line selection circuits that are provided corresponding to each of these header storage circuits 5I to 5t, and make significant only the output sent to the output line corresponding to the stored contents of the corresponding header storage circuits 51 to 5t. .

7, ~7m are prepared corresponding to each of the outgoing lines 2I~2m, and receive the output sent from each of the outgoing line selection circuits 6, ~6t, and assign it to the buffer number of the buffer 3, ~3t. Use the encoder to encode.

8I to 8m are provided corresponding to encoders 7 and 7m, and encoded buffer numbers are written in each encoder T and 7m, and are read out in the order in which they are input. ) type of FIFO memory. 9I to 9m are prepared for each outgoing line 2l to 2m, and are controlled by the buffer code output from the corresponding FIFO memory 8, to 8m, and read the packets stored in the buffers 31 to 3t in their header sections. This is a buffer connection switch that outputs to the designated outgoing lines 2 and 2m.

Note that here, a packet is used instead of a cell as the unit of information to be transmitted, but the multimedia information is divided into blocks and a header section containing destination information is added to each block. In this case, both cells and packets represent the same thing.

However, the difference is that packets are generally treated as having a variable length in one block, whereas cells are treated as having a fixed length defined by international standards.

Next, the operation will be explained. Here, what about Figure 5? This is a time chart showing the timing of signals of each part, and shows the flow of control when packets addressed to outgoing line 2m are simultaneously received from incoming lines 1 and 1n when buffers 3I and 3t are empty. Furthermore, the packets handled here have a fixed length as described above, and the header section thereof includes an outgoing line number coded as destination information.

When a packet arrives at the incoming lines 1I to 1n, the free buffer selection switch 4 selects the free buffer 1 from the buffers 3 and 3t.
Select one of the incoming lines 11 to 1n where the packet arrived.
Connect with. Here, as shown in Figure 5 0) and (entrance), packets whose destination is designated as the outgoing line number "1" of the same outgoing line 2I in the header section arrive from incoming lines 1 and 1n at the same time. In this case, the free buffer selection switch 4
For example, the people Im1I to 1n are selected in descending order of number, and the vacant buffers 3 and 3t are also selected in descending order of number, and these are connected. Therefore, in this case, depending on the empty buffer selection switch 4, the incoming line 1 goes to the buffer 3, and the incoming line 1n goes to the buffer 3.
tK each connected, input line 1■K arrived bucket}A
The packet B that arrived at the incoming line 1n is stored in the buffer buffer 7 server 3, and the packet B that arrived at the incoming line 1n is stored in the buffer 3t.

By switching the free buffer selection switch 4, the bucket }A is also supplied to the header storage circuit 5I corresponding to the buffer 3m, and the bucket }B is also supplied to the header storage circuit 5t corresponding to the buffer 3t. Here, the header storage circuits 5I to 5t extract only the header part of each received packet and store the content thereof, which is the outgoing line number. Therefore, the outgoing line number "1" of the outgoing line 2 is stored in the header storage circuits 5 and 5t, respectively. The contents of these header storage circuits 5, -5t are sent to the corresponding outgoing line selection circuits 6, -6t, respectively, and
L makes only the output sent to the output line corresponding to the outgoing line number specified by the contents of the corresponding header storage circuit 5, ~5t significant, that is, the output sent to other output lines is insignificant. That is, it is set to "0".

Therefore, the output line selection circuit 6I sets the output to the encoder 7 to "1" as shown in FIG.
For t, the output to the encoder TI is set to "1" as shown in FIG. 5(d). Here, encoder 7, ~7 m #:
l. The output of any one of the output line selection circuits 6, to 6t is “1”
'', the corresponding outgoing line selection circuit 6, ~6t encodes the buffer number of the associated buffer 3I~3t, and stores it in the FIFO memory 8, ~6t associated with itself.
Store at 8m. As shown in Figure 5 e9 and (d), 2
The outputs of the two output line selection circuits 6 and 6t are “1” at the same time.
If so, the encoder T stores the buffer codes in the FIFO memory 8, for example in ascending order of i.

Therefore, the buffer number ■ of the buffer 3l is stored in the FIFO memory 8t first, and then the buffer number ■ of the buffer 3l is stored in the FIFO memory 8t.
The buffer number of t is stored. Buffer connection switches 91 to 9m are associated with FIFO memories 8, to 8.
The buffer numbers stored therein are read from m in the order in which they were stored, and the buffers 3I to 3t to which the buffer numbers 1 to 3 are assigned are connected to the outgoing lines 21 to 2m associated with the buffers 3I to 3t.

That is, as shown in FIG. 5(e), the buffer connection switch 9I first reads out the buffer number 3 from the FIFO memory 8, and after the connection process is completed, reads out the next packet number. When the buffer number ■ is read out, first the pad 7a3. t-to the outgoing line 2, and transfers the packet A accumulated in the buffer 3 to the outgoing line 2, as shown in FIG.
Output to. When the sending of the packet A to the output 1112t is completed, the packet number is read out as described above, and the buffer 3t is connected to the output curb in the same manner as shown in FIG.
Packet B stored in the buffer 3t is output to the outgoing line 2, as shown in (g).

Therefore, as for the output lines 2 and K, buckets A and B are outputted continuously as shown in FIG. 5(A).

Buffer connection switches 9 and 9m send packets to output line 2.
, ~2m, the corresponding buffer 3, ~3t
, and informs the free buffer selection switch 4 of this in preparation for reception of subsequent packets.

[Problem to be solved by the invention]

Since the conventional cell switching device is configured as described above, when reading cells (packets) from the buffers 3, to 3t, only one buffer 3 is used to avoid collision with other cells.
,~3t can store only one cell, and if the number of omitted cells exceeds the number of pads 31~3t, that cell will be discarded; In order to reduce the rate, it is necessary to prepare a large number of buffers 3I to 3t, and as a result, it is necessary to prepare a large number of buffers 3I to 3t, and as a result, it is necessary to prepare a large number of buffers 31 to 3L for connecting the incoming lines 1 and 1n and the outgoing lines 2 and 2m. , the scale of the buffer selection switch 4 and the buffer connection switches 9, .about.9m becomes large.

This invention was made to solve the above-mentioned problems, and even if the number of buffers is reduced, cells are less likely to be discarded due to collision, and the buffers are connected to incoming and outgoing lines. An object of the present invention is to obtain a cell switching device that can reduce the scale of the switch.

[Means to solve the problem]

The cell switching device according to the invention K is provided with a header processing circuit corresponding to an incoming line to detect the header part of an input cell and its destination, and stores cells by specifying an address, and also stores cells by specifying an address. Prepare multiple buffers that can read accumulated cells regardless of the order of
This buffer and header processing circuit is connected to the incoming space switch.
In addition, the buffer and the outgoing line are connected by an outgoing line clearance switch, and the buffer number and address of the buffer to which the cell is written in the queue for each destination are set so that the order of the cell is not reversed.
A write buffer management memory that records the state of queues for each destination as a table of buffer numbers manages the memory so that multiple cells output to multiple outgoing lines at the same time are not written to the same pad. , a buffer control circuit is provided for outputting cells to outgoing lines designated in a predetermined order K.

[Effect]

The cell switching device according to the present invention detects the destination of a cell inputted from an incoming line, stores it in a buffer selected by an incoming line space switch, and stores the cell into a buffer selected by the incoming line space switch, and stores the cell into a buffer selected by the incoming line space switch. and their addresses so that the order of the cells is not reversed, and the state of the queue for each destination is displayed as a table of buffer numbers, so that multiple cells that are output to multiple outgoing lines at the same time are not written to the same buffer. By managing cells in a predetermined order and outputting cells to designated outgoing lines, fewer buffers can reduce business closures due to cell collisions, and reduce the scale of switches that connect buffers with incoming and outgoing lines. To realize a cell switching device that is capable of

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 indicates a plurality of incoming lines (four in this example) to which an incoming line number I6sI1+... is assigned and a cell consisting of a header section including an outgoing line number as destination information and a data section is input, 2 is the outgoing line code 0. , Ol. . . , are attached to a plurality of outgoing lines (four lines in this example) to which cells are output according to the destination specified by their header part K.

A header processing circuit 10 is provided corresponding to each person's line 1, and detects the output line 2 of the destination from the header part of the input cell from the corresponding incoming line 1.

In addition, 11 are buffer numbers $0, #1, .
... is given, the cells are stored at a specified address, and by specifying that address, the stored cells can be read out regardless of the order in which they are written (this implementation Conventional buffers 3 to 3 shown in FIG.
It is different from t.

Reference numeral 12 denotes a storage control circuit which is provided corresponding to each of the K buffers 11, manages free addresses using, for example, a FIFO type memory, and provides read addresses and write addresses to the associated buffers 11.

13, each header processing circuit 10 is connected to a predetermined buffer 11;
An incoming space switch 14 selectively connects each buffer 11 to a predetermined output #2. The switching of the 15-digit incoming line space switch 13 is controlled to select the buffer 11 in which cells are stored, and the switching of the outgoing line space switch 14 is controlled to specify cells stored in the buffer 11K in the header section. This is a passer control circuit that outputs 2K output lines in a predetermined order.

In addition, within this buffer control circuit 15, 16 receives the outgoing line number 00-0 of the cell detected at the time of cell arrival by the header processing circuit 10 associated with the individual line 1, and processes the cell. This is a control device that selects the buffer 11 to be stored. 1T is a write buffer selection circuit that controls switching of the line space switch 13 in order to connect the buffer 11 selected by the control device 16 to the corresponding header processing circuit 10. 18 is the outgoing line number 0 sent from this buffer selection circuit 17.

~0, and divide the arriving cells by destination, and write the write address on the buffer 11 where the cell was written,
This is an address exchange circuit that obtains the address from the storage control circuit 12 corresponding to the buffer 11 and writes it to a queue for each destination, which will be described later.

Reference numeral 19 denotes a queue for each destination, which is constituted by a FIFO type memory and is provided corresponding to each K of the outgoing lines 2. In this destination-specific queue 19, for each outgoing line 2 to which it is associated, the write address on the buffer 11 in which cells destined for that outgoing line 2 are stored is retrieved by the address exchange circuit 18. , cells are written in the order in which they arrive. Reference numeral 20 refers to this queue 19 for each destination, determines a cell to be inserted from the buffer 11, uses the address read from the queue 19 for each destination as a read address, and uses the memory control circuit associated with the corresponding buffer 11. 12 and also controls switching of the outgoing line space switch 14 to connect the buffer 11 to the corresponding outgoing line 2.

21 is connected to the control device 16, and the status of the destination queue 19 is controlled by buffer numbers #1 to ## so that multiple cells output to multiple outgoing lines 2 at the same time are not written into the same buffer 11K. This is a write buffer management memory for managing data in a table as shown in Table 5.

Next K operation K will be explained. In a certain time slot, 1
When one or more cells are input to incoming line 1, the header processing circuit 10 where the cells arrived will write the outgoing line number 0 of the cell's destination from the header section. ~0, is taken as the destination information, and the incoming line number is entered. ˜I, sequentially sends destination information of each cell to the control device 16. Controller 16 determines the buffer number into which each cell is written. At this time, the buffer number selection is
It is desirable that all the buffers 11 contain as many K cells as uniformly as possible, but when reading cells later, if the same buffer 11 contains multiple cells addressed to each output line 2 to be read in the same time slot, some Since only one cell can be read out, the control device 16 needs to select the buffer 11 to avoid this. To perform this control, write pad 7a management memory 2
1 is associated with the control device 16. The write buffer management memory 21 manages the buffer numbers into which the cells are written, arranging them in the order in which the cells arrive for each outgoing line 2 of the destination. That is, as shown in FIG. 2, the outgoing line numbers 00 to 0 are displayed vertically and the time slot numbers t. t+1. Create a table that excludes t+2 and t+3, write the cell in it, and write it into the buffer 1.
10 buffer numbers are stored. As the time slot passes, the cells are constantly inputting and outputting, so it is necessary to rewrite the contents of the table, but by providing a pointer that indicates the next time slot number to be output, it is possible to input 1kvI into each cell. The backup numbers of the packs 7a 11 can be identified by destination and in the order of arrival, and the inside of the memory can be reused cyclically.

For example, if the table of the write mark 7a management memory 21 is
When the situation is as shown in the diagram, the person with entering incense number I0 is ls1.
Assume that one cell addressed to outgoing line 2 with outgoing line number 01 is input. However, in the figure, a to 1 indicate the sky. The control device 16 selects the write buffer 11 by referring to the table in the write buffer management memory 21 . This cell addressed to 0 is placed at the end of the line corresponding to the outgoing line number OS. Since buffer number #1 exists at time slot t+1, it enters the column to be read at time slot t+2, and the write buffer number for this cell will be in the column h in the table. Next, in order to determine the cross symbol, the control device 16 reads the buffer number in the column of the same time slot as h} t+2, obtains buffer numbers #5 and #4,
Select from among the other buffers #0 to #3. The buffer numbers can be determined in numerical order as mentioned above.
The buffer number to which the cell was last written is O, and the buffer number #0 in the destination queue 19 is selected, so the next buffer number #1t- is selected. Once the buffer number is determined, it is written to the buffer management memory 2.
Write in position h of 1.

On the other hand, when a plurality of cells are input to the input line 1, it is necessary to select a plurality of write buffers 11. At this time, since it is not possible to write two or more cells to the same buffer 11 due to the structure of the fc{Ij several cells that arrive in the same time slot, the backup numbers are selected so that they are different from each other, that is, exclusively. I have to go. Therefore, the incoming line number engineer. After determining the writing cross 77 number of the cell input to input line 1, write I,,I in the order of input line number.
, ,■, are determined exclusively. However, Batsufa 1
Cells that cannot select 1 are discarded. Furthermore, if the destinations of the input cells are biased and a large number of cells are stored in the buffer 11 and the buffer 11 becomes full, newly arrived cells are discarded.

When the write buffer 11 is determined, the write buffer selection circuit 11 instructs the incoming line space switch 13 to connect the header processing circuit 10 corresponding to the incoming line 1 to which the cell is input and the buffer 11 to which the cell is written. The address of the buffer 11 is specified by the write address of the storage control circuit 12 provided corresponding to each buffer 11,
The address is written to the back of the destination queue corresponding to the destination output line 2 through the address exchange circuit 1B,
Prevents cell order reversal. Read buffer selection circuit 20
reads the address at the head of the destination queue 19 corresponding to all outgoing lines 2, and sends it to the corresponding storage control circuit 12.
The output line space switch 14 is instructed to connect the buffer 11 to which the address in which the cell to be read is written is specified and the predetermined output line 2. Outgoing line space switch 14
In response to this instruction, connects the buffer 11 and the outgoing line 2, and the buffer 11 outputs the cell to the outgoing line 2. The free addresses of the buffer 11 are managed by the storage control circuit 12, but here the read buffer selection circuit 2
The read address sent from 0 is stored in the FIFO as a free address, and when another cell is input from input line 1 and stored in the buffer 11, the address at the beginning of this FIFO is used as the next write address. , to the buffer 11 and the address exchange circuit 18, the addresses in the buffer 11 are used cyclically and efficiently.

FIG. 3 is an explanatory diagram showing the states of randomly input cells on the incoming line 1, buffer 11, destination queue 19, and outgoing line 2 for each time slot. Here, the input line number is I,, I,, ■. Each input line 1 is A
, B, C, and D, and the cell names are expressed using destination ● input line ● input time slot. For example, a cell arriving at incoming iA(xo) whose destination is outgoing line 2 with outgoing line number O in time slot 1 will be expressed as 3A. The row (a) in the figure indicates the arrival of the cell on the input line A-
D (I.-Ia) are shown separately. The name of the cell is written in the column where the cell has arrived, and conversely, a blank field indicates a slot where no cell has arrived. The row (b) in the figure shows the state of existence of cells for each buffer of buffer numbers #0 to #5 and for each address within the buffer 11. In the example shown in the figure, the number of buffers 11 is 6, and the number of cells stored in one buffer 11 is t.
-3, that is, one buffer 11K has three addresses. For example, there are three addresses #Ol to #03 in the buffer 11 of buffer code #0, but in address #02, incoming line D (I,)K arrived at time slot 2 between time slots 3 and 50. Cell I addressed to OI
It can be seen that D, is stored. The line (c) in the figure shows the transition of the queue 19 for each destination. Ultimately, the speed at which cells go out to each outgoing line 2 with outgoing line numbers 00 to 0 is constant, but the rate at which cells arrive at incoming line 1 and the destination vary in time. In order to absorb this, it is necessary to hold cells in the buffer 11 for a certain time slot. At this time, in order to manage buffer numbers and addresses in the buffer 11, the queue 19 for each destination creates a queue of addresses in the buffer 11 for each destination so that cells that arrive first are output first. The address written at the top of the diagram is at the front of the matrix, and the address at the bottom is at the end. For example, in time slot 8, there are currently 3 cells destined for the mountain in the buffer, and the reading order is #11, #2.
1, #41. In addition, the destination queue 19 manages both the buffer number and the address in the buffer, and only refers to the head of the queue, but the write buffer management memory 21 manages only the buffer number and refers not only to the head but also to the memory. You can freely refer to the contents. In the figure, (d) shows cells output from each outgoing line 2K of %OO to 0 for each time slot.

According to this invention, the number of cells that can be written into one buffer 11 in one time slot is 1 due to its structure, so when a plurality of cells arrive in a certain time slot, the buffers 11 to which the cells are written are different from each other and there are 9 different buffers 11. must be selected.

Furthermore, when reading, the number of cells that can be read from one buffer 11 in the same time slot is one, so they must be different from each other. For that purpose, select the candidate buffers 11 according to their patch numbers #0, #1, #2.
, #3, #4, #5, #O, #1... Mutsu is listed cyclically, applied to each arriving cell individually, and determined after confirming that both conditions are met when writing and reading. I will take steps.

For example, the last input cell OC in time slot 10
,. is stored in buffer 11 of #1 in time slot 11. 4 inputted to incoming line 1 at time slot 11
Among the cells, the buffer 11 of #2 next to #1 is selected as a candidate for the cell 3A, . Cell 3A,, is addressed to Os, but currently there are three cells addressed to 0, buffer 11
Since it exists in the time slot 1 when it is read out,
It is 5.

If the #2 buffer 11 stores cells 3A, 1 in the read time slot 15, the #2 buffer 11 stores cells 3A, 1
However, since nothing is currently stored in the #2 buffer 11 in time slot 11, there is no problem. Similarly, incoming line 1 at time slot 11
Cells 3B, +, and OC+t input to #3 and #3, respectively,
Enter #4 buffer 11. However, cell 2D++ is #
5 enters buffer 11, cell 3A, which is in the queue destined for outgoing line 2 of 0,. Since one of the cells will wait in the same buffer as , cell 2 DI, is #
0 buffer 11. In the next time slot 12, buffer 11 selects buffer number #1. The above is about the selection of buffer 11.
Regarding how to use the addresses within 1, the storage control circuit 12 uses the three addresses as uniformly as possible. Further, if the buffer 11 is full of cells, the cells are discarded. On the other hand, destination queue 1
9 is a memory (FI) that can read the previous K written first.
FO) Yes, put the number of write buffer 11 at the back of the queue. When reading a cell, the read buffer selection circuit 20 first reads the buffer number and address from the destination queue 19, and then the outgoing line space switch 14 selects the outgoing line from the buffer 11 according to instructions from the read buffer selecting circuit 20. 2 is connected, and the buffer 11 outputs the cell to its output line 2.

In addition, the following methods are available to reduce the rate of cell abandonment.

Cells that are to be discarded in a certain time slot are
Therefore, it is not discarded and is output in the next time slot of the time slot that was originally supposed to be output. For example, the K1 control device 16 selects the buffer 11tl- for the cell to be discarded at i in FIG. 2 so as to be placed in the next g. At this time, an empty signal is entered in the destination queue 19 corresponding to i in the table of the write buffer management memory 21, and in this time slot, the outgoing line number 0. No cell is output from output line 2 of .

Note that in the above embodiment, the destination queue 19 is a FIFO, but if the order of writing is known by using a read pointer and a write pointer to create an address queue, the FIFO can be used as a RAM. You can change it to

Furthermore, in the above embodiment, when writing cells to the buffers 11, the buffers 11 are selected in numerical order, but in order to reduce the number of discarded cells, the buffers with the most free addresses may be selected. good. Furthermore, it is possible to provide a broadcast function by setting a control circuit that outputs K1 cells to two or more outgoing lines.Furthermore, it is possible to provide a broadcasting function by setting a control circuit that outputs K1 cells to two or more outgoing lines. If provided, priority can be given to cell output.

Further, in the above embodiment, I. When cells arrive at incoming line 1, they are always processed in the order of incoming line number. % I l , I
When selecting z, I n and buffer 11, cell discard is more likely to occur when the incoming line 1 of incoming line number I0 is more likely to be discarded than the incoming line 1 of incoming line number I0, so change the selection order one after another and discard the cells. We will also discuss ways to change the entry line that is likely to occur.

For example, in one timeslot there are workers I,, I, I, I, I, I, and I in the next timeslot. , Ii, then I,, Ii. , I1, ●●● are selected in the order of buffer 11.

Further, in the above embodiment, the number of incoming meters, the number of outgoing lines is 4, the number of buffers is 6, and the buffer size is 3, but the cell switching device is not limited to these. In this case, the cell discard rate is reduced by making the speed between stages higher than the incoming line speed, and serial/parallel conversion circuits are installed before and after this cell switching device.
A parallel/serial conversion circuit may be added to slow down the switching speed, and in either case, the same effect as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, the destination of an input cell is detected, stored in the buffer selected by the incoming space switch, and the buffer control circuit K determines the buffer number of the buffer into which the cell is written. It manages the cells and their addresses so that the order of the cells is not reversed, and also manages the cells so that multiple cells output to multiple output lines at the same time are not written to the same buffer, and outputs the cells in a predetermined order to the specified output. Since the cell is configured to be output to the line, cell delay is small, outgoing line throughput is improved, and a cell switching device can be obtained in which the number of passers can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a cell switching device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of the contents of the write buffer management memory, and FIG. 3 shows each part of the embodiment shown in FIG. 1. FIG. 4 is a timing diagram showing the signal format of the conventional cell switching device. FIG.
The figure is a time chart showing the timing of signals in each part. 1 is an incoming line, 2 is an outgoing line, 10 is a Fi header processing circuit, 11 is a buffer, 13 is an incoming line space switch, 14 is an outgoing line space switch, 15 is a buffer control circuit, 19 is a queue for each destination, 21 is a write buffer management memory . In addition, the same symbols in the figures indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation (2 others) Figure 2 Figure 5 (thousand) ,to

Claims (1)

[Claims] A plurality of incoming lines into which a cell consisting of a header part and a data part is input, a plurality of outgoing lines to which the cell is outputted according to the destination specified in the header part, and an individual line for each incoming line. A header processing circuit is provided, which detects the outgoing line of the destination from the header part of the cell input from the incoming line, and the cell is written by specifying an address, and the order of the writing is determined by specifying the address. a plurality of buffers from which the cells can be read out independently of the buffer; and an input line that selectively connects the input line and the buffer by spatially arranging contacts and performing switching in order to write the cell into the buffer. a space switch, an outgoing space switch that spatially connects the buffer and the outgoing line in a predetermined order, and a buffer number and the address of the buffer to which the cell is written for each destination outgoing line, and the order of the cell is not reversed. The queues for each destination are managed as a table of buffer numbers so that multiple cells output to multiple outgoing lines at the same time are not written to the same buffer. A cell exchange device comprising a write buffer management memory and a buffer control circuit for outputting the cells to the outgoing line specified by the header section in a predetermined order.