JPH03216074A - Picture signal processor - Google Patents

Abstract

PURPOSE:To output an accurate narrow pulse width modulation signal by utilizing a delay circuit and an AND circuit to make a minimum pulse width of the pulse width modulation signal stably by a delay time. CONSTITUTION:A pulse width modulation signal Sp1 outputted from a pulse width modulation circuit 23 receiving a picture element synchronizing signal S1 and a picture signal SD is led to one input terminal of an AND circuit 31 as it is. On the other hand, the pulse width modulation signal Sp1 is led to other input terminal of the AND circuit 31 via a delay circuit 29. Thus, a narrow pulse width modulation signal whose pulse width is made narrow by a delay time of the delay circuit is obtained and a picture signal processing unit with high density gradation number relating to a range of the lightness of the picture and wide dynamic range is realized.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is capable of manually generating an image signal and a triangular wave signal and outputting a pulse width modulated signal accurately. The present invention relates to an image signal processing device that is capable of stably narrowing the pulse width of an image signal.

[Prior Art] Generally, in order to accurately reproduce the density of an image, it is necessary to have a high number of density gradations corresponding to the brightness range of the image, that is, to have a wide dynamic range of density.

As a conventional technique for obtaining a wide density dynamic range, there is an image signal processing device 2 shown in FIG. 3 which inputs an image signal and a triangular wave signal and outputs a pulse width modulation signal.

This image signal processing device 2 operates as shown in the waveform shown in FIG. 4, and includes a comparator 6, and further transmits an integral signal B, which is a triangular wave, to the comparator 6 in synchronization with the pixel synchronization signal A.
an integrator 4 which is introduced into one input terminal of the comparator 6, and an image signal generator 8 which outputs an image signal C in synchronization with the pixel synchronization signal A and introduces this image signal C into the other input terminal of the comparator 6. (See Figure 3).

A pulse width modulated signal D is output from the comparator 6 of the image signal processing device 2 configured as described above.

This pulse width modulation signal D is a signal having a pulse width proportional to the level of the image signal C, as understood from FIG.

By the way, in the field where the image signal processing device 2 is used, as described above, a wide dynamic range of density is required.

When using a pulse width modulation method, the dynamic range of concentration is determined by the ratio of the maximum pulse width to the minimum pulse width.

On the other hand, in the field where the image signal processing device 2 is used,
There is a demand for faster signal processing. This is to increase the added value of a device that uses the image signal processing device 2 by speeding up the processing.

After all, in order to widen the dynamic range of concentration and speed up signal processing, it is desirable to make the minimum pulse width as narrow as possible.

In the conventional image signal processing device 2, when trying to narrow the pulse width of the pulse width modulation signal D, the maximum level of the integral signal B is made larger than the maximum level of the image signal C, as shown in FIG. In addition, it is necessary to reduce the difference (overdrive amount) between the maximum level of the integral signal B and the maximum level of the image signal C.

[Problem to be solved by the invention] However, if the overdrive amount is made too small,
There is a risk that the comparator 6 will not operate stably, and there is a problem that the pulse width will become unstable. Furthermore, since there is a limit to the high-speed response of the integrator 4, so-called waveform rounding occurs at the peak of the integrated signal B, as shown in FIG. Ultimately, there is a problem in that the minimum pulse width cannot be made that narrow due to problems with the stability of the comparator 6 and the rounding of the waveform.

The present invention has been made in order to solve the above-mentioned problems, and the present invention uses a delay circuit and an AND circuit to stably narrow the minimum pulse width of a pulse width modulation signal by the delay time. Therefore, an object of the present invention is to provide an image signal processing device that can output an accurate narrow pulse width modulation signal.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a pulse width modulation circuit that compares an image signal and a triangular wave signal and outputs a pulse width modulation signal, and a pulse width modulation circuit that outputs a pulse width modulation signal by comparing an image signal and a triangular wave signal. a delay circuit that delays a signal by a predetermined time; and a pulse width modulation signal output from the pulse width modulation circuit is introduced into one input terminal, and the delayed pulse width modulation signal output from the delay circuit is input to the other input terminal. and an AND circuit into which a signal is introduced and outputs a narrow pulse width modulation signal having a pulse width narrower than the pulse width of the pulse width modulation signal.

In the image signal processing device of the present invention configured as described above, the pulse width modulation signal output from the pulse width modulation circuit is directly introduced into one of the input terminals of the AND circuit, and on the other hand,
The pulse width modulated signal is passed through a delay circuit. By introducing this into the other input terminal of the AND circuit, it is possible to obtain a narrow pulse width modulation signal whose pulse width is narrowed by the delay time of the delay circuit.

[Embodiment] Next, an image signal processing device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings, citing preferred embodiments in relation to a device incorporating the same.

In FIG. 1, reference numeral 20 is an exposure device incorporating an image signal processing device 22 according to this embodiment.

This exposure device 20 includes a laser diode LD that exposes and records a film F with emitted light L, and a narrow pulse width modulation signal S based on a pixel synchronization signal S1 and digital image data SD.
an image signal processing device 22 that outputs signals p3 and Sp3, and a laser diode drive circuit 24 (hereinafter referred to as LD drive) that inputs the narrow pulse width modulation signal Sp3 and outputs a drive current I sufficient to directly modulate the laser diode LD. circuit).

The image signal processing device 22 inputs the pixel synchronization signal S1 and the image signal S3, and generates a first pulse width modulation signal Spl.
a pulse width modulation circuit 23 that outputs the narrow pulse width modulation signal Spl, and a pulse width modulation circuit 23 that manually outputs the first pulse width modulation signal Spl.
It has a narrow pulse generation circuit 25 that outputs p3 and Sp3.

The pulse width modulation circuit 23 includes a mirror integrator 26 that inputs the pixel synchronization signal S1, which is a square wave signal, and outputs a triangular wave signal S2, and inputs the digital image data SD to generate an image signal S3. An image signal output device 28 inputs the triangular wave signal S2 and the image signal S3 and outputs the first signal.
The comparator 30 outputs the pulse width modulated signal Spl.

On the other hand, the narrow pulse generation circuit 25 includes a delay circuit 29 whose delay time is td, a matching resistor RO, and a delay circuit 29.
The second pulse width modulation signal Sp2, which is the output signal of
It is composed of an AND circuit 31 consisting of an ECL IC that outputs .

Here, as shown in FIG. 2, the image signal S3 has a level Vx between a first DC level V1 and a second DC level V2 exceeding the first DC level V1 as a change area. The triangular wave signal S2 has a variation region at a level VY between the third DC level V3, which is lower than the first DC level V1, and the second DC level V2.

Note that the third DC level v applied to the triangular wave signal S2
3 can be changed by changing the value of the resistor RV2 in the resistor voltage divider circuit 32 consisting of the resistor R1 and the resistor RV2 provided on the input side of the operational amplifier 27 constituting the Miller integrator 26, The slope of the triangular wave signal S2 can be determined by resistor R3 and capacitor C3. Also, the first
Level determination of the DC level V1 and the second DC level V2 will be described later.

The image signal output device 28 includes a D/A converter 34 and a resistive voltage divider circuit 36 including a resistor R4 and a resistor RV5 connected to a reference voltage terminal Vref of the D/A converter 34. The output terminal Vout of the /A converter 34 is connected to the input terminal of the comparator 30. Therefore, the first DC level V1 and the second DC level V2 are set in the resistor voltage divider circuit 3.
It is only necessary to change the resistance RV5 of No. 6.

Note that the data input terminal Da of the D/A converter 34 has 10
It is configured such that bit digital image data SD is introduced.

The LD drive circuit 24 includes a current switch unit 40 into which narrow pulse width modulation signals Sp3 and Sp3 having different polarities are introduced;
The current switch section 40 basically consists of a transistor TR'l and a transistor TR2 whose emitter terminals are coupled together. On the other hand, the constant current section 42 is composed of a constant voltage generator 44, a transistor TR3, and a resistor R16, and the current I is connected to the power supply voltage -CC and the transistor TR.
3 and the resistor R16. Then, as described above, the current I output from the LD drive circuit 24 is introduced into the laser diode LD.

The exposure apparatus incorporating the image signal processing apparatus according to this embodiment is constructed as described above, and its operation will be described next.

FIG. 2 is a waveform diagram illustrating the operation of the exposure apparatus 20 shown in FIG. 1.

Therefore, the pixel synchronization signal S1 corresponding to pixel numbers n to n+5 (see FIG. 2) of the square wave signal is sent to the image signal processing device 22.
A synchronizing signal of the mirror integrator 26 and the D/A converter 34 constituting the synchronizing signal is inputted to the input terminal CL. In this case, the mirror integrator 26 integrates the pixel synchronization signal S1 to generate a triangular wave whose DC level changes between the third DC level V3 and the second DC level V2, as shown in FIG. Outputs signal S2.

On the other hand, the digital image data SD input to the D/A converter 34 constituting the image signal output device 28 in synchronization with the pixel synchronization signal S1 has a DC level that is the first DC level V1 and the second DC level V1. The image signal S3 is converted into an image signal S3 whose changing region is between the DC levels V2 and V2. Note that the DC level of the image signal S3 is here a first DC level v1, a second DC level V2, and a fourth DC level between the first DC level V1 and the second DC level V2. There are three levels of V4.

Therefore, the first pulse width modulation signal Spl shown in FIG. 2 is obtained as the output signal of the comparator 30. In this case, as can be understood from the figure, by providing a so-called offset Voff between the first DC level V1 for the image signal S3 and the third DC level V3 for the triangular wave signal S2, As shown in the figure, even if a signal delay occurs when the image signal S3 moves from pixel number n to pixel number n+1, or a signal delay occurs when moving from pixel number n+2 to pixel signal n+3, the waveform of image signal S3 Since the comparison process is performed using the signal level after being settled, the pulse width modulated signal S output from the image signal processing device 22 is compared to the image signal S3 having the same first DC level V1.
The pulse widths PA, PB, and PC of pl are exactly constant and do not fluctuate.

As described above, this first pulse width modulation signal Spl is introduced as it is into one terminal of the AND circuit 31, and is also passed through the matching resistor RO and the delay circuit 29 whose delay time is td. It is introduced into the other input terminal of the product circuit 31 as a second pulse width modulation signal Sp2. Second
As can be understood from FIG. 2, the pulse width modulated signal Sp2 is a signal delayed by the delay time td compared to the first pulse width modulated signal Sp1.

Narrow pulse width modulation signal S which is the output signal of AND circuit 31
As shown in FIG. 2, p3 is a signal through which only the common high level portion of the first pulse width modulation signal Spl and the second pulse width modulation signal Sp2 has passed. The pulse width of each pulse constituting the pulse width modulation signal Sp2 is narrowed by the delay time td, and the LD drive circuit 2
It will be introduced in 4th. Note that the narrow pulse width modulation signal Sp3 is obtained as an inverted signal of the narrow pulse width modulation signal Sp3.

In the LD drive circuit 24, the narrow pulse width modulation signal Sp3
In response to the high level of the signal Sp3 and the low level of the narrow pulse width modulation signal Sp3, the transistor TRI constituting the current switch section 40 is activated and the transistor TR2 is activated. On the other hand, the transistor TR1 is turned off in response to the low level of the narrow pulse width modulation signal Sp3 and the high level of the narrow pulse width modulation signal Sp3.

Then, when the transistor TR'l is activated, a current I for driving the laser diode LD is supplied from the constant current section 42 side, whereby the laser diode LD is modulated by the narrow pulse width modulation signal Sp3. Ru. Therefore, by irradiating the film F with the emitted light L corresponding to the narrow pulse width modulation signal Sp3 from the laser diode LD without moving the film F in a direction perpendicular to the paper surface, the digital image data can be transferred onto the film F. An image corresponding to SD is formed.

In this case, according to the present embodiment, if the pulse width of the pulse width modulation signal Spl is 15 ns to 19 (lns) and the delay time td of the delay circuit 29 is Ions, then the narrow pulse width modulation signal Sp3 pulse width is 5nse
c to 180 nsec, and the pulse width modulation signal Spl
The pulse width of each pulse becomes narrower. Therefore, the so-called concentration dynamic range, expressed as the ratio of the maximum pulse width to the minimum pulse width, is (190ns/15
n s ) = 1 2. From 7 (1 8 0 n
s/5ns) -36, which is approximately three times as large.

Note that the delay circuit 29 that obtains the Ions delay time td is obtained by using approximately 2 m of coaxial cable, and since the coaxial cable has good high-speed response, it does not cause much waveform distortion on the output side. . Furthermore, instead of the coaxial cable, buffer elements of the ECL IC may be connected in series for the delay time.

In addition, in order to maintain the intensity of the emitted light L output from the laser diode LD at a constant value, a narrow pulse generation circuit 25 is used.
The narrow pulse width modulated signals Sp3 and Sp3 output from the AND circuit 31 constituting the circuit are not shown in FIG.
It may also be supplied to the LD drive circuit 50 to which a (tomatic Power Control) circuit is added.

As understood from FIG. 7, this APC circuit includes a photodiode PD that monitors the intensity of the emitted light L from the laser diode LD, and an I/O circuit that converts the output current l of the photodiode PD into a voltage signal e1. V converter 52;
A/D that converts voltage signal e1 into digital voltage signal E1
A converter 54, a CPU 56 which is a one-chip microprocessor that includes a look-up table that has been measured and stored in advance regarding the correspondence between the digital voltage signal E1 and the current I that drives the laser diode LD, and a CPU 56 that is a one-chip microprocessor that includes a look-up table that has been measured and stored in advance regarding the correspondence between the digital voltage signal E1 and the current I that drives the laser diode LD, and A D/A that converts the digital voltage signal E2 output from the CPU 56 into an analog voltage signal e2.
The converter 58 and the output impedance applied to the analog voltage signal e2 are reduced to provide a gain of 1, which is introduced into the base terminal of the transistor TR3 constituting the constant current section 42.
buffer 59.

[Effects of the Invention] As described above, according to the present invention, a pulse width modulation signal can be converted into a narrow pulse width modulation signal using a delay circuit and an AND circuit.

Here, since relatively high-speed and wide-band circuits can be used as the delay circuit and the AND circuit, so-called waveform rounding does not occur in the narrow pulse width modulation signal. Therefore, the number of density gradations corresponding to the brightness range of the image can be increased, and an image signal processing device with a wide dynamic range of density can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an exposure device incorporating an image signal processing device according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the exposure device shown in FIG. 1, and FIG. 4 to 6 are waveform diagrams illustrating the operation of the image signal processing device shown in FIG. 3; FIG. 7 is a circuit block diagram of the image signal processing device according to the prior art; FIG. FIG. 3 is a circuit block diagram showing a modification of the laser diode drive circuit. 20...Exposure device 22...Image signal processing device 23...Pulse width modulation circuit 25...Narrow pulse generation circuit 26...Miller integrator 28...Image signal output device 29...Delay Circuit 30... Comparator 31... AND circuit 32, 36... Resistance voltage divider circuit 34... D/A converter F... Film L... Light emitting light LD... Laser diode S1... Pixel synchronization signal S2... Triangular wave signal S3... Image signal SD... Digital image data Spl... First pulse width modulation signal Sp2... Second pulse width modulation signal Sp3, Sp3...Narrow pulse width modulation signal V1~■3・
・DC level

Claims (1)

[Claims] (1) a pulse width modulation circuit that compares an image signal and a triangular wave signal and outputs a pulse width modulation signal; a delay circuit that delays the pulse width modulation signal by a predetermined time; and an output from the pulse width modulation circuit. A pulse width modulation signal output from the delay circuit is introduced into one input terminal, and a delayed pulse width modulation signal output from the delay circuit is introduced into the other input terminal, so that a pulse width modulation signal that is narrower than the pulse width of the pulse width modulation signal is introduced into the other input terminal. An image signal processing device comprising: an AND circuit that outputs a narrow pulse width modulation signal having a width.