JPH03216222A - Manufacture of lead frame for semiconductor device - Google Patents

Manufacture of lead frame for semiconductor device

Info

Publication number
JPH03216222A
JPH03216222A JP1235690A JP1235690A JPH03216222A JP H03216222 A JPH03216222 A JP H03216222A JP 1235690 A JP1235690 A JP 1235690A JP 1235690 A JP1235690 A JP 1235690A JP H03216222 A JPH03216222 A JP H03216222A
Authority
JP
Japan
Prior art keywords
clearance
lead
punching
internal
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1235690A
Other languages
Japanese (ja)
Other versions
JP2825584B2 (en
Inventor
Kenji Yamaguchi
山口 建司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Orient Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Orient Watch Co Ltd filed Critical Orient Watch Co Ltd
Priority to JP1235690A priority Critical patent/JP2825584B2/en
Publication of JPH03216222A publication Critical patent/JPH03216222A/en
Application granted granted Critical
Publication of JP2825584B2 publication Critical patent/JP2825584B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Punching Or Piercing (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent a positional deviation for a internal lead by making a clearance of former process side of a die between a punch and a die on the side punching process larger than that of a rear process side. CONSTITUTION:The clearance C1 between the punch 21 and the die 23 on the 1st process on the punching layout, the clearance C2 of the 2nd process and the clearance C3 on the 3rd process are made as the relation of C1 > C2 > C3. The internal lead 24 is applied with the force so as to bend the lead 24 on the punching time. Next, when the side of the lead 24 opposite to the side which is already punched is punched, the lead 24 is apt to bend to the arrow direction. The forces generated on each drawing are made equal by changing the clearances between the punch 21, 26 and the die 23, 27, or mutually counterbalanced because they are operating to the opposite direction. There is the effect to prevent the positional deviation.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は.リードフレームの製造方法に関するもので特
に.半導体装置用リードフレームの製造方法に適用する
ものである。
[Detailed Description of the Invention] (Industrial Application Field) The present invention... Especially regarding the manufacturing method of lead frames. The present invention is applied to a method for manufacturing lead frames for semiconductor devices.

(従来の技術) 従来の半導体装置用リードフレームの製造方法について
図面に基づいて説明する。第4図に半導体装置用リード
フレームの一例を示す。ダイバー42がグイパット41
を吊っている。複数のインターナルリード43が,ダイ
バット41の周りに配してある。
(Prior Art) A conventional method for manufacturing a lead frame for a semiconductor device will be described based on the drawings. FIG. 4 shows an example of a lead frame for a semiconductor device. Diver 42 is Guipat 41
is hanging. A plurality of internal leads 43 are arranged around the die butt 41.

このような半導体装置用のリードフレームを製造する場
合,第5図に示すような抜きレイアウトで製造する。流
れ方向は右である。11〜mはそれぞれ初工程からm工
程までの打抜き形状を示す。この各工程では,材質.材
厚共に等しいので,半導体装置用リードフレームのイン
ターナルリードは.初工程から第m工程まで同じ値のパ
ンチとダイのクリアランスで製造されていた。
When manufacturing such a lead frame for a semiconductor device, it is manufactured with a punched layout as shown in FIG. The flow direction is to the right. 11 to m each indicate the punching shape from the initial process to the m process. In each of these processes, the material Since both the material thicknesses are the same, the internal leads of lead frames for semiconductor devices are. The punch and die clearance was the same from the first process to the mth process.

(発明が解決しようとする課題) しかし,このようなリードフレームの製造方法に於いて
,初工程から最終工程まで打ち抜いたインターナルリー
ドは,先端を切離され内部応力が開放されると後工程で
打抜かれた方向へ位置づれを起こす欠点があった。
(Problem to be Solved by the Invention) However, in such a lead frame manufacturing method, the internal leads punched from the initial process to the final process cannot be used in the subsequent process after the tips are cut off and the internal stress is released. There was a drawback that the position would shift in the direction in which the punch was punched.

そこで本発明は,インターナルリードの両側面の形状を
交互に打抜いた場合でも,インターナルリードの位置づ
れが起きず,正規の位置に保持されるリードフレームの
製造方法を提供することを目的としている。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a lead frame in which the internal leads do not shift in position even when the shapes of both sides of the internal leads are punched out alternately, and the internal leads are held in their normal positions. It is said that

(課題を解決するための手段) 上記課題を解決するため本発明の半導体装置用リードフ
レームの製造方法は.プレス加工により形成され.複数
のインターナルリードを有する半導体装置の一本のイン
ターナルリードを2回以上の打抜き工程で形成し,前工
程で打抜かれる側面の打抜き工程のパンチとダイのクリ
アランスが,後工程で打抜かれる側面の打抜き工程のパ
ンチとダイのクリアランスよりも大きくした。
(Means for Solving the Problems) In order to solve the above problems, the present invention provides a method for manufacturing a lead frame for a semiconductor device. It is formed by press working. One internal lead of a semiconductor device having multiple internal leads is formed in two or more punching processes, and the clearance between the punch and die in the punching process of the side surface punched in the previous process is the same as that of the punch and die in the punching process in the later process. This was made larger than the clearance between the punch and the die in the side punching process.

(作用) 上記の半導体装置用リードフレームの製造方法は.第6
図(a)に示すように,インターナルリード64の片側
面を打抜く際に矢印に示すように.打抜いたパンチ61
の方向へインターナルリード64を正規の位置からづら
せようとする力が.クリアランスCと押え力によって変
化することを利用したものである。すなわち.第6図(
a)に示すように,インターナルリード64の片側面を
抜く際,インターナルリード64を押さえる力は,スト
ッパー62とダイ63によって材料65を押さえるため
大きい.しかし.第6図(b)に示すように,その後の
工程では.インターナルリード64を押さえる力は,イ
ンターナルリードだけを押さえるために小さいくなる.
また,インターナルリードを正規の位置からづらせよう
とする力は.クリアランスCが大きいと太き《,クリア
ランスCが小さいと小さくなる.インターナルリードを
押さえる力が,前工程と後工程で異なり,この差を相殺
するため,前工程で打抜《側面のクリアランスより後工
程で打抜《側面のクリアランスを小さくすることによっ
て.インターナルリードを正規の位置に保持することが
できる。
(Function) The method for manufacturing the above lead frame for semiconductor devices is as follows. 6th
As shown in Figure (a), when punching out one side of the internal lead 64, as shown by the arrow. Punch 61
A force that tries to move the internal lead 64 from its normal position in the direction of . This takes advantage of the fact that it changes depending on the clearance C and presser force. In other words. Figure 6 (
As shown in a), when pulling out one side of the internal lead 64, the force to press the internal lead 64 is large because the stopper 62 and die 63 press the material 65. but. As shown in Figure 6(b), in the subsequent steps. The force for pressing the internal lead 64 becomes small because only the internal lead is pressed.
Also, the force that tries to move the internal lead from its normal position is... The larger the clearance C, the thicker it becomes, and the smaller the clearance C, the smaller it becomes. The force holding down the internal lead differs between the front and back processes, and in order to offset this difference, the punching (side clearance) is made smaller in the post process than the punching (side clearance) in the front process. The internal lead can be held in the correct position.

以下に本発明の実施例を図面に基づいて説明する.第1
図は.インターナルリードの抜きレイアウトを示す図で
ある.中央のインターナルリードを打抜く第1工程から
順にインターナルリードの先端を切離す第n工程まで中
央から順に外側へ打抜きインターナルリード,タイバー
,グイパッドが,形成される。それぞれのインターナル
リード,タイバー,グイパッドは,2または3工程で形
成される。
Examples of the present invention will be described below based on the drawings. 1st
The diagram is. This is a diagram showing the layout of internal leads. From the first step of punching out the center internal lead to the nth step of cutting off the tips of the internal leads, the internal leads, tie bars, and gouging pads are formed by punching outward from the center in order. Each internal lead, tie bar, and guide pad is formed in two or three steps.

この抜きレイアウトの第1工程lのクリアランスはCI
,第2工程2のクリアランスはC2,第3工程3のクリ
アランスはC3,第4工程4のクリアランスはC4,第
5工程5のクリアランスはC5第n工程のクリアランス
はC5であり,それぞれのクリアランスはC I>C2
>C3>C4>C5の関係である。
The clearance of the first process l of this punching layout is CI
, the clearance of the second process 2 is C2, the clearance of the third process 3 is C3, the clearance of the fourth process 4 is C4, the clearance of the fifth process 5 is C5, the clearance of the nth process is C5, and the respective clearances are CI>C2
The relationship is >C3>C4>C5.

このように構成したクリアランスと打抜き順が,該当イ
ンターナルリードに及ぼす作用を第2図で説明する。第
2図(a)は,インターナルリード24の側面を打抜く
バンチ21とそれと対になるダイ23,バンチ2lをガ
イドし材料を押さえるストッパ一22の断面である。第
2図(b)は第2図(a)で打抜いたインターナルリー
ド24の反対側を打抜くパンチ26とダイ27そしてス
トッパー22の断面図である。
The effect that the clearance and punching order configured in this way have on the corresponding internal lead will be explained with reference to FIG. FIG. 2(a) is a cross section of the bunch 21 punching out the side surface of the internal lead 24, the die 23 paired with it, and the stopper 22 that guides the bunch 2l and presses the material. FIG. 2(b) is a sectional view of the punch 26, die 27, and stopper 22 for punching the opposite side of the internal lead 24 punched in FIG. 2(a).

第2図(a)で打抜かれた時インターナルリード24は
.矢印の方へインターナルリード24を曲げようとする
力を受ける。次に第2図(b)で既に打抜かれている反
対側のインターナルリード24の側面が打抜かれるとイ
ンターナルリード24は,矢印に示す方向へリードを曲
げようとする力を受ける.第2図(a)で生じる力と第
2図(b)で生じる力は,クリアランスを変化させた事
により等しい力になり,また.逆方向へ作用しているの
で相殺し会う。
When the internal lead 24 is punched out as shown in FIG. A force is applied to bend the internal lead 24 in the direction of the arrow. Next, as shown in FIG. 2(b), when the side surface of the internal lead 24 on the opposite side that has already been punched out is punched out, the internal lead 24 receives a force that tends to bend the lead in the direction shown by the arrow. The force generated in Figure 2(a) and the force generated in Figure 2(b) become equal by changing the clearance, and... Since they act in opposite directions, they cancel each other out.

第3図は本発明の別の実施例を示すレイアウト図である
FIG. 3 is a layout diagram showing another embodiment of the present invention.

第1工程1゛第2工程2゛のクリアランスはCl,第3
工程3゛第n工程のクリアランスはC5である。
The clearance for the first process 1 and second process 2 is Cl, and the clearance for the third process is Cl.
Step 3 The clearance of the nth step is C5.

ここでもCI>C5の関係である. 二のような,クリアランスに構成すると打抜き時に生じ
る力は前記実施例と同様にリードに作用するのでインタ
ーナルリードの抜きレイアウトは中央から順に1つづつ
外側へ打抜《ような規則制のある抜きレイアウトにする
必要はなく一つの工程でいくつもの形状を打抜くように
してもリード位置を正規位置に保持できる。
Here again, the relationship is CI>C5. If the clearance is configured as shown in 2, the force generated during punching will act on the leads in the same way as in the previous embodiment, so the punching layout of the internal leads will be a regular punching layout in which the internal leads are punched outward one by one from the center. There is no need to create a layout, and even if several shapes are punched in one process, the lead position can be maintained at the correct position.

(発明の効果) 本発明は,以上説明したように.インターナルリードの
プレス加工による形成に於いて,前工程で打抜く側面の
クリアランスよりも後工程で打抜《側面のクリアランス
を小さくしたので.インターナルリードの位1づれを防
ぐ効果があり.特にインターナルリードが密集し.当該
インターナルリードの強度が低い場合に有効である.
(Effects of the Invention) The present invention is as described above. When forming internal leads by press working, the clearance of the side surfaces of the punching in the post-process was made smaller than the clearance of the sides of the punching in the pre-process. This has the effect of preventing the internal read from shifting by one position. In particular, internal leads are concentrated. This is effective when the strength of the internal lead is low.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す抜きレイアウト図,第
2図は本発明の実施例を示す打抜き時の断面図.第3図
は本発明の他の実施例を示す抜きレイアウト図.第4図
はリードフレームの平面図,第5図は従来の技術を示す
抜きレイアウト図,第6図は従来の技術を示す打抜き時
の断面図である。 21.61・・・パンチ 23.63 ・ ・ ・ダイ 24.64・・・インターナルリード 26.66・・・パンチ 27.67 ・ ・ ・ダイ 43・・・インターナルリード
Fig. 1 is a punched layout diagram showing an embodiment of the present invention, and Fig. 2 is a cross-sectional view when punching shows an embodiment of the present invention. FIG. 3 is a cutout layout diagram showing another embodiment of the present invention. FIG. 4 is a plan view of a lead frame, FIG. 5 is a punched layout diagram showing a conventional technique, and FIG. 6 is a sectional view of the conventional technique during punching. 21.61...Punch 23.63...Die 24.64...Internal lead 26.66...Punch 27.67...Die 43...Internal lead

Claims (1)

【特許請求の範囲】[Claims] (1)プレス加工により形成され、複数のインターナル
リードを有する半導体装置用リードフレームの製造方法
に於いて、一本のインターナルリードを2回以上の打抜
き工程で形成し、前工程で打抜かれる側面の打抜き工程
のパンチとダイのクリアランスが、後工程で打抜かれる
側面の打抜き工程のパンチとダイのクリアランスより大
きいことを特徴とする半導体装置用リードフレームの製
造方法。
(1) In a method for manufacturing a lead frame for a semiconductor device that is formed by press working and has a plurality of internal leads, one internal lead is formed in two or more punching processes, and one internal lead is punched in the previous process. A method for manufacturing a lead frame for a semiconductor device, characterized in that a clearance between a punch and a die in a punching process for a side surface is larger than a clearance between a punch and a die in a punching process for a side surface to be punched in a subsequent process.
JP1235690A 1990-01-22 1990-01-22 Method for manufacturing lead frame for semiconductor device Expired - Lifetime JP2825584B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1235690A JP2825584B2 (en) 1990-01-22 1990-01-22 Method for manufacturing lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1235690A JP2825584B2 (en) 1990-01-22 1990-01-22 Method for manufacturing lead frame for semiconductor device

Publications (2)

Publication Number Publication Date
JPH03216222A true JPH03216222A (en) 1991-09-24
JP2825584B2 JP2825584B2 (en) 1998-11-18

Family

ID=11803000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1235690A Expired - Lifetime JP2825584B2 (en) 1990-01-22 1990-01-22 Method for manufacturing lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JP2825584B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745770A (en) * 1993-08-02 1995-02-14 Goto Seisakusho:Kk Method for manufacturing lead frame for semiconductor device and press molding apparatus used therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745770A (en) * 1993-08-02 1995-02-14 Goto Seisakusho:Kk Method for manufacturing lead frame for semiconductor device and press molding apparatus used therefor

Also Published As

Publication number Publication date
JP2825584B2 (en) 1998-11-18

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