JPH03216560A - peak detection circuit - Google Patents

Abstract

PURPOSE:To enhance detection accuracy without receiving the effect of the velocity and mark rate of an input signal by constituting a peak detection circuit so that an input signal is converted to equilibrium signals of the same phase and a reverse phase without using the charging and discharging of a condenser and detecting the OR of both phase signals. CONSTITUTION:A non-equilibrium/equilibrium converter circuit 2 is operated by transistors 8, 9, resistors 10 - 13 and a current source 14 and the linear operation range of the circuit 2 is enlarged by the resistors 12, 13. Next, the signal having the same phase as an input signal among equilibrium signals is applied to the base of a transistor 15 and the signal having a phase reverse to that of the input signal among them is applied to the base of a transistor 16. Transistors 27 - 30, 35, 36, resistors 25, 26, 31 - 34 and a current source 37 are operated as an OR circuit 3 and an AND circuit 4 and function obtaining the same effect as the resistors 12, 13 in the circuit 2 is provided to the resistors 31 - 34. By this constitution, the output logical levels of the circuits 3, 4 do not change and a wide range of a linear output logical level can be obtained with respect to the input signal. Hereupon, the transistors 35, 36 perform switching operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak detection circuit that detects the peak of an input signal.

[Prior Art] FIG. 4 is a circuit diagram showing a conventional peak detection circuit shown in, for example, the Proceedings of the 1981 National Conference of the Institute of Electronics and Communication Engineers, 454. In the figure, l is an input terminal for an input signal;
is the output terminal of the peak detection signal, 47 is the circuit power supply, 49
is a transistor whose base is connected to input terminal 1, 50
is a resistor connected to the emitter of transistor 49, 51
is a transistor whose base is connected to the emitter of transistor 49, 52 is a capacitor connected to the emitter of transistor 51, 53 is a transistor to which the voltage of capacitor 52 is applied to the base, and 54 is transistor 5.
This is a resistor connected to the emitter of 3.

Next, the operation will be explained.

A voltage corresponding to the signal input to the human power terminal 1 appears at the resistor 50, and the transistor 51 is operated by this voltage.

Therefore, the capacitor 52 is charged by the current flowing through the transistor 51 constituting the emitter follower, and discharged by the current flowing to the transistor 53 constituting the emitter follower at the next stage. As a result, the peak value of the input signal is held by the capacitor 52 and output as a peak detection signal at the output terminal 6. The charging time constant at this time is given by the product of the emitter resistance of the transistor 51 and the capacitance of the capacitor 52, and is expressed by the following equation.

qle where γ. is the emitter resistance, τ. is the charging time constant, k
is Boltzmann constant, T is absolute temperature, q is elementary charge, Ie
is the emitter current and C is the capacitance of the capacitor.

[Problems to be Solved by the Invention] Since the conventional peak detection circuit is configured as described above, the current flowing through the transistor 5l in a steady state is several μA, and the emitter resistance γ of the transistor 5l is
．． Since the value is very large at several tens of kilohms, there are problems such as the peak value held decreases when the speed of the input signal is slow or when the mark rate decreases when the input signal is a coded signal. .

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a peak detection circuit that is not affected by the input signal speed or mark rate.

[Means for Solving the Problems J] The peak detection circuit according to the present invention includes an unbalanced/balanced conversion circuit that converts an input signal into a balanced signal, and a signal that is in the same phase as the input signal and a signal that is in the opposite phase of the input signal among the balanced signals. an OR circuit to which a signal is applied and whose output logic level is dependent on the input signal.

[Effect]

The peak detection circuit of the present invention detects the peak value of an input signal using an OR circuit to which a balanced signal from an unbalanced/balanced conversion circuit is added.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Fig. 1 shows an embodiment for detecting the amplitude of an input signal, where 1 is an input terminal of the input signal, 2 is an unbalanced/balanced conversion circuit that converts the input signal into a balanced signal, and 3 is the balanced signal. 4 is an AND circuit to which a signal of the same phase and a signal of opposite phase as the input signal are added; 4 is an AND circuit to which a signal of the same phase and a signal of opposite phase are added; 5 is an OR circuit of 3; a differential amplifier to which the output and the output of the AND circuit 4 are added;
Reference numeral 6 denotes an output terminal to which an amplitude detection signal outputted from the differential amplifier 5 is added.

FIG. 2 is a circuit configuration diagram showing a specific configuration of the circuit in FIG. 1, and parts corresponding to those in FIG. 1 are given the same reference numerals.

In FIG. 2, reference numeral 8.9 indicates differentially connected transistors, and the input terminal 1 is provided at the base of one transistor 8. Reference numeral 7 denotes a bias terminal to which a predetermined bias voltage is applied, and is connected to the base of the transistor 9. 10.11 is a resistor connected to the collector of transistor 8.9, 12.13 is a resistor connected to the emitter of transistor 8.9, 14 is a current source commonly connected to the emitter of transistor 8.9, 15 .16 are {-transistors 17, 18, 19, 20, 21 .
22 is a voltage drop diode connected to the emitter of transistors 15 and 16, and 23 and 24 is a diode 19.
．． The resistors 27.28 and 29.30 connected to the cathode side of 22 are respectively differentially connected transistors, so that the emitter voltage of transistor 15 is applied to the base of transistor 27.30, and the emitter voltage of transistor 16 is applied to the base of transistor 27.30. A voltage is applied to the base of transistor 28,29. 25.26 are resistors connected to the collectors of transistors 27.28, 31.32.
33, 34 are transistors 27, 28, 29 .
A resistor is connected to the emitter of 30, 35.36 is a differentially connected transistor, transistor 35 is commonly connected to the emitter of transistor 27.28, and a resistor is connected to the emitter of transistor 23. 3
6 are commonly connected to the emitters of transistors 29 and 30, and their bases are connected to the resistor 24. 37
are current sources commonly connected to the emitters of transistors 35 and 36; 38 is a transistor to which the collector voltage of transistors 27 and 29 is applied to its base; 39 is a transistor to which the collector voltage of transistors 28 and 30 is applied to its base; 40.41 is transistor 38.3
9, a resistor 46 is an operational amplifier provided with an output terminal 6, 42 and 43 are resistors for applying the voltage of the resistor 40 and 41 to the positive and negative terminals of the operational amplifier 46, and 44 is an operational amplifier. A feedback resistor connected to 46, 4
5 is a resistor for applying a predetermined power supply voltage to the positive terminal of the operational amplifier 46, and 47.48 is a circuit power supply.

Figure 3 shows the input signal waveform input to the human power terminal l in Figure 1 ((a) in the same figure). Output signal waveform of unbalanced/balanced conversion circuit 2 ((b) in the same figure). The output signal waveforms of the OR circuit 3 and the AND circuit 4 ((C) in the same figure), the output waveform of the differential amplifier 5 (
It is a figure showing (d) of the same figure.

Next, the operation will be explained.

In FIG. 1, a human input signal having an amplitude Vm input to an input terminal 1 is transferred to a third input terminal by an unbalanced/balanced conversion circuit 2.
As shown in Figure (b), the phase of the input signal is converted into two balanced signals: a signal in the same phase and a signal in opposite phase.

The OR circuit 3 and the AND circuit 4 calculate the peak value of the input signal as “
It is configured to output a logic level that depends on the input signal level, with the output being ``1'' and the base value being ``0''.For this reason, as shown in Figure 3 (C), the logic level that is input with two balanced signals is The output of the sum circuit 3 is "1", that is, the peak value of the input signal, and the output of the AND circuit 4 is "0", that is, the base value of the input signal. The output of the AND circuit 4 is differentially amplified and the amplitude Vm of the input signal is outputted to the output terminal 6 as shown in FIG. 3(d).

In FIG. 2, transistors 8 and 9, resistors 10 and 11
, 12.13 and current source l4 are unbalanced/balanced conversion circuit 2
operates as The resistors 12 and 13 are for expanding the linear operating range of the unbalanced/balanced conversion circuit 2. Among the balanced signals, a signal having the same phase as the input signal is applied to the base of the transistor 15, and a signal having the opposite phase to the input signal is applied to the base of the transistor 16.

Transistors 27, 28, 29, 30, 35, 36, resistors 25, 26, 31, 32, 33, 34, and current source 37
operates as an OR circuit 3 and an AND circuit 4. The resistors 31, 32, 33, and 34 are used to obtain the same effect as the resistor 12, 13 in the unbalanced/balanced conversion circuit 2, and thereby the output logic level of the OR circuit 3 and the AND circuit 4 is saturated. Therefore, an output logic level that is linear over a wide range with respect to the input signal can be obtained. A current having a current ratio corresponding to the input signal level flows through each pair of transistors 27, 28 and 29, 30. Transistors 35 and 36 perform switching operations, and depending on the input signal, transistors 27, 28 or 29, 3
A current is passed through either pair of 0.

Considering the case where a signal of ゜゜l'' level is input to the input terminal l, the unbalanced/balanced conversion circuit 2 sends the same phase ゜゜l゛゜ level to the transistor 15, and the inverted phase ゜" to the transistor l6. 0° level is output. As a result, among the transistors 35 and 36, transistor 35 becomes conductive and transistor 36 becomes non-conductive.
The current of current source 37 flows through transistor 27.28.

The distribution ratio of the current flowing through the transistors 27 and 28 corresponds to the input level because the OR circuit 3 and the AND circuit 4 output an output logic level that is linear with respect to the input level. Therefore, a current corresponding to the "1" level flows through the resistor 25, and a current corresponding to the "O" level flows through the resistor 26.

Next, considering the case where a "0" level signal is input to the input terminal 1, the transistor 36 of the transistors 35 and 36 becomes conductive and the transistor 35 becomes non-conductive, so that the current of the current source 37 flows through the transistors. It runs at 29.30. The distribution ratio of the current flowing through the transistors 29 and 30 is
Similarly to the above, the distribution ratio corresponds to the input level, a current corresponding to the "1" level flows through the resistor 25, and a current corresponding to the "1" level flows through the resistor 26.
A current corresponding to the "0" level flows through.

In this way, a current corresponding to the "1" level always flows through the resistor 25, and a current corresponding to the "0" level always flows through the resistor 26, so that the transistor 39 is connected to the OR circuit 3.
“1” level is output, which is the output of transistor 3.
The "0" level output from the AND circuit 4 is outputted to 8. The output logic level of the OR circuit 3 and the AND circuit 4 depends on the input signal level since both circuits 3.4 operate linearly. Operational amplifier 46 and resistors 42,4
3, 44, and 45 constitute a differential amplifier circuit, and by differentially amplifying the output of the OR circuit 3 and the output of the AND circuit 4, the amplitude of the signal input to the input terminal 1 is can be detected and output to the output terminal 6.

Although the above embodiment shows a circuit for detecting the signal amplitude, by using only the output of the OR circuit 3, the peak value of the input signal can be obtained in the same way as the conventional peak detection circuit shown in FIG. be able to.

[Effects of the Invention] As described above, according to the present invention, a peak detection circuit converts an input signal into a balanced signal of the same phase and an opposite phase without using charging and discharging of a capacitor, and the logic of both phase signals is adjusted. Since it is configured to perform sum detection, it is possible to perform highly accurate detection without being affected by the input signal speed or mark rate, and by adding an AND circuit, it is possible to detect the amplitude of the input signal. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a peak detection circuit according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of a peak detection circuit according to an embodiment of the present invention, and FIG. 3 shows input signals and input signals in FIG. A waveform diagram showing the output of the balanced/balanced conversion circuit, the output of the OR circuit, the output of the AND circuit, and the output of the differential amplifier circuit. FIG. 4 is a circuit diagram showing a conventional peak detection circuit. 1 is an input terminal, 2 is an unbalanced/balanced conversion circuit, and 3 is an OR circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 4 Figure 3 Written amendment (voluntary)

Claims (1)

[Claims] an unbalanced/balanced conversion circuit that converts an input signal into a balanced signal, and a signal that has the same phase as the input signal and a signal that has an opposite phase to the input signal among the balanced signals obtained from the unbalanced/balanced conversion circuit. and an OR circuit configured to have an output logic level dependent on the level of the input signal.