JPH03216764A - Storage system for delay information - Google Patents

Abstract

PURPOSE:To analyze the delay of a digital circuit of a large scale with the small storage capacity and in a short processing time without deteriorating the purpose of an analyzer by turning the digital circuit into a black box every collective units in terms of functions, obtaining and holding the bus delay value, and using this delay value to perform the total delay analysis. CONSTITUTION:A digital circuit of a large scale is turned into a black box 1 every collective units in terms of functions. Then the delay value 2 of a bus covering an input pin through an output pin (output fan-out pin) of the box 1 is obtained and held. Based on the value 2, the total delay analysis is carried out for the digital circuit. Thus it is possible to analyze the delay of the digital circuit of a large scale with the small storage capacity and in a short processing time without deteriorating the purpose of an analyzer.

Description

[Detailed Description of the Invention] [Summary] The present invention is based on a delay information storage method that stores delay information by converting digital circuits into black boxes into coherent units. The purpose of this system is to obtain and hold the values and use them to perform the overall delay analysis, and to perform delay analysis of large-scale digital circuits with a small memory capacity and short processing time without compromising the analyst's purpose. Regarding digital circuits, make a black box into functionally coherent units, calculate the delay values of each bus from the input pin to the output pin, and store them in the black box, and then use the delay values held in this black box. is configured to perform the overall delay analysis of the large-scale digital circuit described above. [Industrial Field of Application] The present invention relates to a delay information storage method for storing delay information by blanking it into a unit of a digital circuit. In recent years, with the increase in the scale of digital equipment, the number of gates has increased compared to the conventional scale of hundreds of thousands of gates.
It is necessary to perform delay analysis on a scale of several million gates with reasonable computer storage capacity and processing time. Delay analysis of a synchronous digital device determines whether a signal can be propagated between storage elements such as registers and 1111FF (Flinopflosop) through the bus in the combinational circuit within the cycle time of the crosslock. We will take action based on the results.

[Conventional technique] In order to reduce storage capacity and analysis time, conventional delay analysis creates a black box for each LSI, which is one of the implementation layers, and performs delay calculations for each black box. I was trying to perform an overall delay analysis. However, as the degree of integration of LSIs has increased, BRA/NOKUBONOX in LSI units has become an inappropriate method from the viewpoint of where and how to correct the N analysis results. For this reason, it is not possible to adopt the conventional method of creating a blank box for each implementation, and we have been dealing with this by dividing the analysis target and performing it partially. [Problem to be solved by the invention] Therefore, it is not possible to analyze the entire digital circuit at once, and it becomes necessary to perform delay analysis on the paths between the parts that have been analyzed separately.
The problem was that the operation became extremely complicated. The present invention uses a black box as a functionally coherent unit to determine and hold the delay value of a path, and uses this to perform overall delay analysis.The present invention enables delay analysis of large-scale digital circuits to be performed in a short and small storage capacity. The aim is to do this without compromising the analyst's objectives due to processing time. [Means for solving the problem] The means for solving the problem will be explained with reference to Figure 1. In Figure 1, the Blank box is a black box that converts a large-scale digital circuit into functionally coherent units. The delay value 2 is the delay value calculated for the bus heading from the 10-man branok box pin to the output pin (output fan-out pin). [Operation] As shown in FIG. 1, the present invention creates a black box l into a functionally coherent unit for a large-scale digital circuit and creates a path from its input pin to its output pin (output fan-out pin). The delay value 2 is determined and held, and the delay value 2 held by Black Bonoku l is used to perform a delay analysis of the entire large-scale digital circuit. Therefore, delay analysis of large-scale digital circuits can be done with less memory by calculating and storing the delay value 2 of the path in functionally coherent units by determining and holding the delay value 2 of the path. It is possible to perform the analysis without compromising the purpose of the analyst with the large capacity and short processing time. [Embodiment] Next, the configuration and operation of an embodiment of the present invention will be explained in detail using FIGS. 1 to 3. In Figure 1,
A blank box is a large-scale digital circuit that is divided into functionally coherent units, such as arithmetic circuits, decoder circuits, and multiplexer circuits, which are functionally coherent combinational circuit units with a high pin-to-gate ratio. It is. This black boxing can be done by defining one logical symbol at the logic design stage, expanding it at the implementation stage, and automatically recognizing what is handled at the gate level and turning it into a black box. Also, in sequential circuits with strong functional cohesion, such as counters and pipeline sections, paths between storage elements that are closed internally? You may also check and delete them in advance to create a black box to improve the efficiency of delay analysis. Delay value 2 is the delay value obtained for the path from the blank posoc 10 input pin to the output pin (output fan-out pin). This delay value 2 is the delay value T of the gate itself. Delay value T due to ats and wiring
■、．． It is calculated from the sum of the input pins in the figure.
It is the delay value (Σ(TsaLe"TmirJ)) from 1 to 2 to a pin on the output fanout having a bus.

The manual boundaries of blank boxes are the input pins of the game F on the blank boxes 10 input boundaries selected into functionally coherent units.

The output bound of the Branok box is II! This is the output pin (output fanout pin) of the fanout of the gate on the output boundary of the black box l selected as a functionally coherent unit.

Figure 1 (portion) shows an example of the number of delays. In Figure 1 (portion), equation (1) represents the delay number. Number of delays = number of pins on input boundary of blank ponox x
The number of pins on the output fan-out boundary of Bra, Kuposoku
・・・・・・・・・・・・・・・(B.

For example, in the example shown in Figure 1 (a), the number of delays = 5 (number of pins on the input boundary) x 3 (number of pins on the output fan-out boundary) = 15 (2). Therefore, even if there is a faulty gate in the black box (Fig. 1(a)), by using black box 1, the number of delay values can be reduced to 15 as shown in (2) above, and the overall This makes it possible to reduce the storage capacity for storing delay values in digital circuits, reduce processing time, and perform delay analysis. Next, the operation of the configuration shown in FIG. 1 will be explained in detail using the flowchart shown in FIG. In Figure 2, ■ calculates and stores the bus delay for all gates and their output wiring. @ specifies the gate group to be converted into a blank box. This can be done by an analyst instructing a blank node 1 for each functionally coherent unit as shown in Figure 1 (a), for example, from a large-scale digital circuit, or by As described above, when one logical symbol at the logical design stage is expanded to the implementation stage, the group is automatically designated as a blank box 1.

■ recognizes all input pins of input gates on the boundary and all fanouts of output gates. This means that, for example, for Figure 1 (a) Bra Nokubonokus l specified by @, all the input gates on the input boundary are Kapin ■ or ■,
And extract and recognize all fanout pins ■ or ■ on the output fanout boundary. ■ Calculates the delay value for all combinational paths from the input boundary pin to be converted into a blank box to the fanout boundary pin to be converted to a blank box, and replaces the detailed delay storage part for each gate with this value. This calculates all the delay values of the bus going from the input pin (without) on the input boundary of the fan-out boundary in Figure 1 (A) to the output pin on the output fan-out boundary, and calculates the delay values of the bus that each gate has. Replace the previous delay value, reduce the number of delays, and reduce storage capacity. [Phase] determines whether there are any other circuits to be black boxed and whether the required memory capacity is appropriate. If YES, analyze the delay value of the entire digital circuit using the delay value of the bus from the input pin of black box l to the output fan-out pin obtained using 0,0. As described above, for a large-scale digital circuit, the delay value of the path between the input pin and the output fanout pin of the black box box 1 is determined by dividing it into a functionally coherent unit, and the delay value of each gate is calculated. By changing the value to a value and storing it in the black box 1, the number of delay values to be held can be extremely reduced, making it possible for the analyst to perform the desired delay analysis with less storage capacity and in a short time. Figure 3 shows an explanatory diagram of the number of delays. 3rd rM (a)
indicates the number of delays required for each gate. ij Figure 3 (1:I) shows examples of gate delays. The gate on the left has two input pins (■, ■), two output pins, and three fan-out pins (■, ■, ■). The calculation example on the right shows the delay number. Delay number, ■
These numbers correspond to a total of six paths: 1■, ■1■, ■1■, ■1Φ, ■1■, and ■10. FIG. 3(c) shows the number of delays when not using a black point. In this case, the delay number i j k Therefore, unless it is made into a black box 1, it is necessary to have the number of delays equal to the number of delays described above.However, according to the present invention, the part made into a black box 1 is (mouth)
As shown in Figure 2, the number of delays can be reduced, and the total number of delays can be significantly reduced. [Effects of the Invention] As explained above, according to the present invention, the delay value 2 of the bus is determined and held in the Buranok box 1 in a functionally coherent unit, and this is used to perform the overall delay analysis. Because it adopts a configuration that allows delay analysis of large-scale digital circuits, it can be performed with a small storage capacity and short processing time without compromising the purpose of the analyzer. This makes it possible to efficiently develop logic devices 1 that need to operate on a large scale and at high speed, and significantly reduces the development period and development man-hours.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of the present invention, and FIG. 3 is a diagram explaining the number of delays. In the figure, L represents the black ponox and 2 represents the delay value. Patent employee Fujitsu Co., Ltd.

Claims (1)

[Claims] In a delay information storage method in which delay information is stored by converting a digital circuit into a black box into a coherent unit, a large-scale digital circuit is converted into a functionally coherent unit into a black box (1). The delay value (2) of the path from the input pin to the output pin of this is calculated and stored in the black box (1), and the delay value (2) held in this black box (1) is calculated.
) is used to carry out delay analysis of the entire large-scale digital circuit.