JPH03216860A - Compressed audio signal reproducing device - Google Patents

Abstract

PURPOSE:To satisfactorily realize the reproducing thin the device even by using such a small capacity of a memory as less than that of two tracks by detecting whether the memory is writable or not from a comparison between a write address and a read address and managing a write enable signal by a system control part. CONSTITUTION:The device is provided with a write address control part 54, a read address control part 55, a residual amt. detecting circuit 10a, a comparing part 10b for outputting the write enable signal (a) and the system control part 11 for giving a write instruction (b). Then, whether the memory 33 is writable or not is detected, and the write enable signal is generated, and then whether this write enable signal is outputted or not is managed by the system control part 11. By this method, the write instruction can be given in good timing, and even by using the memory of a small capacity, the reproducing is easily feasible without breaking a sound even in any recording pattern based on a format.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a compressed audio signal reproducing apparatus for reproducing a time-base compressed audio signal recorded on a magnetic disk by, for example, a video floppy recorder.

Conventional Technology In recent years, video floppy recorders that record still images on 2-inch floppy disks (hereinafter referred to as video floppies) have been commercialized instead of cameras that use film. With the addition of a function to record signals for a predetermined period of time, it is expected that a variety of products will be produced.

The compressed audio signal reproducing apparatus as described above will be described below with reference to the drawings.

FIG. 6 is a block diagram showing a video floppy audio recording device as an example of a device for recording a time-base compressed audio signal, and FIG. 7 shows a recording format of the audio signal. Figure 7 (a
) is a diagram showing a track format, (b) in the same figure shows a sector format, and (c) in the same figure shows each period of the sector format. FIG. 8 is a block diagram of a video floppy audio reproducing apparatus, and FIG. 9 is a diagram showing memory address values during reproduction.

This will be explained below using FIG. 6.

As is well known, the video floppy 40 has 50 concentric tracks running from the outside to the inside. A video signal (still image) or an audio signal is recorded on each track.

Also, the number of rotations of the video floppy 40 is 3600
r E) mx In other words, since it rotates once every 1/60 seconds, a video signal is recorded in one field on each track, and an audio signal is compressed on the time axis to 1/60 seconds and recorded on each track.

The time axis compression ratio of the audio signal is 320 times, 640 times,
Three modes of 1280x are available, and it is possible to record audio signals of approximately 5 seconds, approximately 10 seconds, and approximately 20 seconds on each track. Also, when the time axis compression ratio is 640 times, the audio signal recorded on one track is approximately 10 seconds, but when recording an audio signal longer than that, it is recorded using multiple tracks, and each track has a length of approximately 10 seconds. is recorded with sequence information such as the first audio track, track number, and subsequent audio track number of a series of audio signals added.

As shown in FIG. 6, the audio signal is input to an input terminal 1 color low-pass filter (LPF) 30 to be band-limited, and then input to a time axis conversion circuit 31.

The time axis conversion circuit 31 is well known and includes an A/D converter 32 that converts an analog audio signal into a digital signal, a memory 33 that stores the digital signal, and a D/A converter that converts the digital signal into an analog signal. It is composed of a container 34.

The signal input to the time axis conversion circuit 31 is converted into a digital signal by the A/D converter 32. Thereafter, it is written into the memory 33 at the write clock frequency fv. After this writing is completed, the data is read out at the read clock frequency fr, and converted into an analog signal by the D/A converter 34. Time axis conversion rate K of time axis conversion circuit 31
c is expressed by the following formula.

Kc=fw/fr When Kca1, the time axis conversion circuit 31 operates as a time axis compression circuit, and when Kca1, the time axis conversion circuit 31 operates as a time axis expansion circuit.

During recording, the time axis conversion circuit 31 operates as a time axis compression circuit and outputs a time axis compressed audio signal (hereinafter referred to as a compressed audio signal) that is time axis compressed to 1/60 seconds. An adder 35 adds a control record and a flag to this compressed audio signal. Thereafter, the signal passes through an emphasis circuit 36, an FM modulation circuit 37, and an amplifier 38, and is recorded on a video floppy 40 by a magnetic head 39.

Next, the recording format of the audio signal will be explained using FIG. 7. FIG. 7(a) is a diagram showing the track format. DSP is the data ● start φ point. The compressed audio signal is divided into four sectors and recorded, with a space provided between each sector. Figures (b) and (c) are diagrams showing sector formats. The start flag and end flag indicate the beginning and end of a sector, and serve as a time axis reference when reproducing a compressed audio signal. The control code is information possessed by the audio signal, and includes the first audio track number and subsequent audio track number of the series of audio signals mentioned above, the track number where the corresponding video signal is recorded, the time axis compression ratio, etc. The same control code is recorded in each sector on the same track.

The same compressed audio signal as the last part of the compressed audio signal of the previous sector is recorded in the overlap.

Furthermore, although the start flag is a positive signal in FIG. 7(b), it becomes a negative signal when, for example, no compressed audio signal is recorded in this sector. Further, the end flag is a negative signal, but becomes a positive signal if, for example, recording of the compressed audio signal ends in this sector and does not continue to the next sector. That is, the polarity of these two flags represents the sector type. There are four types of sectors: Type 1 is the type that continues on the next sector on the same track. Type 2 is the type that follows sector O of the next track. Type 3 indicates the last sector of the sequence and type 4 indicates an unused sector.

The reproduction operation of a compressed audio signal recorded in the above format will be explained with reference to FIGS.

40 is a video floppy; 60 is a playback head; and 61 is a head access section for moving the playback head 50 to an arbitrary track. 52 is a system control circuit which gives an access instruction to the head access [51] and a write instruction to the write address control circuit 54 so that the playback head 50 accesses a desired track. 53 is a reproduction signal processing circuit that amplifies and FM demodulates the audio signal read out from the reproduction head 50. Reference numeral 31 denotes the time axis conversion circuit mentioned earlier, which operates as a time axis expansion circuit during reproduction. 32 is an A/D converter, and 33 is a memory. 34 is a D/A converter. 54 is a write address control circuit, and the system control circuit 52
When a write instruction is given by , the memory 33 is controlled to write only the compressed audio signal into the memory 33. A read address control circuit 55 controls the memory 33 to decompress the written compressed audio signal and read it out from the memory 33 as a series of audio signals.

The operation of the above circuit will be explained below.

FIG. 9 exemplifies the reproduction operation of a continuous compressed audio signal over two tracks, the first track and the second track.

FIG. 9(a) shows the change in the write address when the compressed audio signal is written into the memory 33, and FIG. 9(b) shows the change in the read address. The shaded areas indicate that each address is incremented.

First, the system control section 52 gives an access instruction to the head access section 51 to move the playback head 50 to the first track. When the playback head 50 moves to the first track, the output of the playback head 50 passes through the playback signal processing circuit 53, is amplified and FM demodulated, and then input to the time axis conversion circuit 31 (time axis expansion circuit). The signal input to the time axis conversion circuit 31 is converted into a digital signal by the A/D converter 32. Then, when a write instruction is given to the write address control circuit 54 from the system control circuit 52, the compressed audio signal converted into a digital signal by the A/D converter 32 is transferred to the address of the memory 33 specified by the write address control circuit 54. will be written to.

As mentioned above, the compressed audio signal is transmitted from sector 0 to sector 3.
The compressed audio signal in sector O of the first track is recorded at addresses A-B, sector 1 at addresses B-C, and sector 2 at addresses C-D.
, sector 3 is written to address DH.

When the writing of the compressed audio signal for the first track is completed,
For example, the system control unit 52 gives an access instruction to the head access unit 51 so that the playback head 50 accesses the second track, which is the subsequent audio track.

Thereafter, the reading operation of the compressed audio signal of the first track written in the memory 33 is started.

The read addresses are incremented in order from address A, address B1 address C1 address D
passing through. The read digital signal is D/
It is converted into an analog signal by the A converter 34 and output from the output terminal 2.

However, the first track and the second track are continuous audio signals, and in order to reproduce the sound without interruption, the read address must be set at address E, which is the final address to which the compressed audio signal of the first track was written. It is necessary to write the compressed audio signal of the second track until the second track is reached.

Therefore, the system control unit 52 outputs a write instruction signal to the write address control circuit 54 so as to write the compressed audio signal of the second track into the memory 33. Similar to the first track, the compressed audio signal in sector O of the second track is written to address EF, sector 1 to address FNG, sector 2 to address GH, and sector 3 to address HI. After the reading of the compressed audio signal of the first track is completed (reading address E), reading of the compressed audio signal of the second track is subsequently started, and when the reading address reaches I, this series of reproduction operations ends.

Problems to be Solved by the Invention However, in order to realize the above operation, it is necessary to give a write instruction from the system control unit 52 to the write address control circuit 54 in a timely manner.

In the conventional example described above, it is assumed that the first track is used up to sector 3, but sector 3 may be unused.

In that case, only addresses A to D are used for writing in the memory 33 of the first track, and the write instruction must be given before the read address reaches D. Similarly, it is possible that only sector 2 of the first track is used, and in extreme cases, only sector 0 may be used. Further, even if all four sectors are used, sector 3 is a type 2 or type 3 compressed audio signal in which the length is not constant. For this reason, the address required to write one track's worth of compressed audio signals from sector O to sector 3 cannot be uniquely determined. For this reason, write instructions are given at the right time,
In order to reproduce sound without interruption, it was necessary to take measures such as increasing the memory capacity, for example, providing memory for two tracks.

Furthermore, if this is to be achieved with the memory 33 having a capacity of less than two tracks, writing cannot be performed immediately after writing in order to avoid erasing the previously written compressed audio signal. , it is necessary to wait until the writable memory capacity reaches one track, which is extremely difficult. The smaller the memory capacity, the more sensitive the timing of giving write agitation, and it was almost impossible to achieve this using a memory of less than two tracks.

The present invention has been made in view of the above problems, and has the advantage of being able to reproduce any recording pattern that conforms to the format by having the system control unit 52 manage whether or not the memory 33 is in a writable state. The object of the present invention is to provide a compressed audio signal reproducing device that provides a compressed audio signal.

Means for Solving the Problems In order to achieve the above object, the compressed audio signal reproducing device of the present invention includes a recording medium having a plurality of audio tracks in which a time-base compressed audio signal is divided into a plurality of tracks and recorded;
a head for reproducing the time-base compressed signal recorded on the track; a head access section for moving the head to an optimal position on the recording medium; and a reproduction signal processing section for inputting the output signal of the head and performing signal processing. , a memory unit that receives the output signal of the reproduced signal processing unit and temporarily stores the time-axis compressed audio signal; and a write unit that controls the memory unit to store the time-axis compressed audio signal in the memory unit. an address control unit, decompressing and reading out the time-base compressed audio signal stored in the memory unit;
A read address control unit that controls the memory unit so as to obtain a series of audio signals before division, and a read address control unit that compares the outputs of the write address control unit and the read address control unit, and determines which time-base compressed audio signals have not been read out. a remaining amount detection circuit that detects the remaining amount of the memory; a comparison section that detects whether or not writing to the memory section is possible by comparing the output of the remaining amount detection circuit with a predetermined value and outputs a write enable signal; A write enable signal is input, an access instruction is given to the head access section to move the head to a desired position on the recording medium, and if the memory section is writable, the time axis compressed audio signal is input. and a system control section that gives a write instruction to the write address control section to write into the memory.

Operation The present invention uses the above-described configuration to detect whether or not it is possible to write to the memory, and to generate a write enable signal.

By managing whether or not this write enable signal is output in the system control unit, it becomes possible to give write instructions in a timely manner, and even if a small capacity memory is used, no sound can be recorded in any recording pattern that conforms to the format. It becomes possible to easily reproduce the data without interruption.

EXAMPLE A first example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a video floppy audio reproducing apparatus according to a first embodiment of the present invention.

In the figure, 40 is a video floppy disk, 50 is a playback head, and 51 is a head access section, which moves the playback head 50 to an arbitrary track. 53 is a reproduction signal processing circuit that amplifies and FM demodulates the audio signal read out from the reproduction head 50. Reference numeral 31 denotes the time axis conversion circuit mentioned earlier, which operates as a time axis expansion circuit during reproduction. 32 is an A/D converter, 33 is a memory, 34 is a D/A
It is a converter. 54 is a write address control circuit, which controls the memory 33 to write only the compressed audio signal into the memory 33 when a write instruction is given. 55
A read address control circuit controls the memory 33 to decompress the written compressed audio signal and read it out from the memory 33 as a series of audio signals. The above is the same as the conventional example, and will not be explained here.

10 is a write enable signal generation circuit. The write enable signal generation circuit 10 includes a remaining amount detection circuit 10a and a comparison circuit tab. The remaining amount detection circuit 10a detects the remaining amount of the compressed audio signal that has not yet been read out by comparing the write address that is the output of the write address control circuit 54 and the read address that is the output of the read address control circuit 55. It is. The comparison circuit 10b compares the output of the remaining amount detection circuit 10a with a predetermined value, and when the remaining amount becomes less than the predetermined value, the memory 33 determines that it is possible to write the next compressed audio signal, and the memory 33 is able to write the next compressed audio signal. It outputs a signal to the system control circuit 11.

Reference numeral 11 denotes a system control circuit, which controls the head access unit 5 so that the playback head 50 accesses a desired track.
1, and determines whether the memory 33 is in a writable state based on a writable signal, and if writable, the write address control circuit 54
It gives writing instructions to.

As in the conventional example, the operation of reproducing a continuous compressed audio signal over two tracks, the first track and the second track, will be explained as an example.

FIG. 2(a) shows the change in the write address when the compressed audio signal is written into the memory 33, and FIG. 2(b) shows the change in the read address.

The shaded areas indicate that each address is incremented.

First, the system control section 11 gives an access instruction to the head access section 51 to move the playback head 50 to the first track. When the playback head 50 moves to the first track, the output of the playback head 50 passes through the playback signal processing circuit 53, is amplified and FM demodulated, and then input to the time axis conversion circuit 31 (time axis expansion circuit). The signal input to the time axis conversion circuit 31 is converted into a digital signal by the A/D converter 32, and when a write instruction is given to the write address control circuit 54 from the system control circuit 11, the A/D converter 32 The compressed audio signal converted into a digital signal by the write address control circuit 54
The data is written to the address of the memory 33 specified by.

As mentioned above, the compressed audio signal is transmitted from sector 0 to sector 3.
The compressed audio signal in sector 0 of the first track is recorded at addresses A-B, sector 1 at addresses B-C, and sector 2 at addresses C-D.
, sector 3 is written to address DE.

When the writing of the compressed audio signal for the first track is completed,
For example, the system control unit 11 gives an access instruction to the head access unit 51 so that the playback head 50 accesses the second track, which is the subsequent audio track.

Thereafter, the reading operation of the compressed audio signal of the first track written in the memory 33 is started.

The read addresses are incremented in order from address A, address B1 address C1 address D
passing through. The read digital signal is D
The signal is converted into an analog signal by the /A converter 34 and output from the output terminal 2.

FIG. 2(C) shows the output of the remaining amount detection circuit 10a, and the vertical axis shows the remaining amount of data of the unread compressed audio signal. The full scale is the total capacity of the memory 33, which is never exceeded by 1. Any operation that exceeds this will erase the previously written compressed audio signal.

It shows how the remaining amount of data increases as the compressed audio signal of the first track is written, and decreases as reading begins.

As mentioned earlier, the first track and the second track are continuous audio signals, and in order to reproduce the sound without interruption, the final address to which the compressed audio signal of the first track was written must be It is necessary to write the compressed audio signal of the second track to address E before the read address is reached.

That is, the compressed audio signal of the second track must be written before the remaining amount of data reaches 0. Therefore,
The write enable signal generation circuit 10 outputs a write enable signal when the remaining amount of data becomes less than, for example, a predetermined value x (x>O).

Thereby, the system control circuit 11 gives a write instruction to the write address control circuit 54 to write the compressed audio signal of the second track into the memory 33.

Similar to the first track, the compressed audio signal in sector O of the second track is written to write address EF, sector 1 is written to write address FG, and sector 2 is written to write address GH.
Then, sector 3 is written to write addresses H to H. After the reading of the compressed audio signal of the first track is completed (reading address E), reading of the compressed audio signal of the second track is subsequently started, and when the reading address reaches I, this series of reproduction operations ends.

Next, the predetermined value X mentioned above will be described.

Consider implementing the above operation using a memory with a capacity greater than one track and less than two tracks. Initially, nothing is stored in the memory 33.

Therefore, the first track can be written without any problem. However, since the capacity of the memory 33 is two tracks unrecorded, the remaining unrecorded portion is less than the capacity of one track. Therefore, it is not possible to continue writing to the second track.

The second track becomes writable when the first track begins to be read and the remaining unrecorded portion and the read portion of the first track total one track. However, to be precise, when the second track is written, the first track is read at the same time, so one track is not necessarily required to start writing the second track. Therefore, it is possible to write to the second track earlier, but for the sake of simplicity, it is first determined without considering that reading is being performed.

Here, the remaining amount of data, which is the output of the remaining amount detection circuit 10a, is expressed by "the number of addresses to which unread data is written."

Therefore, if the total number of addresses held by the memory is M1, and the number of addresses required to store one sector of compressed audio signals is S, one track is 4XS.

Since the memory capacity is less than 2 tracks, 4XS<M
<8XM Therefore, after writing the compressed audio signal of the first track,
The remaining unrecorded addresses are (M-4XS)<4XS, which is less than one track. Then, when reading of the written first track starts and there are X addresses remaining, the number of addresses that can be recorded is the number of addresses that have already been read (4XS-x) and the unrecorded addresses (M-4XS).
It is the sum of When this sum becomes one track, it becomes possible to write to the second track for the first time, and a write instruction signal is output.

(M-4XS)+ (4XS-x)≧4XS. '−
x5M-4XS Also, as mentioned earlier, considering that when the second track is written, the first track is also read at the same time, the maximum value is set to X. ．． 8, clearly x:aM-4xS<xaax. Therefore, it is sufficient to set X using the above range as a guide; for example, by setting x=M-4XS, it becomes possible to output a write enable signal.

As described above, according to this embodiment, the system control circuit 1
1 determines whether or not the memory 33 is writable based on this writable signal, and can issue a write instruction.

Further, the present invention is very effective even in the case where the compressed audio signal recorded on one track is very short and is subsequently recorded over a plurality of tracks.

FIG. 3 shows an example of this, where continuous audio signals are recorded on the first track and the second track, and the first track is very short as only sector 0 is used. In such a case, a write enable signal may be output even though data has been written to the memory 33.

This is because (B-A)<x holds true because the compressed audio signal written in the memory 33 is short, and even though the writing of the first track has been completed, there is still one audio signal in the unrecorded part of the memory 33. This indicates that there is room to write compressed audio signals for more than one track. In this case, before reading from the memory 33, the compressed audio signal of the subsequent audio track is written again. The system control unit 11 gives an access instruction to the head moving unit 51 to cause the playback head 50 to access the second track. Then, the compressed audio signal of the second track is written into the memory 33. After writing is completed, read operation is performed after confirming that the write enable signal is not output.

However, if the write enable signal is still being output, the subsequent audio track is accessed again and written. Writing is performed in this way until writing is no longer possible, and the ? of the memory 33 is written. A read operation is performed only when writing becomes impossible.

Also, this is the same while reading,
If the write enable signal is still being output even though writing has been performed, the reproducing head 50 is immediately accessed to the next track and writing is performed in the memory 33.

As described above, even if there is a track on which a very short compressed audio signal is recorded, it can be detected during writing. Therefore, it is possible to write the compressed audio signal recorded in the subsequent audio track in advance, and even if there is a track on which a short compressed audio signal is recorded, the audio signal can be played back without interruption. It is possible.

In the above embodiment, x=M-4XS. For example, if the number of addresses of the read address counter incremented per second in the 10-second mode is XI1, then xII≦X. ■ If , it is possible to set X = Xs. In this case, the write enable signal will be output from one second before the reading of the audio signal written in the memory 33 ends. Therefore, if this write enable signal is output even though writing has been performed, this indicates that the written compressed audio signal is 1 second or less.

This makes it possible to use the write enable signal not only to determine whether or not the memory 33 is writable, but also as a time reference until the track is finished being reproduced. For example, in the above embodiment, if there is an image track corresponding to the audio of the first track, the first track The operation of accessing and reproducing the corresponding image track, outputting the write enable signal, and accessing the second track to write the compressed audio signal becomes possible.

Next, a second embodiment of the present invention will be described.

In the second embodiment, in all modes, a write enable signal is output a certain period of time before the reproduction of a track ends.

FIG. 4 is a block diagram of a video floppy audio reproducing apparatus according to a second embodiment of the present invention.

In the same figure, a video floppy 40, a playback head 501
Head access section 51, reproduction signal processing circuit 53, A/
Components that operate in the same way as in the first embodiment, such as the D converter 32, memory 33, D/A converter 34, write address control circuit 54, remaining amount detection circuit 10a, and system control circuit 11, are designated by the same reference numerals. I will not explain it here.

Therefore, the compression ratio detection circuit 20, read address control circuit 21, and comparison circuit 22 will be explained.

The compression ratio detection circuit 20 detects and outputs the time axis compression ratio of the recorded compressed audio signal. As mentioned earlier, audio signals are multiplied by 320x, 640x, and 1x during recording.
Compression recording is performed by selecting from three time axis compression ratios of 280 times. Therefore, if the original sound is not expanded at the same ratio during playback, the original sound will not be played back. The time axis compression ratio is recorded in the control code of the sector, and the time axis detection circuit 20 detects the time axis compression ratio by detecting the control code, for example.

The read address control circuit 21 controls the memory 33 to expand the compressed audio signal written in the memory 33 using the time axis compression ratio detected by the compression ratio detection circuit 20, and read it out from the memory 33 as a lucky audio signal. .

Similar to the comparison circuit 10b of the first embodiment, the comparison circuit 22 compares the output of the remaining amount detection circuit 10a with a predetermined value,
When the remaining capacity falls below a predetermined value, the memory 33 determines that it is possible to write the subsequent compressed audio signal, and outputs a write enable signal to the system control circuit 11, but the compression ratio detection circuit 20 The feature is that the predetermined value is changed depending on the output.

Similar to the first embodiment, two tracks, the first track and the second track,
The operation of reproducing a continuous compressed audio signal across tracks will be explained as an example.

FIG. 5 is a diagram corresponding to FIG. 2 of the first embodiment, but in order to explain the operation of changing the predetermined value of the comparator circuit 22,
For convenience, only writing and reading of the first track is shown. FIG. 5(a) shows that the compressed audio signal is stored in the memory 3.
Figure 3(b) shows the change in the read address when the compressed audio signal written in the memory 33 has a time axis compression ratio of 320 times. Yes, the figure (C) is 64
In the case of 0 times, the same figure (d) shows the case of 1280 times. The shaded areas indicate that each address is incremented.

The reproduction of the first and second tracks on which continuous audio signals are recorded is performed from the writing of the first track, as in the first embodiment, and the compressed audio signal in sector 0 of the first track is stored at addresses A-B. 1 Sector 1 is at address B-C, sector 2 is at address C-D, sector 3 is at address D
- written to E.

At this time, simultaneously with the writing of the compressed audio signal of the first track, the compression ratio detection circuit 2o detects the time axis compression ratio of the compressed audio signal.

When the writing of the compressed audio signal for the first track is completed,
For example, the system control unit 11 gives an access instruction to the head access unit 51 so that the playback head 50 accesses the second track, which is the subsequent audio track.

Thereafter, the reading operation of the compressed audio signal of the first track written in the memory 33 is started at the time axis compression ratio detected by the compression ratio detection circuit 2o.

In this case, the time required to write the compressed audio signal of the first track is constant in all modes because the writing speed does not change depending on the time axis compression ratio. However, the time required for readout varies depending on the mode because the readout speed changes in proportion to the time axis compression ratio.
In the case of 0 times (FIG. 5(C)), it is twice as long, and in the case of 1280 times (FIG. 5(d)), it is 4 times as long.

Therefore, the predetermined value is changed depending on the read speed. In other words, by changing the time axis compression ratio, for example, in inverse proportion to 1/2 times or 1/4 times, the write enable signal is generated at the same time from the end regardless of the time axis compression ratio. It will be output.

For example, as shown in Figure 5(e), an address that is incremented per second at 320 times is X321, and an address that is incremented per second at 840 times is
Ass 1 2 8 If the address that increments in 1 second at 0 times is X 12@@, then Xaa
By setting ll=X*2i+/2 XI2a@= X32@/4 (X2ag≦Xmax), the first track's A write enable signal will be output one second before the end of reading.

When the time axis compression ratio of the compressed audio signal of the first track is 640 times, the read address changes as shown in FIG. One second before the end of reproduction of the track, a write enable signal is output, and the compressed audio signal of the second track is written into the memory 33.

The second embodiment makes it possible to output the write enable signal at the same time at any time axis compression ratio.

As a result, the system control circuit engineer 1 not only does not need to manage the time axis compression ratio, but also can use the write enable signal as a time axis reference until the end of track reproduction. For example, in the above embodiment, if there is an image track corresponding to the audio of the first track, the first track Access and play back compatible image tracks.

If the write enable signal is set to be output, for example, one second before the end of reproduction of a track, it will be output one second before the end of reproduction of the first track in any mode. Therefore, by accessing the second track and writing the compressed audio signal at the same time as the write enable signal is output, it is possible to reproduce the first corresponding image for a long time without any sound interruption. Here, it is set to 1 second, but it can be made longer by taking into account the maximum access time from the corresponding image track of the first track to the subsequent track of the first track (here, it is set as the second track). It is possible to play the image.

In addition, the writable signal can also be used to indicate the end of reproduction, etc., and the writable signal has a wide variety of applications.

In the above embodiment, the write address is W(t)
, when the read address is R(t) and the predetermined value is X, W(t)-R(t)=x W(t)-R(t)>x W(t)-R(t)<x We made three comparisons and output a write enable signal when W (t) - R (t) ≦ x (< x is also acceptable), which means that W (t) - x = R (t) It is also possible to compare three ways: W (t)-x>R (t) W (t)-x<R (t), and in this case, time axis compression of the compressed audio signal with X written to memory is also possible in case 2. By changing the ratio according to the ratio, it becomes possible to output the write enable signal at the same time regardless of the time axis compression ratio, similarly to the above embodiment.

Further, in the above embodiment, the output of the remaining amount detection circuit 10a is outputted as "the number of addresses to which unread data is written", but any output proportional to the remaining amount of data may be used. , may be an analog quantity. Further, although the predetermined value to be compared in the comparison circuit 10b or 22 is a value converted into an address according to the output of the remaining amount detection circuit 10a, any value may be used as long as it can be compared with the output of the remaining amount detection circuit 10a.

Effects of the Invention As is clear from the above embodiments, the present invention is capable of detecting whether or not a memory is writable by comparing a write address and a read address, and outputting a writable signal. By managing this write enable signal in the system control section, it becomes possible to sufficiently realize the present invention even using a small capacity memory that is less than two tracks worth.

In addition, even if there is a track on which a very short compressed audio signal is recorded, this can be detected when writing to memory, so the compressed audio signal of the next track can be written in advance, and the audio signal can be played without interruption.

Furthermore, in the second embodiment, since the write enable signal is outputted a predetermined time before the end of reproduction of one track in all modes, it is possible to use the write enable signal as a time axis reference. It becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a compressed audio signal reproducing device according to a first embodiment of the present invention. FIGS. 2 and 3 are block diagrams of a compressed audio signal reproducing device according to a second embodiment of the present invention. , FIG. 5 is a block diagram showing an example of a conventional recording device of the same embodiment, FIG. 7 is a format diagram of the same conventional example, FIG. 8 is a block diagram showing an example of a video floppy audio reproducing device, and FIG. The figure shows 10...writable signal generation circuit for explaining the operation of the conventional example.
10a...remaining amount detection circuit, 10b...comparison circuit, 11...system control section, 32...
A/D converter, 33... memory, 34...
D/A converter, 40...video floppy 5
0... Playback head, 51... Head access section,
53... Reproduction signal processing circuit, 54... Write address control circuit, 55... Read address control circuit.

Claims (2)

[Claims] (1) A recording medium having a plurality of audio tracks in which a time-domain compressed audio signal is divided into a plurality of tracks and recorded thereon, a head for reproducing the time-domain compressed signal recorded on the track, and a head that plays the time-domain compressed signal recorded on the track; a head access unit that moves the head to an optimal position; a playback signal processing unit that receives the output signal of the head and performs signal processing; and receives the output signal of the playback signal processing unit as input and temporarily converts the time-axis compressed audio signal a memory unit for storing the time-base compressed audio signal; a write address control unit for controlling the memory unit to record the time-base compressed audio signal in the memory unit; and a write address control unit for decompressing the time-base compressed audio signal stored in the memory unit. a read address control section that controls the memory section so that the audio signal becomes a series of audio signals before division; and a read address control section that compares the outputs of the write address control section and the read address control section, and determines the time axis that has not been read out. a remaining amount detection circuit that detects the remaining amount of the compressed audio signal; and a comparison section that detects whether or not writing to the memory section is possible by comparing the output of the remaining amount detection circuit with a predetermined value and outputs a write enable signal. and inputting the writable signal, giving an access instruction to the head access unit to move the head to a desired position on the recording medium, and if the memory unit is writable, compressing the time axis. A compressed audio signal reproducing device comprising: a system control unit that gives a write instruction to the write address control unit to write the audio signal into the memory unit. (2) The compressed audio signal reproducing apparatus according to claim 1, wherein the predetermined value in the comparison section is changed depending on the speed at which the time-base compressed audio signal stored in the memory section is expanded and read out.