JPH03216869A - Aptip data interpolating circuit - Google Patents

Abstract

PURPOSE:To obtain continuous accurate interpolated ATIP (absolute time in pregroove) data by inputting the frame synchronism detection signal and the error check signal outputted from an ATIP data demodulating circuit to the clock terminal and the mode switching signal input terminal of a time counter. CONSTITUTION:A time counter 36 which has two operation modes, namely, the preset mode and the counter mode and has ATIP data as the input is provided on the output side of an ATIP demodulating circuit 18 which performs demodulation of ATIP data recorded on a disk, frame synchronous detection, and error check. The frame synchronous detection signal and the error check signal outputted from the ATIP data demodulating circuit 18 are inputted to the clock terminal and the mode switching signal input terminal of the time counter 36. Thus, accurate ATIP data is always obtained independently of drop-out of ATIP data outputted from the ATIP data demodulating circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an ATIP data interpolation circuit, and is particularly used to compensate for missing ATIP data recorded on, for example, a CD-WO (WRITE ONCB) disc. Concerning an ATIP data interpolation circuit that is suitable for [Prior Art] For example, a write-once type CD-WO disc that allows the user to record information on the disc only once has a spiral guide groove formed in advance. This guide groove is connected to AT I P (Ab
Solute Time In Pregroove)
Data (absolute time data) is 22. Recorded using FM modulation at a carrier frequency of 0.05kHz. ATIP
The data format, as shown in Figure 4, consists of a serial configuration of a 4-bit synchronization signal, 8-bit minute data, 8-bit second data, 8-bit frame data, and 14-bit CRC data. Of these, the minute data, second data, and frame data, which are absolute time data, are all composed of 2-digit BCD data, and the minute data is from 00 to 99, and the second data is from 00 to 5.
9, frame data takes values from 00 to 74. The 22.05kHz carrier is the CL of the spindle motor.
Used for vM control.

ATIP data is read out by an ATIP data demodulation circuit when recording user data, and is used to form time data in a subcode to be recorded together with user data. [Problem to be solved by the invention] However, with the above-mentioned conventional technology, for example, CD-W
Recovering ATOP data due to scratches on O disk etc.
When the ATIP data output from N is temporarily lost, it becomes impossible to form accurate subcodes, which causes the problem that, for example, when searching for user data, it becomes impossible to perform an accurate search. This invention was made in view of the above-mentioned conventional problems.
It is an object of the present invention to provide an ATIP data interpolation circuit that can always obtain accurate ATIP data regardless of the lack of ATIP data output from an AT[P data demodulation circuit.

[Means to solve the problem]

The ATIP data interpolation circuit of the present invention has two operation modes, a pre-theft mode and a counter mode, on the output side of the ATIP data demodulation circuit that performs demodulation of ATIP data recorded on a disk, frame synchronization detection, and error checking. A time counter is provided to input ATIP data, and a frame synchronization detection signal and an error check signal output from the ATIP data demodulation circuit are input to a clock terminal and a mode switching signal input terminal of the time counter. There is. [Example] Next, one example of this invention will be explained with reference to FIG. FIG. 1 is a block diagram showing an ATIP data demodulation system of a CD-WO disc recording and reproducing apparatus according to the present invention.

An RF amplifier 1l is connected to the output side of the optical pickup 10, and this RF amplifier 11 generates a tracking error signal. An amplifier l2 is connected to the tracking error signal output terminal of the RF amplifier l1, and the tracking error signal is amplified. BPF14 is connected to the output side of amplifier 12, and F
M modulated wave components are extracted. An FM demodulation circuit 16 is connected to the output side of the BPF 14, and performs FM demodulation on the FM modulated wave component to create a biphase signal. An ATIP data demodulation circuit l8 is connected to the output side of the FM demodulation circuit l6, and the ATI
P data (absolute time data consisting of minutes, seconds, and frames)
is demodulated. The ATIP data demodulation circuit 18 also performs frame synchronization detection and error check (CRC check), and outputs a frame synchronization detection signal and an error check signal (CRC check signal).
Output.

The ATIP data demodulation circuit 18 includes a pie-phase demodulation circuit 20, serial-to-parallel conversion circuits 22-26, latch circuits 28-32, and an AND circuit 34. The biphase demodulation circuit 20 is connected to the output side of the FM demodulation circuit 16, and performs demodulation of ATIP serial data from the biphase signal, frame synchronization detection, and CR.
Perform error checking using C data. The biphase demodulation circuit 20 outputs ATIP serial data, a data read clock, a frame synchronization detection signal, and an error check signal. The error check signal is
When the minute data, second data, and frame data for one frame are all correct, it indicates an OK state.If there is an error in any of the IJ level, minute data, second data, or frame data, the "L" level indicates an error state. Output. Here, the relationship between the ATIP serial data, frame synchronization detection signal, data read clock, and error check signal is shown in the time chart of FIG. The frame synchronization detection signal is output at the time when the last bit of the frame synchronization signal in the ATOP serial data is output. The data read clock is output during the output of minute data, second data, and frame data in ATMP serial data.

The error check signal is C in the ATIP real data.
When the last bit of RC data has been output, it is output as an error check result, and the next frame's CR
This continues until the output of the last bit of C data ends. On the output side of the ATIP serial data of the high-phase demodulation circuit 20, there are 8-bit soria-to-parallel converters 2 each.
2 to 26 are connected in series, and ATIP norial data is serially inputted according to the data reading clock and outputted in parallel in 8-bit units. Latch circuits 28-32 are connected to the output side of each serial-parallel converter 22-26, respectively. The frame synchronization detection signal and error check signal output from the high phase demodulation circuit 20 are input to an AND circuit 34, and the output of this AND circuit 34 is input as a rough strobe signal to each latch circuit 28 to 32. .

When the frame synchronization detection signal is input while the error check signal is at "H" level (ATIP data for the previous frame is correct), a latch strobe signal is output from the AND circuit 34, and the current serial-parallel The outputs of the converters 22-26 are latched by respective latch circuits 28-32 and output as ATIP data. The output of the launch circuit 32 is minute data, the output of the latch circuit 30 is second data, and the output of the latch circuit 28 is frame data. The ATtP data demodulation circuit 18 configured in this manner has a
A time counter 36 forming a TIP data interpolation circuit is connected. The time counter 36 includes a 75-decimal BCD counter 38 whose output side of the latch circuit 28 is connected to the briset data input terminal, a sexagenary BCD counter 40 whose output side of the latch circuit 30 is connected to the briset data input terminal, and a latch circuit. It consists of a 100-decimal BCD counter 42 whose output side is connected to a brisset data input terminal, and a 75-decimal B
The carry signal output terminal of the CD counter 38 is sexagesimal BCD.
Connected to the clock input terminal of the counter 40, sexagesimal B
The carry signal output terminal of the CD counter 40 is decimal BC.
It is connected to the clock input terminal of the D counter 42. The frame synchronization detection signal outputted from the biphase demodulation circuit 20 is input to the clock input terminal of the 75-decimal BCD counter 38 as the clock input terminal of the time counter 36, and the 75-decimal BCD counter 38 and the 60-decimal B
An error check signal is input to the mode switching signal input terminals of the CD counter 40 and the decimal BCD counter 42.

Each 75-decimal BCD counter 38, sexagesimal BCD counter 4
The 0, 100-decimal BCD counter 42 has two operating modes: a preset mode and a count mode, and when the [H] level is input to the mode switching signal input terminal, it enters the preset mode, and each latch circuit 28 ~32
Presets the 8-bit data input from and outputs it as is. On the other hand, when the "YES" level is input to the mode switching signal input terminal, the count is increased from the preset value at that point every time a rising edge of the pulse is input to the clock input terminal. Decimal BCD counter 42, sexagesimal counter 40, 7
The output of the quinary counter 38 is interpolated ATIP data, which is output to a system microcomputer or the like. The output of the decimal BCD counter 42 is minute data, the sexagesimal counter 40 is second data, and the output of the 75-decimal counter 38 is frame data.

Next, the operation of this embodiment will be explained with reference to the time charts of FIGS. 2 and 3. First, we will discuss the case where the CD-WO disc has no scratches and the ATIP data is demodulated normally (see Figure 2).
．． When recording user data, a detection signal from the optical pickup 10 is input to the RF amplifier 11, and a tracking error signal is output. This tracking error signal is Ambly l2
After being amplified by , the FM modulated wave component is extracted by BPFl4. The FM modulated wave component is demodulated into a biphase signal by an FM demodulation circuit 16. The biphase signal is input to the ATIP data demodulation circuit l8, and the ATIP data is demodulated. In this ATIP data demodulation circuit 18, first, a biphase demodulation circuit 20 performs demodulation of ATIP serial data, frame synchronization detection, and error checking. The ATIP serial data is sent to the biphase demodulation circuit 20.
According to the data read clock output from the 8-bit data read clock, the data is sequentially transferred to serial-to-parallel conversion circuits 22, 24, and 26, and serial-to-parallel conversion is performed in 8-bit units. When the bi-phase demodulation circuit 20 finishes outputting the frame data, the serial-to-parallel conversion circuit 26 outputs the minute data,
Second data is output from the serial-to-parallel conversion circuit 24, and frame data is output from the serial-to-parallel conversion circuit 22. The outputs of the serial-to-parallel conversion circuits 26, 24, and 22 are output to latch circuits 32, 30, and 28, respectively. When the output of the CRC data from the bi-phase demodulation circuit 20 is finished, if the minute data, second data, and frame data for one frame are all correct, the rH level error check signal, which indicates an OK state, becomes bi-phase. The data is output from the recovery circuit 20 to the AND circuit 34. In this state, when a frame synchronization detection signal for the next frame is output from the biphase demodulation circuit 20 to the AND circuit 34, a latch strobe signal is output from the AND circuit 34 to the latch circuits 32, 30, and 28. At this time, the latch circuits 32, 30, and 28 output the minute data, second data, and frame data inputted from the serial-parallel conversion circuits 26, 24, and 22, respectively. These ATIP data are correct data and are input to each of the decimal BCD counter 42, the sexagesimal counter 40, and the 75-decimal BCD counter 38 of the time counter 36. Each decimal BCD counter 42, 6 of the time counter 36
Since the "H" level error check signal is input to the mode switching signal input terminals of the 0-base counter 40 and the 75-base BCD counter 38, the mode is set to the preset mode.
The minute data, second data, and frame data input from the latch circuits 32, 30, and 28 are output as interpolated ATIP data. This interpolated ATIP data is correct data and is output to the system microcomputer, etc. After outputting a frame synchronization detection signal, the pie-phase demodulation circuit 20 serially outputs minute data, second data, and frame data related to a new frame. These data are transferred to the serial-to-parallel conversion circuits 26, 24, and 22 and subjected to serial-to-parallel conversion in the same manner as described above. When each data is correct, the biphasic demodulation circuit 20 outputs an error check signal when it finishes outputting the CRC data.
Therefore, when the next frame synchronization detection signal is output, it is latched by the latch circuits 32, 30, and 28.
The output data to the time counter 36 changes. Since the time counter 36 remains in the reset mode, the changed ATIP data is used as is for correct interpolation ATI.
It is output as P data.

Hereafter, in the same way, the CD-WO disc has no scratches and the AT
When the ATIP data output from the IP data demodulation circuit 18 is correct, the time counter 36 is maintained in the reset mode state and the correct ATIP data is directly interpolated A.
It is output as TIP data to the system micro combinator. In contrast to this, a case will be explained in which an error occurs in either the minute data, second data, or frame data when demodulating the ATIP data of a certain frame due to a scratch on the CD-WO disc (see Figure 3). At this time, when the biphase demodulation circuit 20 finishes outputting the CRC data, it drops the error check signal from rH, to r(-, which indicates an error state).

Therefore, even if the frame synchronization detection signal for the next frame is output from the biphasic demodulation circuit 20, the latch circuits 32, 30, and 28 do not perform a latch operation and continue outputting the ATIP data for the previous frame. ．． Therefore, ATIP data will be lost.

On the other hand, in the time counter 36, when the error check signal input to the mode switching signal input terminal falls from rHj to "LJ," the latch circuit 32, 3o, 28 to preset 7} The minute data, second data, and frame data input to the data input terminal are used as preset values to switch to count mode,
After that, the clock input terminal of the time counter 36 (75 base B
When the next frame same jiJl detection signal is input to the clock input terminal of the CD counter 38, the 75-decimal BCD
The counter 38 increments by one frame. At this time, if the preset data of the 75-decimal BCD counter 38 is 74, it becomes 00, and the carry signal is set to 60.
Output to the clock input terminal of the advance BCD counter 40 and increment the second data by one second. Similarly, at this time, if the preset data of the sexagesimal BCD counter 40 is 59 in advance, it becomes OO, a carry signal is output to the clock input terminal of the decimal BCD counter 42, and the minute data is incremented by one minute. Let. Therefore, A output from the ATIP data demodulation circuit 20
Even if the TIP data is not updated due to an error and is missing, the output of the time counter 36 is updated in synchronization with the frame, so accurate interpolated ATIP data can continue to be output to the system microcomputer. After outputting a frame synchronization detection signal, the biphase demodulation circuit 20 serially outputs minute data, second data, and frame data related to a new frame. These data are sent to the serial-to-parallel converter circuits 26 and 24 as described above.
, 22 for serial-to-parallel conversion. Bi-phase demodulation circuit 2 when the error condition continues
0, the error check signal remains rL after outputting the CRC data, so even when the next frame synchronization detection signal is output, each latch circuit 32, 30,
The ruff data of No. 28 does not change.

At this time, the time counter 36 remains in the count mode, so when the next frame synchronization detection signal is input, the interpolated ATIP data is incremented by one frame for interpolation.

In the same way, if the CD-WO disc is scratched, etc., the AT
When the ATIP data output from the IP data demodulation circuit is in an error state, the time counter 36 is maintained in the count mode state and correct interpolated AT formed by interpolation is performed.
IP data is output to the system microcomputer.

After that, when the minute data, second data, and frame data become normal when demodulating the ATIP data of a certain frame, CR
After outputting the C data, the error check signal changes from "L" to rH.

At this time, when the frame synchronization detection signal is outputted subsequently, the correct data outputted from the parallel to parallel conversion circuits 26, 24, 22 is detected by the relay circuits 32, 30.
, 28, and output to the time counter 36 as ATIP data. The time counter 36 returns to the preset mode when the error change signal becomes "H", and the correct A is output from the latch circuits 32, 30, and 28.
Outputs TIP data as is to the system microcomputer as interpolated ATIP data. According to this embodiment, the time counter 36 is provided on the ATIP data output side of the ATIP data demodulation circuit 18, and the frame synchronization detection signal and error check signal output from the ATIP data demodulation circuit 18 are input to the clock input terminal of the time counter 36. is input to the mode switching signal input terminal, and when the error check signal is in the OK state, the time counter 36 enters the recent mode and outputs the correct ATIP data output from the ATIP data demodulation circuit 18 as is as interpolated ATIP data. , when the error check signal enters an error state, the time counter 36 detects the ATIP input at that time.
By using data as a preset value and performing interpolation by stepping in accordance with the input of the frame synchronization detection signal, CD
- Even if an error occurs in the ATIP data output from the ATIP data demodulation circuit 18 due to scratches on the WO disk, it is possible to output continuous correct interpolated ATIP data, and it is possible to output continuous correct interpolated ATIP data when recording user data. A.T.
Correct subcodes can be recorded based on IP data. [Effects of the Invention] According to the ATIP data interpolation circuit of this invention, the ATIP
By providing a time counter on the ATIP data output side of the data demodulation circuit and inputting the frame synchronization detection signal and error check signal output from the ATIP data demodulation circuit to the clock terminal and mode switching signal input terminal of the time counter, CD -ATIP due to scratches on WO disk, etc.
Continuous and accurate interpolated ATIP data can be obtained regardless of temporary loss of ATIP data output from the data demodulation circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an ATIP data reproducing system of a CDWO disk recording/reproducing apparatus according to one embodiment of the present invention, FIGS. 2 and 3 are time charts showing the operation of FIG. 1, and FIG. is an explanatory diagram showing the format structure of ATIP data. Explanation of main symbols 18: ATIP data demodulation circuit, 36 two-hour counter.

Claims (1)

[Claims] The output side of the ATIP data demodulation circuit, which performs demodulation of ATIP data recorded on a disk, frame synchronization detection, and error checking, has two operating modes, a preset mode and a counter mode. An ATIP data interpolation circuit comprising: a time counter for input; and a frame synchronization detection signal and an error check signal output from the ATIP data demodulation circuit are input to a clock terminal and a mode switching signal input terminal of the time counter.