JPH03216891A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To eliminate a need of a special external terminal and to prevent the damage of the effective area of a memory by activating a status register write signal generating circuit until supply of a first memory write indicating signal. CONSTITUTION:A power-on detector 20 detects application of the supply voltage of a semiconductor storage device to activate a status register write control circuit 30. When the input of address A0 to Ai designates a specific address during this period of activation, a status register write signal generating circuit 40 generates a write signal to write information which is given to a data input terminal Din at this time, in a status register 50. In this manner, status information supplied from the data input terminal is written in the status register until the specific address is designated before supply of the first memory write signal after power-on. Thus, a special external terminal is not required, and the specific address on the memory is used to prevent the damage of the effective area of the memory.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor memory device having multiple operation modes, in order to set the operation mode of the memory, a special external terminal -T is required, and the effective area of the memory is not damaged. In a semiconductor memory device that has a status register for setting the memory operation mode selection, the power-on detector detects power-on, and the address input is compared with a specific address and operates when a match is found. A status register write signal generation circuit that instructs writing of mode information, and a status register write signal generation circuit that activates the status register write signal generation circuit after the power is turned on until the first memory write instruction signal is supplied. write and hold the operating mode information supplied from the data input terminal of the memory in response to the write instruction signal from the status register write signal generation circuit, or write the status register. The operation mode information supplied as part of the memory address is written and held in the status register by the write instruction signal from the signal generation circuit, or the first memory write instruction signal is supplied after power is turned on. and an output control circuit that puts an output buffer circuit provided at the data input/output terminal of the memory in a high impedance state until the data input/output terminal of the memory is controlled by a write instruction signal from the status register write signal generation circuit. The configuration is such that the operation mode information supplied from the terminal is written and held in the status register.

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having multiple operation modes.

As user needs have diversified in recent years, memory devices have been required to have multiple functions. In response to this request,
A method is often used in which one memory device has a plurality of operation modes, and a user selects and uses a desired one of the operation modes. For example, there are memories that have a built-in validation function in order to increase the reliability of the operation of the memory device. In this case, one bit is required for parity in addition to the required pit width, but some systems do not require that much reliability and would rather use this parity.
You may also request that bits be used for data.
Whether or not to use the parity function is specified by the operation mode.

[Conventional technology]

In this way, when attempting to respond to a plurality of requests using one memory fc, there are the following methods that can be adopted.

The first method is to provide a mode selection input terminal and select one of a plurality of operation modes depending on the application level of the input terminal. However, this method has the disadvantage that the number of input terminals increases and the package becomes larger.

The second method is to select a predetermined operating mode by providing a status register within the chip and setting the status register to a desired state. A first example of such prior art is shown in FIG. In the same figure,
110 is a memory, 120 is a status register, 13
0 is the operating mode! lJIl] circuit. memory 71
0 is address human power A0~Ai, write IIJw input WE,
They each have write data input [)in and data output oout, and perform memory operations. Status register 120 is register write υ1111 manual WEsr, data manual Q
The status data stored in response to each input of in is stored. The operation mode determination 111 circuit 13G is supplied with status data and operates the memory in an operation mode corresponding to the status data.

The operation of this first conventional example is shown in FIG. In the figure, at time point (3), WESr becomes L level, and the information [)sr of the data input Din at that time is written to the status register and held. Operation mode II! 1 circuit 130 is connected to this S
Upon receiving the R output, the memory 110 is operated in a desired mode. Writing to the memory is performed by setting the memory-dedicated write control 11F input WE to the L level.

Time point ■ indicates this. In this first conventional example, although the write data input to the status register 130 is shared with the memory, the write power must be provided separately from the memory, so an increase in the number of terminals can still be avoided. do not have.

FIG. 12 shows a second conventional example improved from this, in which the memory 210. Address detector 220, status register 240. It consists of an operation mode III1 circuit 250 and a 7th mode circuit 230. What about address detector 220? A specific address (for example, address X) where the dress manpower is determined in advance
When selected, it is detected and a detection signal AM is output. In this state, write to memory ilJII1 input W
When the EJFrL level is set, the output W of the AND circuit 230
Sr becomes H level, and the information of D1n at that time is written into the status register. Operating mode III11
Circuit 250 correspondingly operates the memory in a predetermined operating mode. The operation of this second conventional example is shown in FIG. At point ■, the address selects address X, and W
When the E pulse is applied, the information Dsr of D1n at that time is written to the status register and held. At point ■, x ajI! Although writing is being performed to the memory outside Ia, at this time, writing to the status register 240 is not performed, and the state of the status register 240 is maintained as is.

[Problem to be solved by the invention]

In the second conventional example, the end fJF! is used for writing Mw of the status register. : No need to provide. However, poetry point■
As shown in FIG. 2, when an attempt is made to perform polishing on address X of the memory 210, the state of the status register 240 also changes, which is an inconvenience. That is, in this method, address X of the memory 210 used to determine whether to write to the status register 240 is
The problem is that it cannot be used inside.

The present invention was made in view of the above points, and does not require a special external terminal to set the operation mode of the memory.
It is an object of the present invention to provide a semiconductor memory device that does not damage the available 9h area of a memory.

[Means for solving R problem]

The semiconductor memory device of the present invention has a status register for setting selection of a memory operation mode, and includes a power-on detector for detecting power-on, and a power-on detector for detecting power-on, and a power-on detector for detecting power-on, and a power-on detector for detecting power-on, and comparing an address input with a specific address to find a match. A status register write signal generation circuit that instructs the writing of operation mode information when the power is turned on, and a status register write signal generation circuit that activates the status register write signal generation circuit after the power is turned on until the first memory write instruction signal is supplied. and a write control circuit, which writes and holds the operation mode information supplied from the data input terminal of the memory in the status register in response to a write instruction signal from the status register write signal generation circuit.

Further, the assistant operation mode information supplied as part of the memory address by a write instruction signal from the status register write signal generation circuit is written and held in the status register.

Furthermore, it has an output control circuit that puts the output buffer circuit provided at the data input/output terminal of the memory in a high impedance state after the power is turned on until the first memory write instruction signal is supplied, and the output control circuit maintains a high impedance state. The operation mode information supplied from the data input/output terminal of the memory is written and held in the status register in response to a write instruction signal from the write signal generation circuit.

[Effect]

In the present invention, the status information supplied from the data input terminal when a specific address is specified by the address is written to the status register after the power is turned on and before the first memory write instruction signal is supplied. No special external terminal is required, and specific addresses on the memory can be used without damaging the effective area of the memory.

Further, by supplying status information as part of the address, bus fights between data input/output H terminals can be prevented from occurring.

Furthermore, even in a configuration in which status information is supplied from the data input/output terminal by putting the output buffer 7 circuit in a high impedance state until the first memory write instruction signal is supplied after the power is turned on, the bus of the data input/output terminal Fights can be prevented from occurring.

〔Example〕

FIG. 1 shows a block diagram of a first embodiment of the invention.

In the figure, the semiconductor storage device includes a memory 10, a power-on detector 20, a status register agricultural control circuit 30, a status register write signal generation circuit 40, a status register 50, and an operation mode determination circuit 60. It consists of The power-on detector 20 is a tal of a semiconductor storage device.
! The status register write t, 111111 circuit 30 is activated upon detecting that the pressure is applied. During this active period, when the address Ao to A+ input specifies a specific address (for example, address X), the status register write signal generation circuit 40 generates a write signal, and at that point the data
? The information given to Din is written to the status register 50. As a result, the operation mode iIIJIID circuit 60 sets the memory 10 to the specified operation mode.

When the first write power WE is applied to the memory and the memory starts operating, the status register write power 30 to which this "WT" signal is input is deactivated, and from then on the address is set to address X. Even if you specify status register 50
No writing is done.

FIG. 2 shows a circuit diagram of Yoro of FIG. 1. The power-on detector 20 integrates the application of the power supply voltage VCC using a resistor 21 and a capacitor 22, and the waveform is shaped and delayed by inverters 24 and 25 so that the voltage gradually rises upon power-on as shown in FIG. 3(A). The rising edge of the integral waveform Vc shown in B) is detected to generate the H level detection signal CL shown in FIG.

A FET (field effect transistor) 23 is used to discharge the capacitor 22 when the power is cut off.

This detection signal CL is the status register write control circuit 3.
0 to the NAND circuit 32 having a 7-rip, 7-lob configuration, which resets the flip-flop and generates a status register write signal.The L level WC signal shown in FIG. supply The status register write mm circuit 30 holds the WC signal at the L level until the NAND circuit 31 is first supplied with the L level WE signal (FIG. 3 (D)).

The status register write signal generation circuit 40 uses the exclusive number 7 circuits 41 to 42 to convert each bit Ao to Ai of the address shown in FIG.
The AND circuit 43 is supplied with this NOR circuit output, and when all the bits match, the third AND circuit 43 becomes H level.
The AM signal shown in Figure (G) is output. The AM signal is supplied directly to the NAND circuit 45 via the delay inverter 44, where the φW signal shown in FIG. 3(H) is generated and supplied to the NOR circuit 46. In the NOR circuit 46, the WC signal is L.
The above-mentioned φW signal is passed only when the level is the WSR signal shown in FIG. 3(I), and the status register 50
Nantes circuits 52 and 53 respectively.

The status register 50 is a NAND circuit 52.53.54
．． 55, the input signal of the data input terminal Qin shown in FIG. When the signal WSR$ from the status register write signal generation circuit 40 is at the H level, the information [)sr supplied from the data input terminal Din is latched, and the signals SR,
It is supplied to the operation mode till section circuit 60 as SR.

As a result, when the specific address X is designated by the address after the power is turned on at time point (3) in FIG. 3, the information Dsr is written and held in the status register 50 accordingly. When the first write to the memory 10 is performed at time point ■ and the status register write control circuit 30 is deactivated, the status register 50 will not be rewritten even if the address specifies address X at time point ■. , address X of memory 10 is accessed.

By the way, some memories share a data input terminal and a data output terminal with the aim of reducing the number of terminals, and have them as data input/output Yasuko I/O.

Such a memory uses the data input/output terminal I/O as data input when writing, that is, when WE is at L level, and at other times, that is, when WE is at H level, data input/output @i? Use r/0 as data output. Therefore,
In such a data input/output shared type memory, in the first embodiment, when WE attempts to write to the status register when reading at H level, the data input/output terminal ■
If a strong input level is applied to /○, it will compete with the data output being read at that time, causing a so-called bus fight. That is, in the case of such a data input/output shared memory, the information given to the data input/output gate l/0 cannot be written to the status register. The following second and third embodiments solve this problem.

FIG. 4 is a block diagram of the second embodiment of the present invention, 5Fj!
J shows the circuit diagram of Kairo. In the station map, Figures 1 and 2
Components that are the same as those in the figures are given the same reference numerals, and their explanations will be omitted.

The memory 15 shown in FIG. 4 inputs and outputs data from a data input/output terminal I/O, and is designated by addresses A0 to An. In this case, the exclusive NOR circuits 41 to 42 of the status 9 register write signal generation circuit 40
are supplied with part of the address Ao to Ai, and the other part of the address Aj-An is supplied to the NAND circuits 52 and 53 of the status register 50, respectively. In this example,
The I1 input detector 20 detects that a power supply voltage is applied to the semiconductor memory device and activates the status register input-11 circuit 30. During this active vIg question, some of the 7 dress inputs (eg A. ~Ai> specifies a specific address (X), the status register write signal generation circuit 40
A write signal is generated, and information given to other part of the address inputs (W4, eg, Aj to An) at that time is written into the status register 50. By this, the operation mode $1
11111 circuit 60 sets memory 15 to a specified operating mode. First write tl1m input WE is memory 1
5 and the memory 15 starts operating, this W
Status register write control circuit 3 to which E signal is input
0 is deactivated, and no writing to the status register 50 will be performed even if the address specifies address X thereafter.

The operating waveform diagrams of each part of the circuit in FIG. 5 shown in FIGS. 6(A) to (K) are almost the same as those in FIG. The difference is that Qsr is provided.

When the information [)sr is held in the status register 50 at time point ■ shown in FIG. Also status register 50 is a! ! i! There is no change, and address X in memory 15 is accessed.

That is, in this embodiment, bus fights are prevented by supplying the information [)sr to be set in the status register 50 from the other part of the address Aj-An.

FIG. 7 is a block diagram of a third embodiment of the present invention, and FIG. 8 is a circuit diagram of the main part thereof. In the same figure, the same reference numerals are attached to the same parts as in FIGS. 1 and 2, and the explanation thereof will be omitted.

The input terminal Din of the memory 10 shown in FIG. Connected to the input/output terminal I/O, the output terminal ■ou of the memory 10
t is the data input/output terminal through the output buffer 7 circuit 80.
/O is connected.

The power-on detector 20 detects that a power supply voltage is applied to the semiconductor memory device, activates the status register write control (b) path 30, resets the output control circuit 70, and outputs the output buffer 7. The circuit 80 is set to a high impedance state, and the data input/output terminal 1/0 is set to a state where the level can be set to a strong III level from the outside. After this, when the address input (Ao to A1) specifies a specific address (X), the status register write signal generation circuit 40 generates a write signal and applies it to the data input/output terminal I/O at that point. Writes the information to the status register.

As a result, the operation mode control circuit 60 sets the memory to the specified operation mode. When the first dust tllJw manual WE is applied to the memory and the memory 10 starts operating, the status register write IIlIII1 circuit 30 to which this WE signal is input is deactivated, and from now on, the address specifies address X. However, no writing is performed to the status register 50. Further, the WE signal sets the output IIJw1 circuit 70 at the time of broadcasting, and thereafter the activation and deactivation of the output buffer 7 circuit 80 is sub-Wed based on the state of the WE signal.

As shown in FIG. 8, the output control path 70 is composed of NAND circuits 71, 72 with a flip-flop configuration and an AND circuit 73, as shown in FIG. 9(A). At the rising edge of the electrical phenomenon Vcc and signal Vc shown in (8), the power-on detector 20 detects the electrical phenomenon shown in FIG.
) is supplied to the NAND circuit 72, the flip-flop Otub is reset as shown in (E) of the same figure.

Thereafter, when the L-level WE signal is supplied to the Nantes circuit 71, the flip-flop is set, and the double-AND circuit 73 outputs the WE signal as the OE signal shown in FIG. 9(F) to the buffer 7 circuit 80. and the AND circuits 81 and 82, respectively.

The output Bano 7 circuit 80 is supplied with the data output signal [)out and its inverted signal [)out of the memory 10 to the AND circuits 81 and 82, respectively, and the outputs of the AND circuits 81 and 82 are supplied to the N-channel FETs 83 and 84, respectively. The drains of FETs 83 and 84 are commonly connected to the data input/output terminal I/O. OF signal H
At the level, FET83.84 outputs the data output signal Qout.
A signal with a level corresponding to the level of the data input/output terminal I/
output from FET 83, 8 when the OE signal is at L level.
4 are both cut off to put the data input/output terminal I/O in a high impedance state (Fig. 9 (G)). When the power is turned on at time ■ shown in No. 9 @, the data input/output terminal I/O becomes a high impedance state, and by the time ■ when the L level WE signal first arrives, the data input/output terminal I/O When the information [)Sr comes in, this is the status register 5.
Written to 0. After this, the data input/output terminal I/O is W.
It is used for reading from the memory 10 when the E signal is at H level, and for writing to the memory 10 when it is at L level.

In other words, in this embodiment, the output IIJII11 circuit 70 forces the data input/output terminal ■/0 to high impedance until the WE signal is input after the power is turned on, that is, until the memory 10 is written, to prevent the occurrence of a bus shift. are doing.

〔Effect of the invention〕

As described above, the semiconductor memory device of the present invention does not require a special external terminal to set the operation mode of the memory, does not damage the effective area of the memory, and also allows data input/output of the memory. This is extremely useful in practice since it can prevent bus fights from occurring at the terminals.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the first embodiment of the device of the present invention, FIG. 2 is a circuit diagram of the main parts of FIG. 1, FIG. 3 is a signal waveform diagram of each part of the circuit in the circuit diagram of FIG. 2, and FIG. Figure 5 is a block diagram of the second embodiment of the device of the present invention, Figure 5 is a circuit diagram of the main parts of Figure 4, Figure 6 is a signal waveform diagram of each part of the circuit in Figure 5, and Figure 7 is the device of the present invention. FIG. 8 is a circuit diagram of the main part of FIG. 7, FIG. 9 is a signal waveform diagram of each part of the circuit of FIG. 8, and FIGS. 10 and 12 are the conventional device. Block diagrams of each example, Fig. 11, Fig. 13Fj! J are signal waveform diagrams of FIGS. 10 and 12, respectively. In the figure, 10 is a memory, 204.2 power-on detector, 30 is a status register write control circuit, 40 is a status register write signal generation circuit, 50 is a status register, 60 is an operation mode iIIJI11 circuit, and 70 is a output! 1
11@path, 80 indicates an output buffer circuit. The 1st thrust force j07゜ from this Q June Higa's lock diagram Figure 1 Figure 1 mouthpiece diagram of the IP section Figure 2 i2 [! lf7ltl4W fi;tl [a Figure 6 Book J Chuming Table 1 Second Calamity 7! Ij's 70ヮfu map 4th figure 15! The mouth of the enemy and evil in A4 dark blue Hj Figure 5 TS8 Figure l path each evil beginning 413 dark form Figure 9 Color ξ rice. Capturing and overturning 'lA1 Iyen 7゜mouth/riff diagram Figure 10 'lF310 figure Φmouth'I6-Each evil service number J type diagram Figure 11

Claims (4)

[Claims] (1) In a semiconductor storage device having a status register (50) for setting the selection of the operation mode of the memory (10), a power-on detector (20) detects power-on and compares an address input with a specific address. a status register write signal generation circuit (40) which instructs writing of operation mode information when the signals match; Generation circuit (40
) activates the status register write control circuit (30
), and the operation mode information supplied from the data input terminal of the memory (10) is transmitted to the status register (
50) A semiconductor memory device characterized in that data is written and held in the memory. (2) In a semiconductor storage device having a status register (50) for setting the selection of the operation mode of the memory (10), a power-on detector (20) detects power-on and compares an address input with a specific address. a status register write signal generation circuit (40) which instructs writing of operation mode information when the signals match; Generation circuit (40
) activates the status register write control circuit (30
), writes and holds the operation mode information supplied as part of the address of the memory (10) in the status register (50) by the write instruction signal from the status register write signal generation circuit (40). A semiconductor memory device characterized by: (3) In a semiconductor storage device having a status register (50) for setting the selection of the operation mode of the memory (10), a power-on detector (20) detects power-on and compares an address input with a specific address. a status register write signal generation circuit (40) which instructs writing of operation mode information when the signals match; Generation circuit (40
) activates the status register write control circuit (30
), and an output control circuit (70) that puts the output buffer circuit (80) provided at the data input/output terminal of the memory in a high impedance state until the first memory write instruction signal is supplied after the power is turned on. and writes and holds the operating mode information supplied from the data input/output terminal of the memory (10) in the status register (50) in response to a write instruction signal from the status register write signal generation circuit (40). A semiconductor memory device characterized by: (4) Flip-flop circuits (71, 72) that are set by the output signal of the power-on detector (20) that detects power-on and reset by the first memory write signal after power-on. At least during the setting period of the flip-flop circuits (71, 72), the output buffer circuit (8) provided at the data input/output terminal of the memory
Output control circuit (7) that puts 0) in a high impedance state
0).