JPH03216892A - Semiconductor memory and semiconductor integrated circuits - Google Patents

Abstract

PURPOSE:To shorten the time of data write to a memory cell by cutting off the data line of the selected memory cell and a common read line at the time of writing data in the memory cell. CONSTITUTION:Data lines of memory cells of plural columns which are omitted in the figure are connected to a common read line 10 and a common write line 11 through read transfer gates 103(M3) and 104(M4) and write transfer gates 101(M1) and 102(M2). Consequently, read transfer gates 103(M3) and 104(M4) can be forcibly turned off by a write control signal the inverse of w, and data written in a pair of data lines D and the inverse of D is not propagated to the common read line 10 at the time of data write. That is, since the potential of the common read line is not changed by data write, the overall capacity charged to and discharged from a load is reduced at the time of write to shorten the write time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to control of writing data into memory cells thereof.

[Conventional technology] As a data read circuit and a data write circuit in a conventional semiconductor memory, I.S.S.
C.C., Digest of Technical Papers, pp. 186-187, 1988 (IS
SCC, Digest of Technical Pa
pers, PP. 1 8 6 - L 8 7, 1 9
The one discussed in 8) is known.

FIG. 7 shows a schematic diagram of a read circuit and a data write circuit in this conventional semiconductor memory.

In the figure, 1 is a data line load circuit, D and /D are data line pairs,
WL is a word line, 2 is a memory cell, 101 (Ml),
102 (M2) is a transfer gate for writing, M3 and M4 are transfer gates for reading, 3
1 is a two-man NOR gate that receives a column selection signal /Yi and a write control signal /W; 4 is a decoder circuit that generates an address Ao-An column selection signal /Yi; 1
o is a common read line for reading data from memory cells, and 11 is a common write line for writing data to memory cells. transfer gate 103 (M3). 104 (M4) and write transfer gates 101 (Ml), 102
(M2).

The operation of the semiconductor memory according to this prior art will be explained below.

The operation of reading data from a memory cell is performed using word I!
When WL rises, the data held in memory cell 2 is transferred to data line pair D. /D appears as a potential difference.

In this case, since it is a read cycle, the write control signal /W is High, and the power ram selection signal /Yi is selected, so it is Loti. Therefore, write transfer gates 101 (Ml), 102
(M2) is OFF, transfer gate 1 for readout
03 (M3). 104 (M4) is turned on, and the potential difference appearing on the data line pair D and /D is propagated to the common read line 1o and read out.

On the other hand, during the data write operation, the write control signal /W and the column selection signal /YE are both low, so the write transfer gate 101 (Ml
). 102 (M2) and a read transfer gate 103 (M3). 104 (M4) are all ON
becomes.

The data written to the common write line 11 is transferred to write transfer gates 101 (Ml) and 102 (M
2) to the data line pair D, /D, i! ! is written into the memory cell 2 of the selected word line WL.

Also, the written data is read from the data line through transfer gates 103 (M3) and 104 (M4).
) to the common readout 110.

As described above, reading and writing of the memory cell 2 has been realized in the conventional semiconductor memory.

[Problems to be Solved by the Invention] Since the semiconductor memory according to the prior art is configured as described above, the common read line is charged and discharged every time data is written to a memory cell.

However, charging and discharging the common read line, which has a heavy load because multiple columns are connected, every time data is written to a memory cell has the problem of increasing the time required for writing. Ta.

Also, when data writing to the memory cell is completed,
In order to prevent incorrect data from being written to a memory cell or a delay in read time immediately after writing, it is necessary to recover the data line from the write potential to the read potential. At the same time, the potential of the heavily loaded common readout line must also be recovered, which poses a problem of increasing the time required for recovery.

Increasing the capacity of semiconductor memories leads to an increase in the load on the common readout line, so this problem has become serious due to the recent demand for larger capacities and faster access of semiconductor memories.

It also goes against the demand for lower power consumption.

Therefore, an object of the present invention is to speed up the writing time of data to a memory cell in a semiconductor memory, and to
The purpose is to speed up data line recovery time.

[Means for Solving the Problems] To achieve the above object, the present invention provides a memory cell, a write line for writing data to the memory cell, a read line for reading data from the memory cell, and a memory cell. and a second electronic switch connected to the read line via a first electronic switch that is connected when reading data from the memory cell and shut off when writing data to the memory cell; a data line connected to the write line via an electronic switch; and a first line connecting the data line and the read line when writing data.
and means for shutting off an electronic switch.

In order to achieve the above object, the present invention also provides a memory cell, a write line for writing data to the memory cell, a read line for reading data from the memory cell, and a memory cell connected to the memory cell. The memory cell is connected to the read line via a first electronic switch that is connected when reading data from the cell and when writing data to the memory cell, and a second electronic switch that is cut off when writing data to the memory cell. and a data line connected to the write line via a third electronic switch connected when writing data to the write line.

In order to achieve the above-mentioned purpose, a memory cell array consisting of memory cells arranged in a matrix, an address decoder for selecting memory cells, a common write line for writing data to each memory cell, and a data set for each memory cell are provided. A common read line for reading data from the memory cell and a data line of the memory cell selected when reading data from the memory cell are connected to the common read line, and a data line of the memory cell selected when writing data to the memory cell is connected to the common read line. and means for connecting the arta line of a selected memory cell to the common write line when data is written to the memory cell. do.

Note that it is desirable that a semiconductor integrated circuit such as a one-chip CPU, a cache memory LSI, or another controller IC incorporate the first, second, or third semiconductor memory. Further, it is preferable that an information processing device such as a computer includes the first, second, or third semiconductor memory as its memory.

[Function] According to the first semiconductor memory according to the present invention, the first electronic switch connects the data line and the read line when reading data from the memory cell, and disconnects it when writing data to the memory cell. Further, the second electronic switch connects the data line and the write line when writing data to the memory cell.

Further, according to the second semiconductor memory according to the present invention, the first
The second electronic switch is connected when reading data from the memory cell and when writing data to the memory cell, and the second electronic switch is turned off when writing data to the memory cell. Therefore, the data line and the read line are connected when reading data from the memory cell. Further, the third electronic switch connects the data line and the write line when writing data to the memory cell.

Further, according to the third semiconductor memory according to the present invention, the data line of the memory cell selected when reading data from the memory cell is connected to the common read shoulder, and the data line of the memory cell selected when reading data from the memory cell is connected to the common read shoulder, The data line of the memory cell and the common reading line are cut off. Further, when writing data to a memory cell, the data line k of the selected memory cell is connected to the common write line.

As described above, according to the first, second, and third semiconductor memory layers 4, the data line and the common read line are cut off during data writing, so that the potential change of the two common write lines is caused by the heavy load common read line. It will not be carried by U to the line.

That is, the common read line, which has a heavy load, is disconnected from the data line during writing, and its potential does not change.

Therefore, during writing, the total capacity to be charged and discharged is reduced, so that the writing time can be increased. Also,
During recovery, since the potential of the common read line does not change, only the data line needs to be recovered, resulting in faster recovery time.

In addition, a semiconductor integrated circuit such as a one-chip CPU or a cache memory LSI incorporating the first, second or third semiconductor memory, or a computer or the like having the first, second or third semiconductor memory as its memory. The information processing device is
It is possible to access the memory at high speed, and therefore its performance can be improved.

(Left below) [Embodiment 1] A first embodiment of the semiconductor memory according to the present invention will be described below.

FIG. 1 shows the configuration of a read circuit and a data write circuit of a semiconductor memory according to the first embodiment.

In the figure, 1 is a data line load circuit, D and /D are data line pairs,
WL is a word line, 2 is a memory cell, 101 (Ml).
102 (M2) is a transfer gate for writing, 103 (M3). 104 (M4) is a transfer gate for reading, 3 is a two-man NOR gate inputting a column selection signal /Yi and a write control signal /W, and VCC is a power supply voltage.

In addition, in 105 (M5), the write control signal /W is Low.
Time 103 (M3). 104 Pull amplifier MOS that raises the gate voltage of (M4) to High level, 106
(M6) sets the column selection signal /Yi to 103 (M3) when the write control signal /W is Hjgh. 104 (M
4) is a decoder circuit that generates a column selection signal /Yi based on the address Ao-An; 10 is a common read line for reading data from memory cells; 11 is for writing data into memory cells; This is the common writing line. Common readout line 1o
On the common write line 1, data lines of memory cells in a plurality of different columns (not shown) are connected to read transfer gates 103 (M3), 104 (M4) and write transfer gates 101 (Ml) .
102 (M2).

The operation will be explained below.

In the operation of reading data from a memory cell, first, the data held in the memory cell 2 due to the rise of the word line WL appears as a potential difference on the data line pair D, /D.

In this case, the write control signal /W is High because it is a read cycle, and the input ram selection signal /Yi is Low because it is selected.

Therefore, the output of the two-man power NOR gate 3 becomes Low, and the write transfer gate 101 (Ml). 1
02 (M2) is turned OFF.

Also. Since transfer gate M6 is turned on, column selection signal /Y. 103 (M3). via transfer gate M6. 104 (M4), and is propagated to the readout transfer gate 103 (M3
). 104 (M4) is turned ON. The potential difference thus appearing on the data line pair D, /D is propagated to the common read line 10 and read out.

On the other hand, during a data write operation, both the write control signal /W and the column selection signal /YE are LOIll. As a result, the output of the two-man powered NOR gate 3 becomes H.
transfer gate 10 for writing.
1 (Ml) and 102 (M2) are turned on. Also,
Transfer gate 10 by write control signal /W
6 (M6) is OFF, Pluanop MOS 105 (
M5) is turned ON, and the read transfer gate 103 (M3) whose gate voltage is pulled up.
104 (M4) is turned OFF. Therefore, the data written to the common write line 11 is transferred to the write transfer gates 101 (Ml), 102 (M2
) to the data line pair D, /D, and the memory cell 2
written to.

As described above, according to the first embodiment, read transfer gate 103 (M3). 104 (M4) OFF
can be forcibly controlled by the write control signal /W, and when writing data, the data line pair D,
The data written to /D is not propagated to the common read line 10.

Therefore, the data written to the memory cell via the data line is not propagated to the common read line, which has a heavy load capacitance6.In other words, the potential of the common read line does not change due to data writing, so the charging This has the effect of reducing the total capacity of the load to be discharged and speeding up the writing time. In addition, during recovery to restore the data line, etc. from the potential immediately after writing to the potential that can be read, the potential of the common read line has not changed from the potential when reading data, so only the data line needs to be recovered. As a result, recovery time can be speeded up.

Next, a second example of the semiconductor memory according to this example will be explained.

FIG. 2 shows the configuration of a read circuit and a data write circuit of a semiconductor memory according to the first embodiment.

In the figure, the same parts as the semiconductor memory shown in the first embodiment (see FIG. 1) are denoted by the same reference numerals, and the explanation thereof will be omitted.

103 (M3). 104 (M4) is a first read transfer gate controlled by the column selection signal /Yi, 107 (M7). 108 (M8) is a second read transfer gate controlled by an inverted signal of the write control signal /W, and 5 is an inverter circuit that inverts and outputs the write control signal /W.

The operation will be explained below.

In the operation of reading data from a memory cell, data held in memory cell 2 is first transferred to data line pair D. /D appears as a potential difference.

In this case, the write control signal /W is High because it is a read cycle, and the column selection signal /Yi is Low because it is selected. Therefore, 2-person power is NO
The output of the R gate 3 becomes Lotg, and the write transfer gates }-101 (Ml) and 102 (M2) are turned OFF.

In addition, the first readout transfer gate 103
(M3), 104 (M4) is the column selection signal /Y
i is low, so it is turned on, and the second read transfer gates 107 (M7) 108 (M8) are turned on because the inverted signal of the write control signal /W is low.6 Therefore, the data line pair D, /D The potential difference appearing in the first readout transfer gate 101 (Ml)
．． 102 (M2) and second readout transfer gates 107 (M7) and 108 (M8), the signal is propagated to the common readout line 10 and read out.

On the other hand, during data write operation, the write control signal/
Both W and column selection signal /Yi are Low.

As a result, the output of the two-man powered NOR gate 3 becomes High.
, the inverted signal of the write control signal /W becomes High.

Therefore, write transfer gate 101
(Ml). 102 (M2) is ON, first read transfer gate 103 (M3), 104 (M
4) is also turned on, the second read transfer transformer '77-gates 107 (M7) and 108 (M8) are turned off, and the data written to the common write line 11 is transferred to the write transfer gate 101 (Ml). 102
(M2) to the data line pair D, /D, and is written into the memory cell 2.

That is, during writing, the second read transfer gate provided in series with the first read transfer gate 103 (M3) 104 (M4) can be forcibly turned off, and the data line pair D, /D Data written to the common read line 1o is not propagated to the common read line 1o.

As described above, according to the second embodiment, the first read transfer gate 103 (M3) 104 (M4) and the second read transfer gate 107 (M
7) , 108 (M8) are connected in series, the read delay time is longer than in the first embodiment.
With simpler control than in the first embodiment, it is possible to eliminate the propagation of data written into memory cells via the data line to the common read line, which has a heavy load capacitance, as in the first embodiment.

In other words, the potential of the common read line does not change due to data writing, so during writing,
This has the effect of reducing the total capacity of the load to be charged and discharged and speeding up the writing time. In addition, during recovery to restore the data line, etc. from the potential immediately after writing to a potential that can be read, the potential of the common read line has not changed from the potential when reading data, so only the data line needs to be recovered. This has the effect of speeding up recovery time.

Here, the overall configuration of a semiconductor memory using the read circuit and data write circuit according to the above embodiment is as follows.
An example in which the read circuit and data write circuit shown in the first embodiment are used will be explained.

FIG. 3 shows the overall configuration of the semiconductor memory according to this embodiment.

In the figure, A. is an X-system address signal, AY is a Y-system address signal, Dout is an output signal, Din is an input signal, /C
S is a chip select signal, /WE is a write enable signal, 101 is an X-system address buffer, 105 is a Y-system address buffer, 102 is an output buffer, 103 is an input buffer, 104 is a chip select signal /CS and a write enable signal. A control circuit that generates write control signals /Wl and /W2 from /WE, 106 a sense amplifier that amplifies the minute voltage read from the memory cell, 150 to 15m an X-system address buffer output 13
Decoder circuit for decoding 0, 160 to 16m are word line drivers, WLo to WLm are word lines, 115
is an inverter circuit that inverts the input buffer output, 116
, 117 is the input buffer output and write control signal /W2
118 and 119 are write drivers 170, 17n is a decoder circuit that decodes the Y-system address buffer output 131, 1 is a data line load circuit, DO, /Do=Dn, /Dn is a data line versus, 2
are memory cells, 1010 (Ml), 1020 (M2
) ~101n (Ml), 102n (M2) are write transfer gates, 1030 (M3)
, 1040 (M4)-103n (M3). 104n
(M4) is a readout transfer gate. 180～
18n is an inverter circuit that inverts and outputs the column selection signals /Yo to /Yn, VCC is the power supply voltage, 1050 (M5)
, 105n (M5) has a write control signal /Wl of Lo
When ti, read transfer gate 1030
(M3) 1040 (M4) - 103n
(M3) Pull-up MOS that raises the gate voltage of 104n (M4) to high level, 1060 (M6) ~
106n (M6) has write control signal /Wl High
h, transfer gates 1030 (M3), 104 for reading column selection signals /Yo to /Yn
0 (M4) ~103n (M3), 104n (M4
) transfer gate, CD(R), /CD
(R) is a common readout line pair, CD (W), / CD
(W) is a common write line pair.

The operation of the semiconductor memory will be described below with reference to FIG. 4, which shows transitions of input/output signals and internal signals of the semiconductor memory.

In a write cycle in which the /CS signal is LOTE and the /WE signal is LOυ, both write control signals /Wl and /W2 are LOW. Data input from the input buffer 103 is written to the common write line pair CD(W), /CD(W) by write drivers 118 and 119 via two-man NOR circuits 116 and 117.

Common write line pair C D (W), / C D (W)
The data written to is transferred to one memory cell selected by word lines WLo to WLn and column selection signals /Yo to /Yn through a write transfer gate.
1010 (Ml). 1
020 (M2) -101n (Ml
), 102n (M2). At this time, the read transfer gate 1030 (M3
) 1040 (M4) ~ 103n (M3) + 1
04n (M4) is a pull-up MOS 1050 (M5) whose gate voltage receives the write control signal /Wl.
) to 105n (M5), all of them are turned off, and no data is written to the common read line pair CD(R), /CD(R).

On the other hand, in a read cycle when the /CS signal is Low and the /WE signal is High, the write control signal /Wl
．． /W2 both become High.

That is, the column selection signals /Yo to /Yn are propagated to the gates of the read transfer gates via transfer gates 1060 (M6) to 106n (M6), and the common write line pairs CD (W) and /C D (W
) is forcibly set to High level.

Therefore, the data of one memory cell selected by the word line W L o = W L ra and the column selection signals /Yo to /Yn is transferred to the read transfer gate 1030 (M3). 1040 (M4)-1
03n (M3). 104n (M4) to the common read lines CD(R), /CD(R), and is amplified by the sense amplifier 106 and output.

In this case, write transfer gate 1010
(Ml). 1020 (M2) ~101n (Ml).
l02n (M2) is completely O because there is no bias voltage between the gate and source to turn on the NMOS.
Becomes FF.

Next, an example of the configuration of the data line load circuit 1 is shown in FIG.

In the figure, vCC is the power supply voltage, GND is the ground potential, and 501-
504 is PMOSFET. W3 is a write control signal, D
, /D are data line pairs.

In the data line load circuit, in the read cycle, the write control signal W3 becomes LO- level, and the PM
OSFETs 501, 502 and 503, 504
All ONL data line pairs D and /D are strongly pulled up.

In addition, in the write cycle, the write control signal W3 becomes High level and the PMOSFET 50
3, 504 is turned off.

Therefore, the data line pair D and /D are weakly pulled up by the PMOSFETs 501 and 502 which are always ONL.

Next, an example of the configuration of the memory cell 2 is shown in FIG.

In the figure, WL is a warhead LD, /D is a data line pair.
VCC is a power supply voltage, GND is a ground potential, R1 and R2 are high resistances, and 601 to 604 are NMOSFETs.

Reading data from this memory cell and writing data to the memory cell are performed when the word line WL is high.
level, and the NMOSFETs 601 and 602 are turned on.

As described above, in the semiconductor memory according to this embodiment, the data written to the memory cell via the data line is not propagated to the common read line, which has a heavy load capacity. In other words, since the potential of the common read line does not change due to data writing, the total capacitance of the load to be charged and discharged during writing is reduced, making it possible to speed up the writing time. During recovery to return to a readable potential, the potential of the common read line has not changed from the potential at the time of data read, so only the data line needs to be recovered, resulting in faster recovery time. Indicated.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory that can speed up the writing time of data to a memory cell, and also,
A semiconductor memory that can speed up data line recovery time can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory read circuit and data write circuit according to a first embodiment of the present invention, and FIG. 2 is a semiconductor memory read circuit and data write circuit according to a second embodiment. 3 is a circuit diagram showing the overall structure of the semiconductor memory according to this embodiment, FIG. 4 is a timing chart showing the operation of the semiconductor memory, and FIG. 5 is a data line load circuit. 6 is a circuit diagram showing the configuration of a memory cell,
FIG. 7 is a circuit diagram showing the configuration of a read circuit and a data write circuit of a semiconductor memory according to the prior art. 1...Data line load circuit, 2...Memory cell, 101
, 102... write transfer gate, 10
3, 104, 107.108...Readout transfer gate, 10...Common readout line, 11...
Common writing line.

Claims (1)

[Claims] 1. A memory cell, a write line for writing data to the memory cell, a read line for reading data from the memory cell, and a wire connected to the memory cell and for reading data from the memory cell. connected to the read line through a first electronic switch that is connected when writing data to the memory cell and shut off when writing data to the memory cell; and connected to the write line through a second electronic switch when writing data to the memory cell. A semiconductor memory comprising: a data line; and means for cutting off the first electronic switch connecting the data line and the read line when writing data. 2. A memory cell, a write line for writing data to the memory cell, a read line for reading data from the memory cell, and a line connected to the memory cell, and when reading data from the memory cell and when reading data from the memory cell. A third electronic switch is connected to the read line through a first electronic switch that is connected when writing data and a second electronic switch that is cut off when writing data to the memory cell, and is connected when writing data to the memory cell. A semiconductor memory comprising: a data line connected to the write line via a switch. 3. A memory cell array consisting of memory cells arranged in a matrix, an address decoder for selecting memory cells, a common write line for writing data into each memory cell, and a common read line for reading data from each memory cell. and connecting the data line of the selected memory cell to the common read line when reading data from the memory cell, and cutting off the data line of the selected memory cell and the common read line when writing data to the memory cell. and means for connecting a data line of a memory cell selected at the time of writing data to a memory cell to the common write line. 4. A semiconductor integrated circuit comprising the semiconductor memory according to claim 1, 2 or 3.