JPH03216897A - Shift register - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D-flip float with a set and reset function, an AND gate, an inverter, and an analog circuit. The present invention relates to a shift register equipped with a switch.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional shift register. In the figure, 1 to 4 are set and reset D-flip-flops, 5 to 12 are AND gates, 13 is an inverter, and 14
, 15, 16, 17 are parallel data input terminals, l8 is a serial shift/parallel load selection terminal, 19 is a shift clock input terminal, 20 is a serial data input terminal,
21 is an output terminal.

Next, the operation will be explained.

First, when parallel input data is output as serial data, by setting the serial shift/parallel load terminal 18 to "L", the data input to the data input terminals 14 to 17 is transferred to the D-flip-flops 1 to 4. These D-
The Q outputs of flip-flops 1-4 are latched. At this point, the serial shift/parallel load selection terminal 18 was set to "H" and the AND gates 5 to 12 prohibited the parallel input data of the data input terminals 14 to 17 from being input to the D-flip-flops 1 to 4. Above, in synchronization with the clock signal input from the shift clock input terminal 19, the D-flip-flop 1
~4 latched Q outputs are shifted out from the output terminal 21.

Next, to shift out the serial input data from the output terminal 21, set the serial shift/parallel load selection terminal 18 to "H", and
12 prohibits the parallel input data of the data input terminals 14 to 17 from being input to the D-flip-flops 1 to 4, then the serial data input terminal 2
Serial data input from 0 is shifted out from the output terminal 21 in synchronization with the rising edge of the shift clock.

This state is shown in a time chart as shown in FIG.

In the figure, the states of parallel data input terminals 14 to 17 and serial data input terminal 20 are arbitrarily determined.

In the above description, it is assumed that the serial shift/parallel rot signal 18 is generated by Bunshu et al. from the shift clock of the shift clock input terminal 19.

[Problem to be solved by the invention]

Conventional shift register circuits were configured as described above, so when the ever-changing parallel input data is continuously taken out from the output terminal as serial data, a serial shift/parallel load selection signal is generated from the shift clock. Due to the slight serial shift
The parallel load selection signal lags behind the shift clock, which causes a hazard in the signal output from the output terminal as shown in FIG. 5.

This invention was made in order to solve the above-mentioned problems, and it prevents the occurrence of hazards in the output of the output terminal when parallel input data is continuously taken as serial data using an analog switch. The purpose is to obtain a reduced shift register.

[Means to solve the problem]

The shift register according to the present invention is capable of short-circuiting or opening the serial data input terminal and the parallel data input terminal by inserting an analog switch between the serial data input terminal and the parallel data input terminal.

(Function) In the shift register of the present invention, when parallel data is input to the shift register, the set input of the D-flip-flop and the D input (this is a serial data input terminal) are the same, so that the output of the output terminal is Even if serial data input appears, it will not cause a hazard.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
In the figure, parts that are the same as those in the conventional system are designated by the same reference numerals, so their explanation will be omitted. Code 22 in the figure
, 23 is an analog switch, and 24 is an analog switch control terminal.

Next, the operation will be explained.

When the shift register shifts out the parallel data from the parallel data input terminals 14 to 17 from the output terminal 21 using the serial shift parallel load selection signal from the serial shift parallel load selection terminal 18 generated from the shift clock from the shift clock input terminal 19, the shift register is controlled by an analog switch. By setting the terminal 24 to “L”, the analog switch 22 is turned on and the analog switch 23 is turned on.
Leave it in FFL state. In this state, when the parallel input data of the parallel data input terminals 14 to 17 is continuously taken out from the output terminal 21, the serial shift parallel load selection of the serial shift parallel selection terminal 18 is performed as shown in the time chart of FIG. Even if the signal lags behind the shift clock of the shift clock input terminal 19,
Since the D input of the D-flip flop 1 is the same as the parallel data input of the parallel data input terminal 14, no hazard occurs at the output terminal 21 as in the conventional case.

When data from the serial data input terminal 20 is shifted out from the shift register, the analog switch 22 is turned off by setting the analog switch control terminal 24 to "H", and the analog switch 22 is turned off by turning on the analog switch 23 to output the serial data input terminal. 20 and the D input of the D-flip-flop 1 are placed in a short-circuited state, and data is obtained from the output terminal 21 in the same manner as the conventional one.

In the above embodiment, there are four D-flip-flops 1 to 4 with set and reset functions, and the shift register uses 4-bit parallel data as a serial data. You can.

〔Effect of the invention〕

As described above, according to the present invention, by short-circuiting the D input and set input of the D-flip-flop using the analog switch, a hazard is generated at the output terminal when parallel input data is continuously output as a serial data. This has the effect of not allowing

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a shift register according to an embodiment of the present invention, FIG. 2 is a time chart explaining the operation when the shift register of FIG. 1 is used, and FIG. 3 is a circuit diagram of a conventional shift register. FIG. 4 is a time chart explaining the operation of the shift register in FIG. 3, and FIG. 5 is a time chart showing hazards in the shift register in FIG. In the figure, 1 to 4 are D-flip-flops with set/reset, 5 to 12 are AND gates, 13 is an inverter,
14 to 17 are parallel data input terminals, 18 is a serial shift parallel load selection terminal, 19 is a shift clock, 20 is a serial data input terminal, 21 is an output terminal, 2
2 and 23 are analog switches, and 24 is an analog switch control terminal. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] A D-flip-flop with set and reset inputs and this D-flip-flop with set and reset inputs;
- In a shift register composed of an AND gate, an inverter, and an analog switch connected to a flip-flop, the D input of the D-flip-flop and the set input of this D-flip-flop can be short-circuited or opened by the analog switch. A shift register characterized by: