JPH03216899A - Built-in self-test circuit - Google Patents

Abstract

PURPOSE:To realize a function capable of hold test by stopping the progression of self-test for a certain time and restarting the test thereafter to test the stored information hold time of a memory cell of a semiconductor memory. CONSTITUTION:The end of test pattern write to the memory cell is detected on the outside of a chip by a test pattern write end discriminating means 128, and the internal state of a self-test circuit is held by a self-test state holding means 126 at the time of interrupting the test. By these two functions, the progression of test procedures of self-test is stopped for a certain time after detection of the end of test pattern write to the memory cell and the operation is restarted. Consequently, the progression of self-test is temporarily stopped to stop the access to the memory cell for a prescribed hold time, and thereafter, self-test is restarted and data is read out from the memory cell and is compared with an expected value. Thus, the hold test of the memory is possible.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to built-in self-test circuits for semiconductor memories.

(Prior Art) As semiconductor memory becomes larger in scale, the time required to test its operation increases, leading to an increase in cost. One way to solve this problem is to mount its own test circuit, that is, a self-test circuit, on the semiconductor memory chip. There is. This is called a built-in self-test method. According to this method, it is possible to easily test a large number of memory chips in parallel, and the testing time n can be shortened. Furthermore, since it takes over the functions of a memory tester, the cost of the memory tester can be reduced.

As a memory equipped with a built-in self-test circuit, for example, I. E. E. E-Journal of Solid State Circuits Part 1 (I
EEE JOURNAL OF SOLID STAT
E CIRCUITS Vol. SC-22, No.
5, OCT. 1987 PP. 663-668
Paper published in “A 60-ns 4-Mbit
CMOS DRAM witlBuilt-InSe
lf-Test Function” T. Ohsa
wa et. al. ) has been removed. The concept of this built-in self-test will be explained clearly using the circuit block diagram shown in FIG.

In FIG. 8, the block diagram above the one-dot chain line is a block diagram of a normal memo circuit 801, and the block diagram below is a block diagram of a self-test circuit 803. In the figure, the circles indicate signal pin terminals protruding from the tip tab. Further, thin arrows indicate the flow of signals inside the chip, and thick arrows indicate the flow of addresses and data.

First, the memory circuit 801 in FIG. 8 will be explained. Addresses input from outside the chip are decoded by address buffer 805 and x, y decoders 807 and 809, and a target memory cell is selected from memory cell array 811. When reading data, the data read from the selected memory cell is transferred to the data amplifier 8.
13, it passes through the input/output buffer 815 and is output from the data output pin to the outside of the chip. Furthermore, when writing data, data is input from the data input pin and written into the selected memory cell via the large buffer 815 and data amplifier 813.

Next, the self-test circuit 803 shown in FIG. 8 will be explained. The term "test" used here refers to a so-called functional test in which certain data is written into a memory cell, and then the data is read out to confirm whether the memory storage operation is normal. When a self-test start signal is input from outside the chip, this memory chip enters self-test mode.
Thereafter, based on the self-test reference signal, the self-test control circuit 820 controls the test pattern generation circuit 822 and the comparison circuit 82.
4 to proceed with a series of test procedures including writing and reading a test pattern and comparing it with an expected value.

During the self-test, if a mismatch between the read data from the memory cells and the expected value data is detected, an error signal (error flag) is output to the outside of the chip. After the test is finished, output a test completion signal to notify the outside.

By installing the above self-test circuit on a memory chip, as mentioned at the beginning, test time can be shortened by testing multiple chips in parallel, and the cost required for testing can be reduced by replacing the functions of the memory tester. reduction can be achieved.

(Problem to be Solved by the Invention) However, in conventional self-test circuits, one of the extremely important tests for distinguishing between good and defective memory products.
Testing of memory information retention time was not possible. A memory information retention time test is a test to determine whether the time that memory information is retained after writing data to a memory cell without rewriting the data to the memory cell satisfies the standard. This is called the hold test.

An object of the present invention is to provide a memory equipped with a built-in self-test that performs a conventional functional test a function that enables a hold test using a control signal from outside the chip.

(Means for Solving the Problems) The present invention provides a test pattern generating means for generating address and expected value data for testing the operation of a semiconductor memory, data read from a memory cell of the semiconductor memory and the expected value data. and a comparison means for notifying the comparison result to the outside of the semiconductor memory chip, a self-test control means for controlling the operation of the test pattern generation means and the comparison means, and data using the test pattern generation means to the memory cell. A built-in self-contained device comprising test pattern write completion determining means for informing the outside of the memory chip whether or not writing has been completed, and self-test state holding means for holding the internal states of the self-test control means, the test pattern generation means, and the comparison means, respectively. A test circuit is provided on the semiconductor memory chip, and when performing a test using this built-in self-test circuit, after the test pattern has been written into the memory cell, the test pattern write completion determination circuit outputs the The completion of writing the test pattern to the memory cell is detected by a signal, the progress of the self-test is stopped for a certain period of time by a control signal from outside the memory chip, and the self-test is then restarted to read the information stored in the memory cell of the semiconductor memory. Consists of a built-in self-test circuit with means for testing retention times.

(Function) In the built-in self-test circuit of the present invention, the end of writing a test pattern to a memory cell can be detected outside the chip by the test pattern writing end determination means.
Furthermore, the self-test state holding means can hold the internal state of the self-test circuit when the test is interrupted. These two functions make it possible to resume operation after a certain period of time after detecting the end of the test pattern applied to the memory cell, without proceeding with the test procedure by self-test. Therefore, after detecting the data write end signal, the progress of the self-test is temporarily stopped, access to the memory cells is stopped for a standard hold time, and then the self-test is restarted to read data from the memory cells and obtain the expected value. This method allows not only a simple functional test like the conventional built-in self-test, but also a memory hold test.

(Example) Next, specific embodiments of the present invention will be described using the drawings.

The hold test is basically performed in the following steps.

(a) Write certain data to a memory cell.

(b) Leave it alone for a certain period of time (data is not rewritten).

(e) Read data from the memory cell and check whether the data (expected value) written in (a) is retained.

A method for carrying out the steps (a) to (C) above using the built-in self-test circuit of the present invention will be described.

FIG. 1 shows the block configuration of a memory equipped with the built-in self-test circuit of the present invention, and FIG. 2 shows the operation timing waveforms of the circuit shown in FIG.

First, when a self-test start signal is manually applied to the memory chip, the memory enters the self-test mode from the normal read or write mode. In this self-test mode, only addresses and data generated from the self-test circuit 103 are valid, and addresses and data from outside the chip are ignored.

As described above, when the self-test mode is entered, the self-test is performed using the self-test reference signal as the reference clock.

First, a test pattern to be written into a memory cell, that is, an address and data to be written into a memory cell corresponding to the address, is generated by the test pattern generation circuit 122 and actually written into the memory cell ((2) in FIG. 2). When this operation is completed, the test pattern write end determination circuit 128 outputs a signal indicating the end of the write operation to the outside of the chip. At the same time, the self-test state holding circuit 126 causes the self-test circuit 103 to maintain its current state and not proceed with the test procedure. Self-test control circuit 1
20 and the test pattern generation circuit 122 are configured with static circuits, it is sufficient to stop the clock that operates these two circuits in order to prevent the test procedure from proceeding further. In the case of a dynamic circuit, a flip-flop or the like may be connected to a node whose state is to be held, and the flip-flop may be operated when the holding mode is entered. Outside the chip, when the write operation end signal is detected, the self-test reference signal is stopped and access to the memory cells is stopped. By doing so, it is possible to carry out the hold test described in (a) and (b) above, in which data is written to the memo cell and then the memory cell is left for a certain period of time without being accessed ((2) in FIG. 2). Note that "do not access memory cells" here means that data is not rewritten, that is,
In the case of DRAM, this means that frescoche is not performed. If refresh is not performed, the above (b)
), the circuit operation of the memory main body may be performed. Specifically, as shown in FIG. 3, a capacitor 308 for storage storage, a gate connected to a word line 302,
When a memory having a memory cell 300 consisting of a switching N-channel field effect transistor 306 whose drain is connected to a bit line 304 and whose source is connected to a storage storage node 312 of a memory cell capacitor 308 is tested using the circuit of the present invention. Take for example. At this time, in the circuit operation of changing the voltage of the bit line 304 while keeping the word line 302 of the memory cell to be tested (referred to as the memory cell of interest) at a low level and the switching transistor 306 kept non-conductive, the memory cell of interest is refreshed. will not be carried out.

Therefore, such a circuit operation may be performed during the above period (b). In such a case, it becomes possible to perform a hold test that also takes into account the influence of noise caused by voltage changes on the bit line.

Of course, it is also possible to perform a test in which the memory main body does not operate the circuit at all during the period (b) without doing this. In this case, a static hold test of the memory cell can be performed to detect defects mainly due to leakage from the storage storage node. In other words, the key point is that the memory cell of interest is not refreshed during the period (b), and as long as this is followed, it does not matter if the circuit is operating in the memory itself.

After a predetermined period of time has elapsed, the self-test reference signal is restarted, data is read from the memory cells, and the comparison circuit 124 compares this data with the expected value obtained from the test pattern generation circuit. If a mismatch between the read data and the expected value data is detected, an error flag is output and
Inform outside of the chip. (Figure 2 ■).

In Figure 2, the self-test is temporarily stopped by stopping the manual input of the self-test reference signal, but instead of using the reference signal to suspend the self-test, a new circuit block is shown in Figure 4. Another method is to input a self-test interrupt signal from outside the chip to instruct the test to stop. FIG. 5 shows the timing when testing using the built-in self-test circuit of FIG. 4. Here, upon receiving the test pattern write end signal, a self-test interrupt signal is input to the self-test control circuit 120 to stop the self-test, and when restarting, the self-test interrupt signal is returned to the original state.

FIG. 6 shows a modification of the embodiment shown in FIG. The operation timing is shown in FIG. In the method shown in Figure 1, the self-test can be temporarily stopped by stopping the input of the self-test reference signal, etc.
This is done in synchronization with a human clock input from outside the chip. However, as shown in FIG. 7, the output of the test pattern write end determination circuit 128 is input to the self test control circuit 120, and the self test control circuit 128 synchronizes with the signal (test pattern write end flag) output from the determination circuit 128. There is also a method in which the circuit 120 automatically stops generating the test pattern and then waits until an instruction signal to start the test is manually input from the outside. Here, a self-test restart signal is newly provided, but this can be replaced with a self-test start signal, a self-test reference signal, or the like.

In the above, the signals related to self-test, namely,
It is assumed that the self-test start signal, self-test reference signal, pattern writing end flag, error flag, etc. are each provided with dedicated pins and manually or output. However, the method is not limited thereto. for example,
Another method is to share the signal pins, address bins, and data bins of the memory main body with the pins for self-testing. Another method is to use the logic of a plurality of human output pins of the memory main body as the self-test start signal, and enter the self-test mode when a certain clock human input pattern is input.

(Effects of the Invention) As described above, by using the present invention, a hold test can be performed by a built-in self-test. thus,
The hold test in memory selection can also be made into a self-test, which is effective in reducing test costs.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a memory equipped with a built-in self-test which is the first embodiment of the present invention, FIG. 2 is a diagram showing the operation timing of the circuit in FIG. 1, and FIG. 3 is a DRA
4 is a circuit block diagram of the second embodiment of the present invention, FIG. 5 is a diagram showing the operation timing of the circuit of FIG. 4, and FIG. 6 is a diagram of the third embodiment of the present invention. FIG. 7 is a circuit block diagram of the embodiment, FIG. 7 is a diagram showing the operation timing of the circuit of FIG. 6, and FIG. 8 is a circuit block diagram showing an example of a conventional built-in self-test mounted memory.

Claims (1)

[Claims] A test pattern generating means for generating addresses and expected value data for testing the operation of the semiconductor memory, comparing data read from the memory cells of the semiconductor memory with the expected value data, and transmitting the comparison result to the semiconductor memory chip. A comparison means for informing the outside, a self-test control means for controlling the operation of the test pattern generation means and the comparison means, and a means for informing the outside of the memory chip whether or not data writing to the memory cell using the test pattern generation means has been completed. A built-in self-test circuit is provided on the semiconductor memory chip, and includes a test pattern writing completion determination means, a self-test state holding means for holding the internal states of the self-test control means, the test pattern generation means, and the comparison means, respectively. When performing a test using the built-in self-test circuit, after the writing of the test pattern to the memory cell is completed, the writing of the test pattern to the memory cell is completed by a signal output from the test pattern writing completion determination means. The present invention further comprises a means for detecting the self-test, stopping the progress of the self-test for a certain period of time using a control signal from outside the memory chip, and then restarting the self-test to test the storage information retention time of the memory cell of the semiconductor memory. Features a built-in self-test circuit.