JPH03217045A - Automatic lay-out and wiring method - Google Patents

Abstract

PURPOSE:To optimize a cell size without complicating a wiring process or increasing calculating time by setting a cell frame for determining a boundary of a standard cell along an imaginary half wiring lattice of 1/2 of lattice interval of the lattice. CONSTITUTION:In an automatic lay-out and wiring method for automatically setting wiring lattices GX, GY at predetermined intervals in two perpendicular directions, automatically wiring standard cells 10A, 20, 30, 40, 50, 60 at terminals on lattice points of its wiring lattice, and automatically wiring the terminals C11-C66 of the standard cells on the lattice, cell frames 11A, 21, 31, 41, 51, 61 for determining boundaries of the standard cells are set along imaginary half wiring lattice of 1/2 of the interval of the lattice, the standard cells in which inner cell frames 12, 22, 32, 42, 52, 62 are set inside the interval of the half wiring lattice by the cell frames are used, and the standard cells are automatically laid to separate the inner cell frames by the wiring lattice interval.

Description

[Detailed description of the invention] 【overview】

In chip design, the automatic placement and wiring method uses computers to automatically place and route standard cells to lay out semiconductor integrated circuits. For the purpose of optimization, a wiring grid is set at regular intervals in each of two orthogonal directions, standard cells whose terminals are set on the grid points of the wiring grid are automatically placed, and the terminals of the standard cells are In an automatic placement/routing method of automatically routing a line between lines along the wiring grid, a cell frame that defines the boundary of the standard cell along a virtual half-wiring grid that halves the grid spacing of the wiring grid. is set, and an internal cell frame is set inside the cell frame by a half wiring grid interval, and the standard cell is automatically arranged so that the internal cell frames are separated from each other by the wiring grid interval. shall be.

[Industrial application field]

The present invention relates to an automatic placement and wiring method for laying out a semiconductor integrated circuit by automatically placing and wiring standard cells using a computer in chip design.

[Conventional technology]

This type of automatic placement and wiring method creates a library of layout patterns for inverters, NAND gates, NOR gates, etc. as standard cells, and uses a computer to place standard cells based on logic circuit diagrams.
Wire between standard cells. FIG. 3 shows a standard cell 10 of a two-man powered NAND gate. In the figure, 11 is a cell frame defining the boundary of the standard cell 10, 13 is a P-channel transistor, 14 is an N-channel transistor, 15 and 16 are power supply lines (Vnn
, Vss), N 1 1 and N12 are contacts connecting between the diffusion region of the P-channel transistor 13 and the power supply line 15, and N13 is a contact connecting between the diffusion region of the N-channel transistor 14 and the power supply line 16. Contacts C11 and C12 are the two input terminals of the NAND gate, and contacts C13 to C17 are the output terminals of the NAND gate. Wiring between standard cells is performed according to complicated pattern rules for a large number of cells, so the process is complicated and takes a lot of time. Therefore, a method is generally used in which wiring grids GX and GY are set at regular intervals in each of two orthogonal directions, and wiring is performed along the wiring grids GX and GY. This method simplifies pattern rules and wiring processing, simplifies automatic wiring software configuration, and shortens processing time. In this method, since the wiring is arranged along the wiring grids GX and GY, the terminals CI1 to C17 are set on the grid points (intersections of the wiring grids GX and GY). Furthermore, since the power supply lines 15 and 16 must be continuous between adjacent cells, the cell frame 11 that defines the boundary of the standard cell 10 must be set along the wiring grids GX and GY, and must be connected to the adjacent cells. Cell frames of matching standard cells are matched. The wiring lattice spacing is determined based on the line width of the wiring, the required minimum wiring spacing, the arrangement of elements within the basic cell, etc., so as to enable the most efficient wiring.

[Problem to be solved by the invention]

However, for example, if the necessary and sufficient width of a standard cell without considering the wiring grid GY is 15 μm and the interval between the wiring grids GY is 10 μm, then the width of the cell frame 11 of this standard cell is set to 20 μm. As a result, a wasted area is created within the cell frame 11. In order to prevent this wasted area from occurring, the wiring grid spacing could be halved to 5 μm, but this would complicate the wiring process and increase the amount of processing, making the automatic wiring software configuration complicated. Along with this, the processing time becomes longer. In view of these problems, an object of the present invention is to provide an automatic placement/routing method that can further optimize cell size without complicating wiring processing or increasing calculation time. be.

[Means to solve the problem]

In order to achieve this object, in the automatic placement/wiring method according to the present invention, for example, as shown in FIG. 2 of the embodiment drawings, wiring grids GX,
Set GY, standard cells 20, 30, 40, 5
0 and 60 are automatically placed and automatically wired between the terminals of the standard cell along the wiring grid. Standard cells 20, 30, 40, 50, and 660 have terminals C21 to C66 set on grid points of a wiring grid, and cell frames 21, 31, which define boundaries of standard cells 20, 30, 40, 50, and 60, 41, 51, and 61 are set along a virtual half-wiring grid that halves the grid spacing of the wiring grids GX and GY, and the internal cell frame 22
, 32, 42, 52 and 62 are cell frames 21, 31, 4
1, 51, and 61 by a half wiring grid interval. Such standard cells 20, 30, 40, 50 and 60 are arranged in internal cell frames 22, 32, 42, 52 and 62.
are placed so that they are separated from each other by the wiring grid interval.

[Effect]

Internal cell frames 22, 32, 42, 52 assumed to be inside the half-wiring grid interval from the cell frames 21, 31, 41, 51, and 61
By arranging the standard cells 20, 30, 40, 50, and 60 such that the terminals and 62 are separated from each other by the wiring grid interval, the standard cells are arranged without any gaps, and the minimum terminal interval between adjacent standard cells is is equal to the wiring grid spacing (terminals C23 and C31, terminals C33 and C41, terminals C43 and C51, and terminal C54)
and C61 interval). Therefore, standard cells 20, 30, 40, 50
and 60, there is no need to consider the cell frames 21, 31, 41, 51, and 61 set along the virtual half-wiring grid, and it is sufficient to process the wiring grids GX and GY. In addition, standard cells 20, 30, 40, 50 and 6
Cell frames 21, 31, 41, 51 and 6 that define the boundaries of 0
1 is set along a hypothetical half-wiring grid in which the grid spacing of the wiring grid GXXGY is halved, so in areas where wasted areas occur, the grid spacing is effectively halved. Become. Therefore, wasted areas within the cell frame can be reduced, and the cell size can be more optimized than before. Furthermore, since there is no need to actually narrow the interval between the wiring grids GX and GY in order to narrow the wasted area, there is no need to complicate the wiring process or increase calculation time.

【Example】

Hereinafter, one embodiment of the present invention will be described based on the drawings. FIG. 1 shows a standard cell corresponding to FIG. Components that are the same as those in FIG. 3 are given the same reference numerals and their explanations will be omitted. The spacing between the wiring grids GX and GY is the same as in FIG. 3. The cell frame 11A of the standard cell IOA is set along a hypothetical half-wiring grid in which the grid spacing between the wiring grids GX and GY is halved. Accordingly, both ends of the power supply lines 15 and 16 in the longitudinal direction are each shortened by a half wiring grid interval. The pattern within the cell frame 11A is exactly the same as the corresponding portion within the cell frame 11 in FIG. That is, the cell size is optimized more than in the case of FIG. 3 by reducing the wasted area within the cell frame 11A without narrowing the interval between the wiring grids GX and GY9. In the figure, 12 is an internal cell frame, which is set inside the cell frame 11A by a half-wiring grid interval. Terminals (contacts) C11 to C17 exist at the grid points on this internal cell frame 12. When such standard cells IOA are automatically arranged by a computer, they are arranged so that the internal cell frames 12 are separated from each other by the wiring grid interval. FIG. 2 shows an example of automatic placement. In the figure, 20, 30, 40, 50 and 60 are standard cells of an inverter, a NAND gate, a NOR gate, an inverter and a NAND gate, and 2131, 4
1, 51 and 61 are cell frames of these standard cells, 22, 32, 42, 52 and 62 are internal cell frames of these standard cells, C21 to C25,
C31-C35, C41-C47, C51-C55 and -
10 and C61 to C66 are terminals (contacts) arranged in each standard cell. Between internal cell frames 22 and 32, between internal cell frames 32 and 42, between internal cell frames 42 and 52, and internal cell frame 52
and 62 are separated by the wiring grid interval. By arranging the standard cells in this manner, the standard cells are arranged without any gaps. Further, the minimum value of the terminal spacing between adjacent standard cells is equal to the wiring grid spacing (the spacing between terminals C23 and C31, terminals C33 and C41, terminals C43 and C51, and terminals C54 and C61). Therefore, when arranging standard cells, there is no need to consider the cell frame set along the virtual half-wiring grid, and processing can be performed on the wiring grids GX and GY.

【Effect of the invention】

As explained above, in the automatic placement/routing method according to the present invention, the cell frames that define the boundaries of standard cells are set along a virtual half-wiring grid in which the grid spacing between the wiring grids GX and GY is 172. As for the parts where wasted areas occur, the grid spacing is effectively halved, so the wasted areas within the cell frame can be reduced, and the cell size can therefore be optimized more than before. Moreover, since there is no need to actually narrow the spacing between the wiring grids GX and GY to narrow the wasted area, there is no need to complicate the wiring process or increase the training time. It has a great effect.

[Brief explanation of drawings]

1 and 2 relate to an embodiment of the automatic placement and wiring method according to the present invention, FIG. 1 is a layout diagram of standard cells on a wiring grid, and FIG. 2 is a layout diagram of standard cells on a wiring grid. It is a diagram. FIG. 3 is a layout diagram of standard cells on a wiring grid according to a conventional example. In the figure, CI1 to C66 are terminals (contacts) 10, IOA, 20, 30, 40, 50, 60 are standard cells 11, 11A, 21, 31, 41, 51, 61 are cell frames 12, 22, 32, 42 , 52, 62 are internal cell frames 13

Claims (1)

[Claims] Wiring grids (
GX, GY) and the standard cells (10A, 20, 30, 4) whose terminals are set on the grid points of the wiring grid.
0, 50, 60) and automatically route between the terminals (C11 to C66) of the standard cell along the wiring grid, the grid spacing of the wiring grid is set to 1/2. Cell frames (11A, 21, 31, 41, 51, 61) that define the boundaries of the standard cell are set along the virtual half-wire grid, and internal cells are placed inside the half-wire grid interval from the cell frame. Frame (12
, 22, 32, 42, 52, 62) are set, and the internal cell frames are separated from each other by the wiring grid interval.
An automatic placement and wiring method characterized by automatically placing the standard cells.