JPH03217052A - Semiconductor protecting circuit device - Google Patents

Abstract

PURPOSE:To obtain a high integration protective device having substantially same strength against positive and negative high voltage noises by bonding a reverse conductivity type second semiconductor substrate for forming a second diode along with an impurity region formed on the rear surface onto a semiconductor substrate for forming a diode along with an impurity region formed on the surface through an insulating film. CONSTITUTION:In a semiconductor device in which a reverse conductivity type second semiconductor substrate 5 is bonded on one conductivity type first semiconductor substrate 1 through an insulating film 3, a reverse conductivity type impurity region 2 provided on the substrate 1 to form a first PN junction diode along with the substrate 1, and one conductivity type impurity region 4 provided on the lower surface of the substrate 5 to form a second PN junction diode along with the substrate 5 are connected, and provided between an input terminal 14 and an input circuit 17 or between an output terminal and an output circuit. For example, the regions 2, 4 are connected via trench-buried conductive film 9, and ground voltage 16 and power source voltage 15 are respectively applied to the substrate 1, 5.

Description

[Detailed Description of the Invention] [Summary] A first semiconductor substrate having one conductivity type and an impurity region of an opposite conductivity type formed on the upper surface of the first semiconductor substrate.
A second semiconductor substrate having an opposite conductivity type and an impurity region of a -conductivity type formed on the lower surface of the second semiconductor substrate form a second PN junction diode in an opposite direction. In addition, the second semiconductor substrate is bonded to the first semiconductor substrate via an insulating film, and the first and second PN junction diodes connected in parallel are connected between the input terminal and the input circuit or between the output terminal and the first semiconductor substrate. Since it is formed in a structure provided between output circuits, it is possible to form a protection device consisting of two forward-operating PN junction diodes with opposite operating directions three-dimensionally, thereby increasing the degree of integration and reducing the degree of integration. High reliability can be achieved by forming a protection device that has the same strength against positive and negative high voltage noise without causing
Further, SOI (Si) is formed on the upper surface of the second semiconductor substrate.
licon on insulator) Semiconductor protection circuit device that enables high integration and high reliability by forming a deep protection device with large resistance and capacitance added under a manufactured element 9 [Industrial application field] Book The present invention relates to MIS and bipolar semiconductor integrated circuit devices, and relates to a highly integrated protection device that prevents destruction of input circuits or output circuits due to positive and negative high voltage noise.9 Conventionally, protection devices for semiconductor integrated circuits include:
An impurity region of an opposite conductivity type is provided on the surface of a semiconductor substrate of one conductivity type, a first PN junction diode is formed by the impurity region of the opposite conductivity type and the semiconductor substrate of one conductivity type, and a first PN junction diode is formed on the surface of a semiconductor substrate of one conductivity type. Provide an impurity well region of opposite conductivity type,
Furthermore, an impurity region of one conductivity type is provided on the surface of the impurity well region, and a second PN junction diode with opposite directions is formed by the impurity region of one conductivity type and the impurity well region of the opposite conductivity type, and are connected in series or in parallel. The protection device is provided between the input terminal and the input circuit or between the output terminal and the output circuit. In order to improve the protection characteristics, it is necessary to increase the time constant of two PN junction diodes with opposite directions that operate in the forward direction, and the resistance and capacitance to blunt high voltage noise, which improves the protection characteristics. The area occupied by the protection device increases accordingly. Particularly in game I arrays and microprocessors where a large number of input and output terminals are required.
This has led to an extremely large reduction in the degree of integration, and is becoming a problem that is becoming a hindrance to the integration of large-scale systems into integrated circuits. Therefore, there is a need for a means to form extremely highly integrated protection devices with high protection characteristics.
[Prior Art] Fig. 4 (a) (1)) is a schematic diagram of a conventional semiconductor protection circuit device, in which (a) is a side sectional view, (1)) is a circuit diagram, and 51 is a p-type silicon ( Si) substrate, 52 is an n-type impurity well region, 53 is an n-type impurity region, 54 is a p-type impurity region, 55 is a field oxide film, 5G is an oxide film for impurity blocking, 57 is phosphosilicate glass (PSG) Membrane, 58 is A1
Wiring, 59 is input 7/output terminal, 60 is Vcc (power supply voltage), 61 is V. ss (ground voltage), 62 indicates an input 2/output circuit section.

In the same figure, n-type silicon substrate 51 is selectively
A ten type impurity region 53 is provided, and an n ten type impurity region 53
A first PN junction diode is formed by a p-type silicon substrate 51, and 1) an n-type impurity well region 52 is selectively provided in the p-type silicon substrate 51, and a p-type impurity well region 52 is selectively provided in the p-type silicon substrate 51. A second PN junction diode is formed with the p-type impurity region 54 and the n-type impurity well region 52 in opposite directions, and relatively small resistance and capacitance are added and connected in series. A protection device including first and second PN junction diodes is provided between the input terminal and the input circuit or between the output terminal and the output circuit. Therefore, since the first and second PN junction diodes can only be formed on the surface of the semiconductor substrate, and in order to improve the protection characteristics, it is necessary to form a protection device with large resistance and capacitance, which reduces the degree of integration. There has been a problem in that it is difficult to form high-yield large-scale integrated circuits. In addition, there is also the problem that it is difficult to obtain a protection device that has the same strength against positive and negative high voltage noises because PN junction diodes are connected in series (if they are connected in parallel, the layout 1 and 2 will reduce the degree of integration). there were.

[Problem to be Solved by the Invention 1] The problem to be solved by the present invention is that, as shown in the conventional example, a protection device consisting of two forward-operating PN junction diodes with different directions is attached to the surface of a semiconductor substrate. In addition, since a large protection device is required to improve the protection characteristics, a considerable number of protection devices are required in an integrated circuit that requires a large number of input or output terminals. Since high integration could not be achieved, it was difficult to form high-yield large-scale integrated circuits, and it was difficult to obtain highly integrated protection devices with equivalent strength against positive and negative high voltage noise. .

[Means for solving the problem] The above problem is solved by a semiconductor device in which a second semiconductor substrate having an opposite conductivity type is bonded onto a first semiconductor substrate having one conductivity type via an insulating film. an impurity region of opposite conductivity type provided on the upper surface of the first semiconductor substrate and forming a first PN junction diode with the first semiconductor substrate; and an impurity region provided on the lower surface of the second semiconductor substrate. The second semiconductor substrate is connected to an impurity region of one conductivity type forming a second PN junction diode, and is provided between an input terminal and an input circuit or between an output terminal and an output circuit. This problem is solved by the semiconductor protection circuit device.

[Function] That is, in the semiconductor protection circuit device of the present invention, the first PN is formed by the first semiconductor substrate having one conductivity type and the impurity region of the opposite conductivity type formed on the upper surface of the first semiconductor substrate. forming a junction diode, forming a second PN junction diode in opposite directions with a second semiconductor substrate having an opposite conductivity type and an impurity region of a -conductivity type formed on a lower surface of the second semiconductor substrate; In addition, the second semiconductor substrate is connected to the first semiconductor substrate through an insulating film.
The first and second PN junction diodes bonded to the semiconductor substrate and further connected in parallel are formed in a structure provided between the input terminal and the input circuit or between the output terminal and the output circuit. Semiconductor substrate and bonded SOI base A protective device consisting of two forward-operating PN junction diodes with opposite operating directions can be formed in a completely three-dimensional manner, which increases the degree of integration on the surface. It is possible to form a protection device consisting of two PN junction diodes with opposite operating directions by connecting them in parallel without reducing the integration density, regardless of the In addition, by being able to form a protection device under an element with an SOI structure, it does not require any surface area other than the connection between the two PN junction diodes, and has a large resistance. The ability to form a capacitance-added protection device also enables high integration and high reliability with excellent protection characteristics. That is, it is possible to obtain a semiconductor protection circuit device that enables the formation of extremely highly integrated and highly reliable semiconductor integrated circuits.

[Examples] The present invention will be specifically described below with reference to illustrated examples. 1st
Figure (a) (1)) is a schematic diagram of the first embodiment of the semiconductor protection circuit device of the present invention, and Figure 2 (a) (1)) is a schematic diagram of the second embodiment of the semiconductor protection circuit device of the present invention. 3(a) to 3(e) are process cross-sectional views of an embodiment of a method for manufacturing a semiconductor protection circuit device of the present invention.

Identical objects are indicated by the same reference numerals throughout the figures.

FIG. 1 is a schematic diagram of the first embodiment of the semiconductor protection circuit device of the present invention when a p-type silicon substrate is used.
is a side sectional view, (1)) is a circuit diagram, 1 is 10 cm
The first silicon substrate of p type 2 is 10'''cm
−” first impurity region of type n0, 3 is 1/lAm
4 is a p+ type impurity region of about 1020 cm", 5 is an n- type second silicon substrate of about 1016 cm-3, and 6 is an n0 type second impurity region of about 102' cm-3. region, 7 is a trench-embedded insulating film in the first 1, 8
1 is the second 1-trench sidewall insulating film, 9 is the second and third trench-embedding conductive film, 10 is an oxide film for impurity blocking of about 35 nn+, 11 is a phosphosilicate glass (PSG) film of about 600 nm, 12 is A1 wiring of about 17um, 1
3 is Au electrode, 14 is input, 'output terminal, 15 is Vcc
(power supply voltage), 16 is vss (ground voltage),
Reference numeral 17 indicates an input/'output circuit section.

In the figure, 1) a one-type first silicon substrate 1 to which a ground voltage 16 is applied; and 1) an n0-type first impurity formed on the upper surface of the one-type first silicon substrate 1. A first PN junction diode is formed with region 2, and a second n-type silicon substrate 5 to which a power supply voltage of 15 is applied, and n
A second PN junction diode in the opposite direction is formed with the p+ type impurity region 4 formed on the lower surface of the - type second gyricon substrate 5, and the n-type second silicon substrate 5 is formed with the oxide film 3. A resistor consisting of a p-type impurity region 4 and an n-type first impurity region 2 is added, and is connected in parallel by a buried conductive film 9. First and second PN junction diodes connected are formed in a structure provided between the input terminal and the input circuit or between the output terminal and the output circuit. Although not shown in the figure, various elements (MIS transistors, bibolar transistors, resistors, capacitors, etc.) are formed on the upper surface of the 11-type second silicon substrate 5. This is because a protection device consisting of two forward-operating PN junction diodes, each formed on a semiconductor substrate and a bonded SOI substrate, which operate in opposite directions and have large resistance and capacitance, can be formed completely three-dimensionally. High integration is also possible, as a protection device consisting of two PN junction diodes with opposite operating directions connected in parallel can be formed regardless of the surface layout, i.e. without reducing the degree of integration. High reliability is achieved by forming a protection device with the same strength against voltage noise, and the ability to form a protection device under an element with an SOI structure improves the reliability of two PN junction diodes.
It does not require any surface area other than the connections at certain points, and it also enables the formation of a protective device with large resistance and capacitance, which enables high integration and high reliability with excellent protection characteristics. can.

FIG. 2(a)(1)) is a schematic diagram of a second embodiment of the semiconductor protection circuit device of the present invention, in which (a) is a side sectional view;
b) is a circuit diagram, and 1 to 17 show the same components as in FIG.

In this figure, the same horizontal structure as in FIG. 1 is formed, except that a protection device consisting of two forward-operating PN junction diodes with no added resistance is formed. Compared to the effect of the first embodiment, in this embodiment, since no resistor is added, the protection characteristics are slightly inferior, or the connection between the two PN junction diodes is in one place, and the integration is higher. fhi is possible.

Next, an embodiment of the method for manufacturing a semiconductor protection circuit device according to the present invention will be described with reference to FIGS. 3(a) to 3(e) and FIG. 1. However, only the manufacturing method related to the formation of protection devices will be described here, and various elements (transistors, resistors, capacitors, etc.) mounted on general semiconductor integrated circuits will be described here.
A description of the manufacturing method for forming the will be omitted.

FIG. 3(a) Arsenic ions are implanted into the upper surface of a p-type first silicon substrate 1 to form an n+-type first impurity region 2. FIG. Next, boron ions are implanted into the lower surface of the n-type second silicon substrate 5 to form (1) a ten-type impurity region 4; Next, an oxide film 3 (approximately IPm) is grown on the lower surface of the second silicon substrate 5 on which the p-type impurity region 4 is formed, and is grown on the first silicon substrate 1 at approximately 1100°C in an N2/02 atmosphere. Bonding is performed by annealing for 2 hours. In this way, the first type of n-type
The impurity region 2 is a p-type impurity region (FIG. 3(l)) to a thickness of about 1.tAm. Next, an oxide film 18 and a nitride film 19 are sequentially grown.

Next, using a normal photolithography technique, using the resist 1- (not shown) as a mask layer, the nitride film 19, the oxide film 18, the second silicon substrate 5, and the oxide film 3 are selectively formed.
A hole is opened in a portion (approximately 5 Pm) of the first silicon substrate 1, and a trench is formed in the first silicon substrate 1.9 Then, the resist is removed. A chemical vapor deposition oxide film is then grown. Next, anisotropic tri-etching is performed to fill the first trench with a chemical vapor grown oxide film 7.

FIG. 3(C) Next, using a resist (not shown) as a mask layer, the nitride film 1 is selectively deposited using a normal photolithography technique.
9. A hole is opened in the oxide film 18 in the n-type second silicon substrate 5, and a second I-wrench reaching the p-type impurity region 4 is formed. Next, the resist 1 is removed. Next, a chemical vapor phase epitaxial oxide film is grown. Next, anisotropic dry etching is performed to form a chemical vapor phase grown oxide film 8 on the sidewalls of the second trench.

FIG. 3 ((1) Next, using the oxide film 7, oxide film 8, and nitride film 19 as mask layers, holes are selectively formed in the second silicon substrate 5 and the oxide film 3 including the 10-shaped impurity region 4. , n. A third trench reaching the + type first impurity region 2 is formed.

FIG. 3(e) Next, a selective chemical vapor deposition tungsten film 9 is grown,
Fill the second and third trenches, then nitride film 19
, the oxide film 18 is removed by etching.

Next, using a normal photolithography technique and using the resist 1- (not shown) as a mask layer, arsenic ions are implanted to form an n-type second silicon substrate 5 which will become a contact region of the n--type second silicon substrate 5. The impurity regions 6 are selectively formed. Next, the resist I is removed.

FIG. 1 Next, by applying conventional techniques, an oxide film 10 for impurity blocking and a phosphosilicate glass (PSG) film 11 are grown, impurity regions are controlled by high-temperature heat treatment, and electrode contact I is formed.
・The semiconductor protection circuit device is completed by forming windows, forming the A1 wiring 12, forming the back AH electrode 13, etc.

As shown in the embodiments above, according to the semiconductor protection circuit device of the present invention, a protection device consisting of two forward-operating PN junction diodes with opposite operating directions formed on a semiconductor substrate and a bonded SOI substrate, respectively. The protection consists of two PN junction diodes with opposite operating directions connected in parallel, regardless of the surface layout, i.e. without reducing the degree of integration. The ability to form a protection device with equal strength against positive and negative high voltage noise provides high reliability, and the ability to form a protection device under an element with an SOI structure provides two PN junction diodes. Since it is possible to form a protective device with large resistance and capacitance without requiring any surface area other than the connecting portion, it is possible to achieve high integration and high reliability with excellent protection characteristics.

[Effects of the Invention] As described above, according to the present invention, in MIS and bipolar semiconductor integrated circuits, a protection device consisting of two forward-operating PN junction diodes with opposite operating directions can be formed three-dimensionally. Integration, and high reliability due to the ability to form a protection device with equal strength against positive and negative high voltage noise without reducing the degree of integration.
Furthermore, high integration and high reliability can be achieved by forming a protection device with large resistance and capacitance under the element of the SOI structure. That is, it is possible to obtain a semiconductor protection circuit device that enables the formation of extremely highly integrated and highly reliable semiconductor integrated circuits.

[Brief explanation of drawings]

FIGS. 1(a) and (11) are schematic diagrams of a first embodiment of a semiconductor protection circuit device of the present invention, and FIGS. 2(a) and (b) are schematic diagrams of a second embodiment of a semiconductor protection circuit device of the present invention. 3(a) to 3(e) are process cross-sectional views of an embodiment of the manufacturing method for the semiconductor protection circuit device of the present invention, and FIG. 4(a) is a schematic diagram of FIG.
(1)) is a schematic diagram of a conventional semiconductor protection circuit device. In the figure, 1 is a p-type first silicon substrate, 2 is an n-type first impurity region, 3 is an oxide film, 4 is a p-type impurity region, and 5 is an n-type second silicon substrate. substrate; 6 is an n-type second impurity region; 7j is the first trench-embedded insulating film; 8j is the second trench sidewall insulating film; 9i is the second and third trench-embedded conductive film;
Oxide film for impurity blocking, 11 phosphosilicate glass (PSG) film, 12j Al wiring, 13. ．． tAu electrode, 14 is input/output terminal, 15 is V. 0 (power supply voltage), 16 indicates Vs5 (ground voltage), and 17 indicates an input/output circuit section.

Claims (1)

[Claims] A semiconductor device in which a second semiconductor substrate having an opposite conductivity type is bonded onto a first semiconductor substrate having one conductivity type via an insulating film, the semiconductor device being provided on the upper surface of the first semiconductor substrate. , an impurity region of opposite conductivity type forming the first semiconductor substrate and a first PN junction diode, and an impurity region provided on the lower surface of the second semiconductor substrate, forming the second semiconductor substrate and the second PN junction diode. 1. A semiconductor protection circuit device, wherein the semiconductor protection circuit device is connected to an impurity region of one conductivity type forming a semiconductor protection circuit, and is provided between an input terminal and an input circuit or between an output terminal and an output circuit.