JPH03217053A - Resistor - Google Patents
ResistorInfo
- Publication number
- JPH03217053A JPH03217053A JP2012275A JP1227590A JPH03217053A JP H03217053 A JPH03217053 A JP H03217053A JP 2012275 A JP2012275 A JP 2012275A JP 1227590 A JP1227590 A JP 1227590A JP H03217053 A JPH03217053 A JP H03217053A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- channel thin
- film transistor
- polycrystalline
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置中等に形成される抵抗体
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resistor formed in a semiconductor integrated circuit device or the like.
本発明は、上記の様な抵抗体において、電流の温度依存
特性が互いに逆であるnチャネル薄膜トランジスタとp
チャネル薄膜トランジスタとを接続して抵抗体を構成す
ることによって、抵抗僅の温度依存性を小さくしたもの
である。The present invention provides an n-channel thin film transistor and a p-channel thin film transistor whose current temperature dependence characteristics are opposite to each other in the resistor as described above.
By connecting a channel thin film transistor to form a resistor, the temperature dependence of the resistance can be reduced.
半導体集積回路装置中等の抵抗体は、一般に多結晶St
膜によって構成されており、その他にMOSトランジス
タ等によって構成されている場合もある。Resistors in semiconductor integrated circuit devices are generally made of polycrystalline St.
It is composed of a film, and may also be composed of a MOS transistor or the like.
ところで、MOS−SRAMの負荷用の抵抗体としては
MΩ程度の高抵抗が要求され、バイボーラデバイスでも
kΩ程度の高抵抗がしばしば要求される。Incidentally, a resistor for a load in a MOS-SRAM is required to have a high resistance on the order of MΩ, and a bibolar device is often required to have a high resistance on the order of kΩ.
一方、多結晶Stは半導体であるので、伝導帯の下端の
エネルギをEC、フェルミ準位をErとすると、抵抗値
Rは、
R=Ro exp { (Ec −Er ) /kT
)と表わされる。On the other hand, since polycrystalline St is a semiconductor, if the energy at the lower end of the conduction band is EC and the Fermi level is Er, then the resistance value R is R=Ro exp { (Ec - Er ) /kT
).
このため、高抵抗を得るためには、E,を禁制帯の中央
付近に位置させてEC−Efを大きくする必要がある。Therefore, in order to obtain high resistance, it is necessary to position E near the center of the forbidden band and increase EC-Ef.
しかし、EC−E,を大きくすると、上記の式からも明
らかな様に、抵抗値Rの温度依存性が大きくなる。従っ
て、多結晶St膜では、高抵抗で且つ抵抗値の温度依存
性の小さな抵抗体を構成することが原理的に困難であり
、設計上及び動作上のマージンが小さい。However, as EC-E increases, the temperature dependence of the resistance value R increases, as is clear from the above equation. Therefore, with a polycrystalline St film, it is theoretically difficult to construct a resistor with high resistance and low temperature dependence of resistance value, and the design and operational margins are small.
また、MOS}ランジスタでは、その相互コンダクタン
スgイは移動度μに比例するが、単結晶Siの移動度は
音響形格子振動による散乱の影響を大きく受ける。この
ため、温度が高くなれば移動度及び相互コンダクタンス
が小さくなって抵抗値が高くなり、多結晶Si膜とは逆
特性ではあるが、やはり温度依存性が大きい。Furthermore, in a MOS transistor, its mutual conductance g is proportional to its mobility μ, but the mobility of single crystal Si is greatly affected by scattering due to acoustic lattice vibration. Therefore, as the temperature increases, the mobility and mutual conductance decrease and the resistance value increases, and although this is the opposite characteristic to that of a polycrystalline Si film, it still has a large temperature dependence.
本発明による抵抗体は、電流の温度依存特性が互いに逆
であるnチャネル薄膜トランジスタとpチャネル薄膜ト
ランジスタとが接続されて成っている。The resistor according to the present invention is formed by connecting an n-channel thin film transistor and a p-channel thin film transistor whose current temperature dependence characteristics are opposite to each other.
本発明による抵抗体では、nチャネル薄膜トランジスタ
とpチャネル薄膜トランジスタとで電流の温度依存性が
相殺される。In the resistor according to the present invention, the temperature dependence of current is canceled out between the n-channel thin film transistor and the p-channel thin film transistor.
以下、本発明の実施例を第1図及び第2図を参照しなが
ら説明する。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.
本実施例は、樹枝状(デンドライト)多結晶St膜を能
動層とするnチャネル及びpチャネル薄膜トランジスタ
を形成し、これらの薄膜トランジスタを第IA図または
第IB図の様に接続したものである。In this embodiment, n-channel and p-channel thin film transistors having a dendrite polycrystalline St film as an active layer are formed, and these thin film transistors are connected as shown in FIG. IA or FIG. IB.
樹枝状多結晶St膜を形成するには、通常の多結晶Si
膜にSt”をイオン注入して非品質化するか、または低
温で当初から非晶質St膜を形成し、これらの非晶質S
i膜を600゜C程度の低温でアニールして固相成長さ
せる。To form a dendritic polycrystalline St film, ordinary polycrystalline Si
Either ion-implanting St'' into the film to make it non-quality, or forming an amorphous St film from the beginning at a low temperature,
The i-film is annealed at a low temperature of about 600°C to grow in a solid phase.
樹枝状多結晶Siでは、通常の多結晶Stよりも、粒径
が大きく且つ粒界の電気性特性も改善されているので、
トラップが少ない。このため、樹技状多結晶Siは単結
晶Siと通常の多結晶Stとの中間的な性質を有してい
る。Dendritic polycrystalline Si has a larger grain size and improved grain boundary electrical properties than normal polycrystalline St.
There are fewer traps. Therefore, dendritic polycrystalline Si has properties intermediate between single crystal Si and normal polycrystalline St.
ところで、既述の様に、単結晶Siの移動度は音響形格
子振動による散乱の影響を大きく受けるので、温度が高
くなれば移動度が小さくなる。By the way, as mentioned above, the mobility of single-crystal Si is greatly affected by scattering due to acoustic lattice vibrations, so the higher the temperature, the lower the mobility.
これに対して、通常の多結晶Siではトラップが多いの
で、その移動度はイオン化不純物による散乱の影響を大
きく受ける。このため、温度が高くなれば移動度は大き
くなる。On the other hand, since ordinary polycrystalline Si has many traps, its mobility is greatly affected by scattering by ionized impurities. Therefore, the higher the temperature, the higher the mobility.
しかし、上述の様に樹枝状多結晶Siは単結晶Siと通
常の多結晶Stとの中間的な性質を有しているので、そ
の移動度は温度依存性自体が小さい。However, as described above, dendritic polycrystalline Si has properties intermediate between single-crystal Si and normal polycrystalline St, so its mobility itself has small temperature dependence.
第2図は、本実施例の様に樹枝状多結晶St膜を能動層
とし、ゲート幅及びゲート長が夫々20μm及び7μm
であるnチャネル薄膜トランジスタと、ゲート幅及びゲ
ート長が夫々40μm及び7μmであるpチャネル薄膜
トランジスタとの、電流の温度依存特性を示している。Figure 2 shows a case where a dendritic polycrystalline St film is used as the active layer as in this example, and the gate width and gate length are 20 μm and 7 μm, respectively.
2 shows the temperature dependence characteristics of the current of an n-channel thin film transistor with a gate width and a p-channel thin film transistor with a gate width of 40 μm and a gate length of 7 μm, respectively.
この第2図から明らかな様に、nチャネル薄膜トランジ
スタでは通常の多結晶Si膜を能動層とした場合の特性
が若干残っており、pチャネル薄膜トランジスタでは単
結晶Si基板を用いた場合の特性が若干現れているが、
電流依存性自体は共に小さい。As is clear from Figure 2, the characteristics of the n-channel thin film transistor when using a normal polycrystalline Si film as the active layer remain slightly, and the characteristics of the p-channel thin film transistor when using a single crystal Si substrate remain slightly. Although it is appearing,
The current dependence itself is small.
従って、第1図に示した本実施例では、nチャネル薄膜
トランジスタとpチャネル薄膜トランジスタとで電流の
温度依存性が相殺され、全体の抵抗値の温度依存性が非
常に小さい。Therefore, in this embodiment shown in FIG. 1, the temperature dependence of the current is canceled out between the n-channel thin film transistor and the p-channel thin film transistor, and the temperature dependence of the overall resistance value is extremely small.
また、薄膜トランジスタの能動層を構成している樹枝状
多結晶Si膜の膜厚を薄くする程、単位面積当りの見掛
のトラップが少なくなるので、抵抗値の温度依存性を小
さくするのに効果的である。In addition, the thinner the dendritic polycrystalline Si film that constitutes the active layer of the thin film transistor, the fewer the apparent traps per unit area, which is effective in reducing the temperature dependence of resistance. It is true.
以上の様な本実施例の抵抗体の抵抗値を調整するには、
例えば、ゲート長を一定にしておき、ゲート幅を変動さ
せることによって行う。To adjust the resistance value of the resistor of this example as described above,
For example, this is done by keeping the gate length constant and varying the gate width.
なお、ハイポーラデバイスではその製造プロセス中に薄
膜トランジスタの製造プロセスを含んでいないのでこの
プロセスを追加する必要があるが、MOS−SRAM等
の様に元々薄膜トランジスタの製造プロセスを含んでい
る場合はプロセスは従来通りでよい。Note that this process must be added because hyperpolar devices do not include the thin film transistor manufacturing process in their manufacturing process, but if they originally include the thin film transistor manufacturing process, such as MOS-SRAM, the process is It's fine as usual.
本発明による抵抗体では、nチャネル薄膜トランジスタ
とpチャネル薄膜トランジスタとで電流の温度依存性が
相殺されるので、抵抗値の温度依存性が小さい。In the resistor according to the present invention, the n-channel thin film transistor and the p-channel thin film transistor cancel out the temperature dependence of the current, so the temperature dependence of the resistance value is small.
第1図は本発明の実施例の回路図、第2図は樹枝状多結
晶Si膜を能動層とするnチャネル及びpチャネル薄膜
トランジスタの電流の温度依存特性を示すグラフである
。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a graph showing the temperature dependence characteristics of current of n-channel and p-channel thin film transistors having a dendritic polycrystalline Si film as an active layer.
Claims (1)
ランジスタとpチャネル薄膜トランジスタとが接続され
て成る抵抗体。A resistor formed by connecting an n-channel thin film transistor and a p-channel thin film transistor whose current temperature dependence characteristics are opposite to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012275A JP2881894B2 (en) | 1990-01-22 | 1990-01-22 | Resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012275A JP2881894B2 (en) | 1990-01-22 | 1990-01-22 | Resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03217053A true JPH03217053A (en) | 1991-09-24 |
| JP2881894B2 JP2881894B2 (en) | 1999-04-12 |
Family
ID=11800817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012275A Expired - Lifetime JP2881894B2 (en) | 1990-01-22 | 1990-01-22 | Resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2881894B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0595648A1 (en) * | 1992-10-30 | 1994-05-04 | Sharp Kabushiki Kaisha | A thin-film transistor circuit having a load device and a driver transistor and a method of producing the same |
-
1990
- 1990-01-22 JP JP2012275A patent/JP2881894B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0595648A1 (en) * | 1992-10-30 | 1994-05-04 | Sharp Kabushiki Kaisha | A thin-film transistor circuit having a load device and a driver transistor and a method of producing the same |
| US5471070A (en) * | 1992-10-30 | 1995-11-28 | Sharp Kabushiki Kaisha | Thin-film transistor circuit having an amorphous silicon load and a driver transistor and a method of producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2881894B2 (en) | 1999-04-12 |
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