JPH03217054A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] -3- The present invention relates to a semiconductor integrated circuit device, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit device having a memory circuit.

[Conventional technology]

A memory cell that stores information in an ultraviolet 111AM erasable non-volatile memory (EFROM) is composed of a field effect transistor. This field effect transistor is mainly composed of an information storage gate electrode (floating gate electrode), a control gate electrode (control gate electrode), a source region, and a drain region.

In the case of an EPROM employing a horizontal structure (parallel structure), memory cells are arranged at the intersections of a plurality of word lines and a plurality of data lines. The word line is integrally formed and electrically connected to the control gate electrodes of a plurality of individual memory cells (field effect transistors) arranged in the direction in which the word line extends.

The data line is electrically connected to the drain regions of a plurality of individual memory cells (field effect transistors) arranged in the direction in which the data line extends. The data line extends above the word line with an interlayer insulating film interposed therebetween, and is made of, for example, aluminum, which is a low resistance wiring material. The data line and the drain region of the memory cell are electrically connected through contact holes formed in the interlayer insulating film.

In this type of EPROM, it is necessary to ensure a mask alignment allowance in the manufacturing process, and it is difficult to reduce the area occupied by the memory cells and increase the degree of integration. In particular, the mask alignment margin secured between the control gate electrode (or word line) of the memory cell and the connection hole connecting the drain region of the memory cell and the data line hinders the degree of integration.

As a technology to solve such technical problems, IEDM 88, pages 432 to 435 (IEDM
88, pp. 432-435) is effective. This reported technology is used in EPROM.
Adjacent drain regions of a plurality of memory cells (field effect transistors) arranged in a direction intersecting a word line are formed integrally, and this is formed as a data line. The drain region is formed by ion implantation using the control gate electrode (or information storage gate electrode) as an impurity introduction mask, and is formed in self-alignment with the control gate electrode.

Therefore, the data line is formed in the drain region of the memory cell and is formed in self-alignment with the control gate electrode. In other words, the area occupied by the memory cell can be reduced by abolishing the above-mentioned mask alignment allowance, so the EPRO
M can improve the degree of integration.

[Problem to be solved by the invention]

The inventor has proposed an EPRO system that employs the above-mentioned reported technology.
It has been found that the following problems occur in M.

In the aforementioned EFROM, since the data line is formed in the drain region (semiconductor region or diffusion layer), the resistance value of the data line is significantly increased compared to conventional aluminum. An increase in the resistance value of the data line increases the charging/discharging time of the data line during an information read operation, thereby reducing the information read operation speed.

Further, in the aforementioned EPROM, since the data line is similarly formed in the drain region, a parasitic capacitance is formed at the pn junction between the drain region and the semiconductor substrate. Therefore, the parasitic capacitance is added to the data line, and the charging/discharging time of the data line becomes longer during the information read operation, thereby reducing the information read operation speed.

Further, in the above-mentioned EPROM, a source line is electrically connected to the source region of a memory cell (field effect transistor), and this source line is formed of a source region similarly to the data line. The source line has a high resistance value like the data line, and the potential of the source line rises during the information write operation (
(floating), it is not possible to secure a sufficient write potential difference. Therefore, the information writing characteristics of the memory cell deteriorate.

An object of the present invention is to provide a technique that can increase the operating speed of a memory circuit in a semiconductor integrated circuit device having a memory circuit.

Another object of the present invention is to provide a technique capable of increasing the speed of information read operation of the memory circuit in a semiconductor integrated circuit device having the memory circuit.

-7- Another object of the present invention is to provide a technique that can improve the information writing characteristics of a memory circuit in a semiconductor integrated circuit device having a memory circuit.

Another object of the present invention is to provide a technique that can improve the degree of integration in a semiconductor integrated circuit device having a memory circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows: 2. (1) A semiconductor having a memory circuit in which memory cells are arranged at the intersection of a data line and a word line. In integrated circuit devices,
The data line is buried in a groove formed from the main surface of the semiconductor substrate in the depth direction thereof with an insulating film interposed therebetween. This data line is formed of a metal film, a silicon film, or a metal silicide film. The memory circuit 18 is a mask ROM. EPROM or EEPROM
It is.

(2) In a semiconductor integrated circuit device having a memory circuit in which a memory cell constituted by a field effect transistor is arranged at an intersection of a data line, a source line, and a word line extending substantially parallel to each other, the data line , each of the source lines is buried in a trench formed from the main surface of the semiconductor substrate in the depth direction thereof with an insulating film interposed therebetween.

(3) In a semiconductor integrated circuit device having a memory circuit in which a memory cell formed of a field effect transistor is arranged at an intersection of a data line and a word line, the data line is
A trench formed from the main surface of the semiconductor substrate in the depth direction is buried with an insulating film interposed therebetween, and this data line is placed in the same conductive layer as one semiconductor region of the field effect transistor of the memory cell. It is composed of the following.

(4) In a method for manufacturing a semiconductor integrated circuit device having a memory circuit in which memory cells each composed of a field effect transistor are arranged at an intersection of a data line and a word line, the memory cells are arranged on the main surface of a semiconductor substrate. a step of forming a gate electrode of a field effect transistor constituting the semiconductor substrate; a step of forming a semiconductor region in self-alignment with the gate electrode on a main surface portion of at least one side surface of the gate electrode of the semiconductor substrate; forming a sidewall spacer on one side of the gate electrode in self-alignment with the gate electrode; interposing the sidewall spacer on the main surface of the one side of the gate electrode of the semiconductor substrate; forming a groove in the depth direction from the main surface in self-alignment with the gate electrode, embedding the data line with an insulating film interposed in the groove, and burying the data line in the electric field effect. and electrically connecting to the semiconductor region of the type transistor.

[For production]

According to the above-mentioned means (1), the cross-sectional area of the data line can be increased in the depth direction of the semiconductor substrate in the groove, and the resistance value of the data line can be reduced, so that the charging and discharging time of the data line can be shortened.
The operating speed of the memory circuit can be increased. Further, since the data line is covered with the insulator formed in the groove and the parasitic capacitance added to the data line can be reduced, the charging/discharging time of the data line can be shortened and the operating speed of the memory circuit can be increased.

According to the above-mentioned means (2), in addition to the effect of the above-mentioned means (1), the cross-sectional area of the source line can be increased in the depth direction of the semiconductor substrate by the groove, and the resistance value of the source line can be reduced. , it is possible to reduce the potential rise of the source line (reduce floating potential), increase the information writing potential difference, and improve the information writing characteristics of the memory circuit. Further, since the source line is covered with the insulator formed in the groove and the parasitic capacitance added to the source line can be reduced, potential rise in the source line can be reduced and information writing characteristics of the memory circuit can be improved.

According to the above-mentioned means (3), in addition to the effect of the above-mentioned means (1), the data line and the semiconductor region of one of the field effect transistors of the memory cell can be connected to each other without a mask alignment margin in the manufacturing process. Therefore, the area occupied by the memory cell can be reduced by the amount corresponding to this mask alignment allowance.
, the degree of integration can be improved.

According to the above-mentioned means (4), since the connection position between the semiconductor region of the field effect transistor and the data line is set in self-alignment with respect to the gate electrode of the field effect transistor, the connection position It is possible to eliminate the mask alignment allowance dimension in the manufacturing process of the gate electrode and the gate electrode.

Hereinafter, regarding the configuration of the present invention, an EP adopting a horizontal structure will be described.
An embodiment in which the present invention is applied to a ROM will be described.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example I) EPROM adopting a horizontal structure which is an example of the present invention
The schematic configuration of the device is shown in FIG. 1 (a cross-sectional view of the main part), FIG. 2 (a plan view of the main part), and FIG. 3 (a cross-sectional view of the main part).

1 is a sectional view including a cross section taken along the line I-1 in FIG. 2. FIG. 3 is a sectional view taken along line 1-12- of FIG. 2.

As shown in FIG. 1, the EPROM is composed of a p-type semiconductor substrate 1 made of single crystal silicon. A p-type well region 2 is formed on the main surface of each of the memory cell formation region and the n-channel MISFET formation region of this p-type semiconductor substrate 1. In addition, p-channel MISFE of p-type semiconductor substrate 1
An n-type well region 3 is formed on the main surface of the T-forming region.

As shown in FIG. 1, the memory cell array of the EPROM is constructed on the main surface of the P-type well region 2 within a defined region surrounded by the field insulating film 4 and the P-type channel stopper region 4A. Ru. This memory cell array has a memory cell Q that stores 1 [bit] of information.
A plurality of m are regularly arranged in a matrix.

As shown in FIGS. 1 to 3, the memory cell Qm has a p-type well region in a region whose periphery is defined by a p-type semiconductor region 25 for element isolation (mainly gate width dimensions are defined). It is constructed on the main surface of 2.

The memory cell Qm includes a p-type well region (channel formation region) 2, a gate l@rim film 5, an information storage gate electrode (floating gate electrode) 6, a gate insulating film 13, a control gate electrode (control gate electrode) 15, and a source. It is composed of a pair of n' type semiconductor regions 7 which are a region and a train region. In other words, the memory cell Qm is composed of an n-channel field effect transistor.

The control gate electrode 15 of the memory cell (field effect transistor) Qm is arranged in the gate length direction (vertical direction in FIG. 2).
It is constructed integrally with a word line (WL) 15 that extends to , and the two are electrically connected. In other words, the control gate electrode 15
, word line 15 are each made of the same conductive layer. The word line 15 is connected to each control gate electrode 15 of the plurality of memory cells Qm arranged in the gate length direction.

In the Go-type semiconductor region 7, which is the drain region of the memory cell Qm, there is a data line (DL) 1 extending in the gate width direction (in the left-right direction or the direction intersecting the word line 15 in FIG. 2).
0 is electrically connected. This data line 10 is connected to an n-type semiconductor region 7 which is an individual train region of a plurality of memory cells Qm arranged in the gate width direction.

Similarly, a source line (SL) 10 extending substantially parallel to the data line 10 is electrically connected to the d-type semiconductor region 7, which is the source region of the memory cell Qm.

This source line 10 is connected to an n-type semiconductor region 7 which is the individual source region of a plurality of memory cells Qm arranged in the gate width direction.

The data line 10 and the source line 10 are each buried in the trench 8 with an insulator 9 interposed therebetween. Groove 8 is formed in the main surface of p-type well region 2 in the depth direction from this main surface, and extends in the gate width direction with a substantially uniform trench width dimension. The trench 8 is formed by interposing an n° type semiconductor region 7 on the side surface portion of the information storage gate electrode 6 in the gate length direction of the memory cell Qm. This groove 8 is formed in the depth direction of the p-type well region 2.
The cross-sectional area of each of the data line 10 and the source line 10 can be increased.

Further, the insulator 9 is formed along the inner wall of the groove 8 . Insulator 9 electrically isolates p-type well region 2 and data line 10 or source line 10 buried in trench 8-15-. In other words, the insulator 9 has a structure in which no pn junction is formed between the P-type well region 2 and the data line 10 or the source line 10, and the parasitic capacitance formed at this pn junction is 10 or the source line 10. The n° type semiconductor region 7, which is the drain region of the memory cell Qm, and the data line 10 are each formed through a contact hole 11 formed by removing the insulator 9 in the upper part of the groove 8.
connected through. Similarly, the Go-type semiconductor region 7 serving as a source region and the source line 10 are connected through a connection hole 11, respectively.

The word line l5 is arranged around the memory cell array (
or at predetermined intervals in the extending direction of the word line 15). The wiring 24 is made of interlayer green films 21 and 2.
The word line 15 is connected to the word line 15 through a connection hole 23 formed in the word line 2 .

Although the system configuration of the EPROM is not shown, peripheral circuits such as a decoder circuit, an information write circuit, an information read circuit, etc. are composed of complementary MISFETs (CMOS)-16-. In other words, the complementary MISFET is composed of an n-channel MISFETQn and a p-channel MISFETQp.

As shown in FIG. 1, the n-channel MISFETQn
is formed on the main surface of the p-type well region 2 in a region defined by the field insulating film 4 and the p-type channel stopper region 4A.

In other words, the n-channel M I S F E T Q n mainly consists of the p-type well region 2, the gate insulating film 14, the gate electrode 15, the source region and the drain region.
It is composed of a type semiconductor region 16 and a pair of go-type semiconductor regions 19. This n-channel MISFETQn is located at i1 L
D D (Lightly Doped Drain
) consists of a structure. A wiring 24 is connected to one d-type semiconductor region 19 of the n-channel MISFETQn. The wiring 24 is connected to the go-shaped semiconductor region 19 through a connection hole 23 formed in the interlayer insulating film 22.

The p-channel MISFET QP is formed on the main surface of the n-type well region 3 in a region defined by field insulating film 4 . In other words, p-channel MISFETQ
P is mainly composed of an n-type well region 3, a gate insulating film 14, a gate electrode 15, a pair of p-type semiconductor regions 17 serving as source and drain regions, and a pair of p-type semiconductor regions 20. This p-channel MISFETQp has an LDD structure similar to the n-channel MISFETQn. A wiring 24 is connected to one p' type semiconductor region 20 of the p channel MISFET QP.

Next, a specific method for manufacturing the EFROM will be briefly explained using FIGS. 4 to 14 (cross-sectional views of main parts shown for each manufacturing process).

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, the memory cell Qm. of the EPROM. n channel M
In each formation region of IsFETQn, a p-type well region 2 is formed on the main surface of a p-type semiconductor substrate 1. After this, in the formation region of p-channel MISFETQp,
An n-type well region 3 is formed on the main surface of a p-type semiconductor substrate 1 .

Next, the memory cell Qm. n-channel MISFETQ
n. Between each P-channel MISFET QP, that is, in the inactive region, a p-type well region 2 and an n-type well region 3 are formed.
A field insulating film 4 is formed on each main surface. The field insulating film 4 is formed, for example, by a well-known selective thermal oxidation method. Furthermore, a p-type channel stopper region 4A is formed on the main surface of the p-type well region 2 under the field insulating film 4 by using substantially the same manufacturing process as that for forming the field insulating film 4.

Next, a gate insulating film 5 is formed on the main surface of the element formation region, that is, the active region of each of the p-type well region 2 and the n-type well region 3. The gate insulating film 5 is formed by, for example, a thermal oxidation method, and has a thickness of about 20 [nm].

Next, a conductive film 6 is deposited over the entire surface of the substrate including active regions and non-active regions. The conductive film 6 is formed of, for example, a polycrystalline silicon film deposited by the CVD method, and this polycrystalline silicon film has a thickness of about 200 [
nm].

Furthermore, an n-type impurity (P or As) is introduced into this polycrystalline silicon film to reduce the resistance value.

19 Next, as shown in FIG. 4, an insulating film 30 is formed on the entire surface of the conductive film 6. The insulating film 30 is formed of, for example, a silicon oxide film deposited by the CVD method, and this silicon oxide film has a thickness of about 400
It is formed with a film thickness of [nm].

Next, in the formation region of the memory cell array, the insulating film 3
0. Each conductive film 6 is sequentially patterned, and the shape of a part of the information storage gate electrode 6 is formed using the conductive film 6.

In other words, the patterning defines the gate length of the information storage gate electrode 6. This patterning is performed by, for example, anisotropic etching using a mask (for example, a photoresist film) formed by a well-known photolithography technique.

Further, this patterning is not performed in the element formation region of the peripheral circuit, and the conductive film 6 and the insulating film 30 remain in their deposited state.

Next, as shown in FIG. 5, in the formation region of the memory cell array, n
A type semiconductor region (source region and drain region) 7 is formed. The n-type semiconductor region 7 is, for example, I
15~5 X 1 0” [atoms/σ2] about -2
It is formed by introducing 0 A s (or P) by ion implantation with an energy of about 60 KeV.

When introducing As, the information storage gate electrode 6 and the insulating film 30 above it are used as an impurity introduction mask.

As a result, the n'-type semiconductor region 7 is formed in self-alignment with the information storage gate electrode 6.

Next, as shown in FIG. 6, sidewall spacers 31 are formed on the sidewalls of the information storage gate electrode 6. The sidewall spacer 31 is formed by depositing a silicon oxide film with a thickness of about 300 nm by CVD, and etching it by an amount corresponding to the thickness of the deposited silicon oxide film using anisotropic etching such as RIE. It is formed by

Next, as shown in FIG. 7, trenches 8 are formed in the formation region of the memory cell array. The groove 8 is formed by etching the main surface of the p-type well region 2 by anisotropic etching using the upper insulating film 30 of the information storage gate electrode 6 and the sidewall spacer 31 on the side wall as an etching mask. . The groove 8 is formed, for example, with a depth of about 1 to 3 [μm] and a groove width of about 0.5 to 0.8 [μm].

Note that the depth and groove width of the groove 8 are changed as appropriate in accordance with the respective resistance values of the data line (DL) and source line (SL) that are set. For example, if it is desired to reduce the resistance value of each of the data line and the source line and to reduce the occupied area, the depth of the groove 8 is increased and the groove width of the groove 8 is decreased.

Next, light etching is performed within the groove 8 for the purpose of removing etching damage or the like. The light etching is performed, for example, by isotropic etching using HF/HN○3. After this,
As shown in FIG. 8, an insulating film 9 and a conductive film 10 are sequentially laminated over the entire surface of the substrate including the surface of the p-type well region 2 exposed from within the groove 8. Insulating film 9 is formed in trench 8 to electrically isolate p-type well region 2 and conductive film 10 from each other. The insulating film 9 is formed of, for example, a silicon oxide film deposited by the CVD method, and this silicon oxide film has a thickness of, for example, about 50[n].
m]. Further, the insulating film 9 may be formed almost selectively within the groove 8 by a thermal oxidation method. Conductive film 10
are formed mainly to form data lines and source lines, respectively, and to fill the inside of the trench 8 and make the top of the trench 8 substantially flat. The conductive film 10 is formed of, for example, a polycrystalline silicon film deposited by a CVD method, and an n-type impurity is introduced into this polycrystalline silicon film to reduce the resistance value. This conductive film 10 has a thickness of about 200 to 400, for example.
It is formed with a film thickness of 0 [nm]. In addition to the polycrystalline silicon film, the conductive film 10 may also include a high melting point metal film (Mo, W, etc.),
It may be formed as a single layer such as a high melting point metal silicide film (MoStx, WSix, etc., where X is 2, for example), or a composite film in which such a metal film is laminated on a polycrystalline silicon film.

Next, the conductive film 10 is etched back by an amount corresponding to the thickness of the deposited film, so that the conductive film 10 remains only in the groove 8, and the conductive film 10 is used to form data lines (DL) 10, source lines (
SL) 10 are formed. In other words, the data line 10,
Each of the source lines 10 is embedded in the trench 8 in self-alignment with the trench 8. The etch back is performed by anisotropic etching such as RIE.

Next, as shown in FIG. 9, the entire surface of the insulating film 9 is etched to leave the insulating film 9 in the groove 8 and remove the remaining part of the insulating film 9.

Since this etching is performed with slight overetching, the insulating film 9 is etched on the upper side of the groove 8, that is, on the side surface portion of the go-shaped semiconductor region 7 exposed on the side wall of the groove 8.
A connection hole 1 through which a side surface of the Go-type semiconductor region 7 is exposed.
1 is formed.

Next, as shown in FIG. 10, a conductive film (not shown) is deposited again and this conductive film is etched back to remove the portion (connection A conductive film can be embedded in the hole 11 portion). This conductive film is integrally formed as a part of each of the data line 10 and source line 10, and electrically connects each of the data line 10 and source line 10 in the groove 8 to the square semiconductor region 7. do. The conductive film is, for example, a polycrystalline silicon film deposited by a CVD method, and the polycrystalline silicon film is formed to have a thickness of about 100 [nm]. In addition, n-type impurities are introduced into this polycrystalline silicon film in order to reduce the resistance value, but the n-type impurities are introduced from the surface side (
(ion implantation method or thermal diffusion method), -24 or from the lower layer data line 10 and source line 10 after deposition.

Next, a silicon oxide film with a thickness of about 20 [nm] is formed on the entire surface of the substrate by a thermal oxidation method, and then a silicon oxide film with a thickness of about 300 [nm] is deposited on the entire surface of the substrate by a CVD method. .

Then, a silicon oxide film or a photoresist film is coated on the entire surface of the silicon oxide film by the SOG method to flatten the surface.

Next, the surface of the silicon oxide film or photoresist film is etched back, and as shown in FIG. removed).

The interlayer insulating film 12 is formed to such an extent that the upper surface of the information storage gate electrode 12 is exposed, and as a result, it is buried between the information storage gate electrodes 6, and the surface is flattened.

Specifically, at least in the formation region of the memory cell array, a gate insulating film 1 is formed on the upper surface of the information storage gate electrode 6.
form 3. The gate insulating film 13 is, for example, a silicon oxide film formed by thermal oxidation on the surface of the information storage gate electrode 6, a silicon nitride film deposited by CVD, or a silicon oxide film formed by thermal oxidation on the surface of the silicon nitride film. It is formed from a composite film in which each layer is sequentially laminated. The silicon oxide film underlying this gate insulating film 13 is formed to have a thickness of about 3 [nm], for example. The silicon nitride film is formed to have a thickness of about 15 [nm], for example. Further, the thermal oxide film on the silicon nitride film is, for example, 5 [n
m].

Next, an etching mask (for example, a photoresist film) is formed in the area where the memory cell array will be formed, and as shown in FIG. 12, the remaining conductive film 6 and gate insulating film 5 in the area where the peripheral circuit will be formed are sequentially removed. and p-type well region 2, n
The main surface of each active region of type well region 3 is exposed.

Next, in the peripheral circuit formation region, the p-type well region 2
, a gate insulating film 14 is formed on the main surface of each active region of the n-type well region 3. For the gate insulating film 14, a silicon oxide film formed by, for example, a thermal oxidation method is used, and this silicon oxide film is formed to have a thickness of, for example, about 20 nm.

Next, a conductive film 15 is formed on the entire surface of the substrate including on the gate insulating film 13 and the gate insulating film 14. The conductive film 15 is made of, for example, a polycrystalline silicon film, a high melting point metal silicide film (for example, WS
It is formed of a laminated film in which each of ix) is sequentially laminated. The polycrystalline silicon film of the conductive film 15 is formed with a thickness of, for example, about 100 [nm], and the high melting point metal silicide film is formed with a thickness of, for example, about 150 [nm].
] is formed with a film thickness of .

Next, the conductive film 15 is patterned to form the shape of the #control gate electrode 15, word line (WL) 15, and other parts of the information storage gate electrode 6 in the memory cell array formation region, and to form peripheral circuits. A gate electrode 15 is formed in the region. The information storage gate electrode 6 is cut in an overlapping manner using the control gate electrode 15 as an etching mask to define the gate width. The word line 15 is
The surface of the underlying gate insulating film 13 is the interlayer insulating film 1
Since it is flattened by the flattening of step 2, it can be extended linearly (without a stepped shape) substantially in the plane direction. Through the process of forming the control gate electrode 15 and the information storage gate electrode 6, a memory cell Qm consisting of a field effect transistor 27 is completed.

Next, in the formation region of the memory cell array, the control gate electrode 15 and the information storage gate electrode 6 (or their etching masks) are used as impurity introduction masks, and as shown in FIGS. 2 and 3, A p' type semiconductor region 25 is formed on the main surface of the p type well region 2. p
The type semiconductor region 25 has, for example, 1013 atoms.
/an''] by introducing B by an ion implantation method.
0's are formed in self-alignment with each other.

Next, an n-type semiconductor region 16 is formed in the formation region of the n-channel MISFET of the peripheral circuit.

The n-type semiconductor region 16 is formed on the main surface of the p-type well region 2 on the side of the gate electrode 15, and is formed in self-alignment with the gate electrode 15. n-type semiconductor region 1
6, using the gate electrode 15 as an impurity introduction mask, for example, IQ 13 [atoms/an2] of P is ion-implanted with an energy of about 50 [KeV].
− Formed by introducing in an embedding manner.

Next, as shown in FIG. 13, the p-channel M of the peripheral circuit
A p-type semiconductor region 17 is formed in the ISFET formation region. The p-type semiconductor region 17 is formed on the main surface of the n-type well region 3 on the side of the gate electrode 15, and is formed in self-alignment with the gate electrode 15. The p-type semiconductor region 7 is formed by using the gate electrode 15 as an impurity introduction mask and introducing, for example, about 10" [atoms/an2] of BF2 by an ion implantation method with an energy of about 60 [KeV]. Ru.

Next, sidewall spacers 18 are formed on the sidewalls of the gate electrode 15 at least in the peripheral circuit formation region. The side wall spacer 18 is CVDed on the entire surface of the board.
The silicon oxide film is formed by depositing a silicon oxide film by a method and performing anisotropic etching on the silicon oxide film by an amount corresponding to the thickness of the deposited film. The surfaces of each of the n-type semiconductor region 16 and the p-type semiconductor region 17 are exposed by anisotropic etching during the formation of the sidewall spacer 18. Thereafter, a silicon oxide film (not shown) is formed over the entire surface of the substrate including the exposed surfaces of the n-type semiconductor region 16 and the p-type semiconductor region 17 by thermal oxidation or CVD.

Next, an n-type semiconductor region 19 is formed in the formation region of the n-channel MISFET of the peripheral circuit.

The green semiconductor region 19 is formed by ion implantation using, for example, an AS of about 10"-101G [atoms/cm2] and an energy of about 60 [KeV], using the gate electrode 15 and sidewall spacer l8 as an impurity introduction mask. By the process of forming the go-type semiconductor region 19, the n-channel MISFE
TQn is completed.

Next, as shown in FIG. 14, the p-channel M of the peripheral circuit
A final type semiconductor region 20 is formed in the ISFET formation region. The p-type semiconductor region 20 is formed using the gate electrode 15 and sidewall spacer 18 as an impurity introduction mask, for example, 10'' [atoms/LlII
It is formed by introducing BF2 of about 60 [KeV] by ion implantation with an energy of about 60 [KeV]. Through the step of forming this p° type semiconductor region 20, the p channel MISFET Qp is completed.

Next, an interlayer insulating film 22 is formed on the entire surface of the substrate, and then, as shown in FIGS.
4 are formed in sequence. For example, a BPSG film is used as the interlayer insulating film 22, and this BPSG film is deposited by a CVD method, and after forming the connection hole 22, glass flow is applied to flatten the surface. Glass flow is approximately 95
The test is carried out in a nitrogen gas atmosphere at 0°C. The wiring 24 is formed of, for example, an aluminum alloy (to which at least one of Cu, Si, etc. is added).

Next, although not shown, a final passivation film is formed on the entire surface of the substrate including on the wiring 24.
The EPROM of this embodiment (2) is completed.

In this way, the data line (DL) 10 and the word line (WL)
EPROM in which memory cell Qm is arranged at the intersection with 15
In this step, the data line 10 is buried in a groove 8 formed from the main surface of the p-type well region 2 (semiconductor substrate) in the depth direction thereof, with an insulating film 9 interposed therebetween. With this configuration, the cross-sectional area of the data line 10 is increased in the depth direction of the p-type well 31 region 2 in the groove 8,
Since the resistance value of the data line 10 can be reduced, the data line 10
The charging and discharging time of the EPROM can be shortened, and the operating speed of the EPROM, especially the information read operation speed, can be increased.

Further, the data line 10 is formed by the insulator 9 formed in the groove 8.
Since the parasitic capacitance added to the data line 10 can be reduced, especially compared to pn junction isolation, the charging/discharging time of the data line 10 can be shortened and the operating speed of the EPROM can be increased.

Further, at the intersection of the data line 10 and the source line (SL) 10 and the word line (WL05) extending substantially parallel to each other,
In an EPROM in which a memory cell Qm composed of a field effect transistor is arranged, each of the data line 10 and the source line 10 is formed in a groove formed from the main surface of the p-type well region 2 in the depth direction thereof. 8 with an insulating film 9 interposed therebetween. With this configuration, in addition to the above effects, the cross-sectional area of the source line 10 can be increased in the depth direction of the p-type well region 2 in the trench 8, and the resistance value of the source line 10 can be reduced. It is possible to reduce the potential rise (lower potential float), increase the information writing potential difference, and improve the information writing characteristics of the EPROM. In addition, since the source line 10 is covered with the insulating film 9 formed in the groove 8, the parasitic capacitance added to the SOS line 10 can be reduced, thereby reducing the potential rise of the source line 10 and improving the information writing characteristics of the EPROM. You can improve.

Further, in an EPROM in which a memory cell Qm constituted by a field effect transistor is arranged at the intersection of the data line 10 and the word line 15, the data line 10 is connected in the depth direction from the main surface of the p-type well region 2. An insulating film 9 is buried in the groove 8 formed toward the data line 10 .
is formed integrally with one n° type semiconductor region 7, which is the drain region of the field effect transistor of the memory cell Qm, in the same conductive layer. In other words, the upper side surface of the groove 8 of the Go-type semiconductor region 7 and the data line 10 can be considered to be the same conductive layer (through the connection hole 11), and the conductive film (10th They are electrically connected via a polycrystalline silicon film (as shown in the figure). With this configuration,
In addition to the above-mentioned effects, the data line 10 and the go-type semiconductor region 7 of one of the field effect transistors of the memory cell Qm can be connected without any margin for mask alignment in the manufacturing process.
The area occupied by the memory cell Qm can be reduced by an amount corresponding to this mask alignment margin, and the degree of integration of the EPROM can be improved.

Further, in an EPROM in which a memory cell Qm formed of a field effect transistor is arranged at the intersection of the data line 10 and the word line 15, on the main surface of the p-type well region 2,
The step of forming the information storage gate electrode 6 of the field effect transistor constituting the memory cell Qm (defining the gate length), and the step of forming the information storage gate electrode 6 on the main surface of the side surface portion of the information storage gate electrode 6 of the p-type well region 2. , forming an n° type semiconductor region (drain region) 7 in self-alignment with the information storage gate electrode 6; a step of forming a sidewall spacer 31; interposing the sidewall spacer 31 on the main surface of the side surface portion of the information storage gate electrode 6 of the p-type well region 2;
forming a groove 8 in a depth direction from the main surface in self-alignment with the information storage gate electrode 6; embedding the data line 10 with an insulating film 9 interposed in the groove 8; , a step of electrically connecting the data line 10 to the go-type semiconductor region 7 of the field effect transistor. With this configuration, the n° type semiconductor region 7 of the field effect transistor which is the memory cell Qm and the data line 1
Since the connection position with 0 is set in self-alignment with respect to the information storage gate electrode 6 of the field effect transistor,
The mask alignment allowance dimension in the manufacturing process between the connection position and the information storage gate electrode 6 can be eliminated. Note that these effects can be similarly achieved at the connection position between the source line 10 and the Go-type semiconductor region 7, which is the source region of the field effect transistor that is the memory cell Qm.

(Embodiment 3) Old Embodiment Embodiment 3 is a second embodiment of the present invention in which the data line and the source line are formed after the control gate electrode of the memory cell is formed in the EPROM.

FIG. 15 (a sectional view of a main part) shows a schematic structure of an EPROM adopting a horizontal structure, which is the present embodiment H.

The EPROM of this embodiment (2) has the same basic structure as that of the above embodiment (2), but the control gate electrode 15A of the field effect transistor which is the memory cell Qm and the word line 15 are each formed using a separate conductive layer. Consists of. The control gate electrode 15A is formed of, for example, a polycrystalline silicon film deposited by a CVD method, and an n-type impurity is introduced into this polycrystalline silicon film. The word line 15 is formed of, for example, W or WSix deposited by CVD or sputtering. Note that in reality, a part of the word line 15 is connected to the control gate electrode 15A, and the control gate electrode of the field effect transistor is connected to the control gate electrode 15A.
Consists of A and 15.

In addition, the n-channel MISFET of the peripheral circuit
Each of the Q n and p channel MISFET QP has a gate electrode 15A that is the same conductive layer as the control gate electrode 15A.
Consists of. Further, each of the go-type semiconductor region l9 of the n-channel MISFETQn and the p°-type semiconductor region 20 of the p-channel MISFET-36-Qp is connected to the word line 1.
It is connected to the wiring 24 with an intervening intermediate conductive film 15 which is the same conductive layer as 5.

Next, regarding the specific manufacturing method of the EPROM, FIGS. 16 to 23 (cross-sectional views of main parts shown for each manufacturing process)
Let's briefly explain using.

First, in the same manner as in Example 2, a p-type semiconductor substrate 1 is
A type well region 2 and an n-type well region 3 are each formed.

Thereafter, field insulating film 4, P-type channel stopper region 4A, and gate insulating film 5 are formed in sequence.

Next, as shown in FIG. 16, a conductive film 6 is formed in the formation region of the memory cell array. This conductive film 6 is formed almost over the entire surface of the memory cell array.

Next, a gate insulating film 13 is formed on the surface of the conductive film 6 in the memory cell array formation region, and a gate insulating film 14 is formed in the peripheral circuit formation region. Each of the gate insulating films 13 and 14 is formed in the same manufacturing process or in separate processes using, for example, a thermal oxidation method or a CVD method.

Next, as shown in FIG.
A conductive film 15A and an insulating film 30 are formed on the entire surface of the substrate including each of the upper parts of 4.
, respectively.

Next, in the formation region of the memory cell array, the insulating film 3
0. The conductive film 15A and the conductive film 6 are sequentially patterned to form the control gate electrode 15A and the information storage gate electrode 6, respectively. This patterning defines the gate lengths of the control gate electrode 15A and the information storage gate electrode 6, respectively. After that, in the peripheral circuit formation area, the insulating film 3
0. Each conductive film 15A is sequentially patterned to form a gate electrode 15A.

Next, as shown in FIG. 18, a Go-type semiconductor region 7 is formed in the memory cell array formation region, and an n-type semiconductor region 16 and a P-type semiconductor region 17 are formed in the peripheral circuit formation region, respectively.

Next, as shown in FIG. 19, the information storage gate electrode 6,
A sidewall spacer 31 is formed on each sidewall of the control gate electrode 15A and the gate electrode 15A.

Next, in substantially the same manner as in Example I, as shown in FIG. 20, trenches 8 are formed in the region where the memory cell array is to be formed. As shown in FIG. 20, the area where the peripheral circuit is to be formed is covered with an etching mask (for example, a photoresist film) 32.

Next, as shown in FIG. 21, an insulating film 9 is interposed in the groove 8 to form a data line 10 and a source line 10, respectively, and each of the data line 10 and source line 10 has an n° type. The semiconductor region 7 is connected to the semiconductor region 7.

Next, as shown in FIG. 22, a go-type semiconductor region 19 and a p-type semiconductor region 20 are sequentially formed in the peripheral circuit formation region. The n-channel MISFETQn is completed by the step of forming the n-type semiconductor region 19, and the p-channel MISFETQn is completed.
The p-channel M
ISFETQp is completed.

Next, in the same manner as in Example 2, an interlayer insulating film 12 is formed, and the upper surface of the control gate electrode 15A is exposed in the region where the memory cell array is to be formed. Further, in the region where the peripheral circuit is to be formed, connection holes (not provided with reference numerals) are formed in the interlayer insulation film 12.

Next, as shown in FIG. 23, word lines 15 are formed in the memory cell array formation region, and intermediate conductive films 15 are formed in the peripheral circuit formation region. In the memory cell array, the gate widths of the control gate electrode 15A and the information storage gate electrode 6 of the field effect transistor, which is the memory cell Qm, are defined by the same manufacturing process as the patterning process of the word line 15. By forming word line 15, memory cell Qm is completed.

Thereafter, the interlayer insulating film 22, connection hole 23, and wiring 24 are formed in sequence to complete the EFROM of this embodiment.

According to this embodiment H, substantially the same effects as those of the above-mentioned embodiment I can be achieved.

Although the invention made by the present inventor has been specifically explained based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. 140-, of course.

For example, the present invention provides a mask ROM. EEPROM. D.R.
A.M. It can be applied to semiconductor memory devices such as SRAM.

Further, the present invention is applicable to microcomputer LSIs and logic LSIs.
ROM installed in SI. It can be applied to RAM, etc.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a memory circuit, the operation speed of the memory circuit can be increased.

In a semiconductor integrated circuit device having a memory circuit, the information read operation speed of the memory circuit can be increased.

In a semiconductor integrated circuit device having a memory circuit, information writing characteristics of the memory circuit can be improved.

In a semiconductor integrated circuit device having a memory circuit, the degree of integration can be improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part showing a schematic configuration of an EPROM adopting a horizontal structure as an embodiment of the present invention, FIG. 2 is a plan view of a main part of a memory cell array of the previous EEPROM, and FIG. 4 to 14 are sectional views of essential parts of other regions of the memory cell array of the EPROM. FIGS. 4 to 14 are sectional views of essential parts showing each manufacturing process of the EPROM. FIG. EP adopting structure
16 to 2 are cross-sectional views of main parts showing the schematic structure of the ROM.
FIG. 3 is a sectional view of a main part of the EFROM showing each manufacturing process. In the figure, 1... semiconductor substrate, 2, 3... well region,
6, 15, 15A...gate electrode, 7, 1
6. 17, 19. 20...Semiconductor area, 8...
・Groove, 9...l@marginal membrane, 15...word line, 10・
. . . data line or source line, Qm . . . memory cell, Q n + Qp . . . MISFET. -43-

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a memory circuit in which memory cells are arranged at intersections between data lines and word lines, the data lines extend from the main surface of the semiconductor substrate in the depth direction thereof. 1. A semiconductor integrated circuit device characterized in that the semiconductor integrated circuit device is embedded in a groove formed by using an insulating film. 2. In a semiconductor integrated circuit device having a memory circuit in which a memory cell constituted by a field effect transistor is arranged at an intersection of a data line, a source line, and a word line extending substantially parallel to each other, the data line; A semiconductor integrated circuit device, wherein each of the source lines is embedded in a groove formed from the principal surface of the semiconductor substrate in the depth direction thereof with an insulating film interposed therebetween. 3. In a semiconductor integrated circuit device having a memory circuit in which a memory cell composed of a field effect transistor is arranged at an intersection between a data line and a word line, the data line extends from the main surface of the semiconductor substrate in the depth direction thereof. The data line is buried with an insulating film interposed in the groove formed toward the memory cell, and the data line is integrally formed in the same conductive layer as one semiconductor region of the field effect transistor of the memory cell. Features of semiconductor integrated circuit devices. 4. A method for manufacturing a semiconductor integrated circuit device having a memory circuit in which memory cells each formed of a field effect transistor are disposed at an intersection of a data line and a word line, wherein the memory cell is disposed on the main surface of a semiconductor substrate. a step of forming a gate electrode of a field-effect transistor comprising the semiconductor substrate; a step of forming a semiconductor region in self-alignment with the gate electrode on a main surface portion of at least one side surface of the gate electrode of the semiconductor substrate; forming a sidewall spacer on one side of the gate electrode in self-alignment with the gate electrode; interposing the sidewall spacer on the main surface of the one side of the gate electrode of the semiconductor substrate;
forming a groove in the depth direction from the main surface in self-alignment with the gate electrode, embedding the data line with an insulating film interposed in the groove, and exposing the data line to the electric field. 1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of electrically connecting to a semiconductor region of an effect transistor. 5. The semiconductor integrated circuit device according to each of claims 1 to 3, or claim 4, wherein the data line or the source line is formed of a metal film, a silicon film, or a metal silicide film. A method of manufacturing the semiconductor integrated circuit device described above. 6. Each of claims 1 to 3, wherein the memory cell constitutes a read-only nonvolatile memory circuit, an electrically erasable nonvolatile memory circuit, or an ultraviolet erasable nonvolatile memory circuit. Semiconductor integrated circuit device or claim 4
A method for manufacturing a semiconductor integrated circuit device according to .