JPH03217121A - Asynchronous counter device - Google Patents

Abstract

PURPOSE:To raise the frequency of countable input pulses by inputting the clock input and the output of a flip flop in the preceding stage to a gate circuit and inputting the output of the gate circuit to the clock input of a flip flop in the succeeding stage. CONSTITUTION:The clock input and the output of a T type flip flop T-FF 1 in the preceding stage are inputted to an AND circuit 5, and the output of the AND circuit is inputted to the clock input of a T-FF 6 in the succeeding stage. Then, the output of a T-FF 7 in the last stage is delayed in comparison with the input pulse by (the number of stages of the counter -1)XTA+TF where TA is the propagation delay time of the AND circuit and TF is that in one stage of T-FF. Consequently, the propagation delay time TA is made shorter than the propagation delay time TF to shorten the propagation delay of the output of the T-FF 7 in the last stage for the input pulse, and the frequency of countable input pulses is raised.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an asynchronous counter device that makes it possible to increase the operating frequency.

Conventional technology A conventional asynchronous counter device will be described below.

FIG. 3 shows a conventional asynchronous counter device, and FIG. 4 shows its operating waveforms. In FIG. 3, numerals 8 to 11 are T-type flip-flops (hereinafter referred to as T-FF) that operate at the falling edge of the clock input;
The output of the T-FF is coupled to the clock input of the next stage T-FF.

The operation of the conventional asynchronous counter device configured as described above will be described below.

First, it is assumed that the output voltages of all T-FFs are at low level. When the first falling edge of the input pulse I is input, the output J of the T-FF 8 changes from low level to high level. When the second falling edge is input, the output J of T-FF8 changes from high level to low level, and therefore the output K of T-FF9 changes from low level to high level. Thereafter, in the same way, the previous stage T-FF
When the output of the T-FF changes from high level to low level, the output of the subsequent T-FF is inverted, so that the input pulses I can be counted.

Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, since the T-FF of each stage is operated by the output of the T-FF of the preceding stage, the T-FF is
If the propagation delay time of one stage of FF is TF, then the final stage T
The output of -FF is delayed by (the number of counter stages) XTF with respect to the input pulse. Therefore, it has the disadvantage that the frequency of input pulses that can be counted is reduced.

The present invention solves the above-mentioned conventional problems, and aims to provide an asynchronous counter device that makes it possible to increase the frequency of input pulses that can be counted.

Means for Solving the Problems In order to achieve this object, the asynchronous counter device of the present invention, when connecting flip-flops that invert the output with a clock input in series, connects the clock input and output of the previous stage flip-flop. It has a configuration in which the input signal is input to a gate circuit, and the output of the gate circuit is input to the clock input of the next-stage flip-flop.

Effect: With this configuration, the propagation delay of the clock input to each stage of flip-flops is determined by the propagation delay of the gate circuit, and by making the propagation delay of the gate circuit smaller than the propagation delay of the flip-flop, the number of input pulses that can be counted is The frequency can be increased.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an asynchronous counter in an embodiment of the present invention.
FIG. 2 is a diagram of its operating waveforms. In Figure 1, 1~
4 is a T-FF that operates at the falling edge of the clock input, 5
7 are AND circuits which have the clock input and output of the T-FF in the previous stage as inputs, and input the output to the clock input of the T-FF in the next stage.

The operation of the asynchronous counter device configured as described above will be described below.

First, it is assumed that the output voltages of all T-FFs are at a low level. When the output voltage of the TFF in the previous stage is at a high level, the T-FF in each stage receives the clock input from the previous stage through an AND circuit, and the output voltage is inverted. - Therefore input pulses can be counted.

4 As described above, according to this embodiment, the clock input and output of the previous stage T-FF are input to the AND circuit, and the output of the AND circuit is input to the clock input of the next stage T-FF. Assuming that the propagation delay time of the circuit is T^, the output of the final stage T-FF is delayed by (number of counter stages - 1) x T80T'F with respect to the input pulse. Therefore, by setting TA<TP, it is possible to reduce the propagation delay of the output of the final stage T-FF with respect to the input pulse, and it is possible to increase the frequency of input pulses that can be counted.

Effects of the Invention As described above, the present invention inputs the clock input and output of the flip-flop in the previous stage to a gate circuit, and inputs the output of the gate circuit to the clock input of the flip-flop in the next stage, thereby generating input pulses that can be counted. This makes it possible to realize an excellent asynchronous counter device that can increase the frequency.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an asynchronous counter device according to an embodiment of the present invention, FIG. 2 is a timing chart of an asynchronous counter device according to an embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional asynchronous counter device. Circuit diagram of equation counter device, 4th
The figure is a timing chart diagram of a conventional asynchronous counter device. 1-4, 8-11...T-type flip-flop, 5-7...AND circuit.

Claims (1)

[Claims] An asynchronous counter device comprising a flip-flop whose output state is inverted by a clock input, two inputs coupled to the clock input and output of the flip-flop, and a gate circuit coupled to the clock input of the next-stage flip-flop.