JPH03217122A - Phase locked loop signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital phase synchronization signal generator for generating a signal synchronized with a reference phase.

2. Description of the Related Art A general phase synchronization signal generator has a configuration shown in FIG. The output signal (fo) of the VCOI is divided by the counter 2 to the frequency (fs) of the signal applied to the reference phase input signal application terminal, and the divided output (-L9-fs) is applied to the digital phase comparator 3. The reference phase input signal (b) is applied to one input terminal of N (al), and the reference phase input signal (b) is applied to the other input terminal. -NOR
The phases are compared by edge comparison such as the MC4044 manufactured by Motorola, and output signals e and f are obtained by the phase lead and lag of signals a and b, respectively. By charging and discharging the LPF 4 with the output signal of the digital phase comparator 3, an oscillation frequency control voltage of the VCO is obtained to form a loop, and the output signal of the VCO is synchronized with the reference phase.

Problems to be Solved by the Invention However, in the digital phase comparator 3 of the phase synchronized signal generator shown above, when the edges of both signals to be compared are very close to each other, the comparison output (es or f) is This results in a signal with an extremely narrow pulse width.

As a result, these pulses disappear when the LPF 4 is charged and discharged, phase error information cannot be transmitted, and a loop is no longer formed. As a result, the frequency and control voltage of the VCOI have characteristics as shown in FIG. 9, and the oscillation frequency of vC01, that is, the frequency of the phase synchronization signal is not stable.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention changes the digital phase comparator from an edge comparison type to a level comparison type.
This allows a stable comparison output to be obtained even when the edges of both signals to be compared match.

The output signal of the counter input to the operational digital phase comparator is a conventional window pulse signal having a constant width before and after the edge portion. This window pulse can be easily created by decoding the counter. Level comparison between this window pulse and the reference phase input signal is performed only within the window pulse to obtain a phase comparator output signal. Therefore, the signals for charging and discharging the LPF are output simultaneously within the window pulse. This phase comparison output signal may have a narrow pulse width at both ends of the window pulse, but
In that case, the other output signal always outputs a pulse with the maximum window width. Therefore, unlike the prior art, error information of narrow pulse widths does not disappear during charging and discharging of the LPF, and the loop does not become open.

Embodiment An embodiment of the present invention will be described with reference to the drawings of FIGS. 1 to 5. As shown in FIG. 1, this embodiment includes a VCOI, a counter 2 that divides the frequency of its output signal, a digital phase comparator 3, and an LPF 4.
o) The frequency (fs) of the signal applied to the reference phase input signal application terminal is divided by the counter 2, and the window pulse decoded by the divided output is input to one of the inputs of the digital phase comparator 3. Applied to the terminal (a
' s window), the reference phase input signal b is applied to the other input terminal. The LPF4 is charged and discharged by the outputs c and d of the digital phase comparison 3, and the LPF4
The output of the VCO1 is set as the frequency control voltage of the VCO1.
is giving feedback.

FIGS. 2 and 3 are operational timing diagrams of the digital phase comparator 3 of the embodiment shown in FIG. 1 constructed as described above, and FIG. 4 is a circuit configuration diagram thereof. In Figures 2 and 3, a
Conventionally, the signal shown by the broken line was applied from the counter 2 to the digital phase comparator 3. In the present invention, a window pulse having a constant width before and after the edge of a is input to the digital phase comparator 3. This window pulse is easily created by decoding the counter 2. The reference phase input signal is applied to the other input terminal of the digital phase comparator 3 as before.

The digital phase comparator 3 has a circuit configuration shown in FIG. 4, and the levels of the two signals are compared and outputted as output signals C and D. The LPF 4 is charged and discharged by the output signals C and D of the digital phase comparison 3, and the output is fed back to the VCOI as a control voltage. Even if the edges a and b in Figures 2 and 3 match,
Since each half of the window pulse is output as the output of the digital comparator 3, the pulse width does not become narrow and disappear. Therefore, the relationship between the output frequency of VCOI and the voltage of LPF4 is as shown in Figure 5,
There are no discontinuous points as in the conventional method.

Effects of the Invention As explained above, according to the present invention, the drawback of the VCO frequency fluctuation due to the disappearance of error output pulses, which existed in the conventional phase synchronization signal generation device using an edge comparison type digital phase comparator, can be eliminated. A stable phase synchronization signal generator for a VCO can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a phase synchronization signal generator according to an embodiment of the present invention, FIGS. 2 and 3 are operation timing diagrams of the 6 digital phase comparator, and FIG. 4 is a diagram of the operation timing of the digital phase comparator. A circuit configuration diagram, FIG. 5 is a diagram showing the relationship between the frequency of the VCO and the voltage of the LPF in FIG. 1,
Figure 6 is a circuit configuration diagram of a conventional phase synchronization signal generator, Figures 7 and 8 are timing diagrams of a conventional digital phase comparator, and Figure 9 shows the relationship between the frequency of a conventional VCO and the voltage of an LPF. FIG. 1...VC0, 2...Counter, 3.
...Digital phase comparator, 4...LP
F, 5...Reference phase input signal application terminal, 6...
...Phase synchronization signal output terminal, 7...Decoder.

Claims (1)

[Claims] It includes a VCO, a counter that divides its output signal, a digital phase comparator, and an LPF. At the frequency of the signal,
A pulse signal having a constant width is decoded, and its decode output terminal is connected to one input terminal of the digital phase comparator, and the other input terminal of the digital phase comparator is connected to a reference phase input signal application terminal. connected, the output of the digital phase comparator is applied to the LPF,
A phase synchronization signal generating device characterized in that an output terminal of the LPF is connected to a voltage control terminal of the VCO to form a loop.